Commit ca7c2b1b authored by ths's avatar ths
Browse files

Handle invalid accesses as SIGILL for mips/mipsel userland emulation.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2235 c046a42c-6fe2-441c-8c8c-71466251a162
parent 7d600c80
......@@ -1352,6 +1352,8 @@ void cpu_loop(CPUMIPSState *env)
}
}
break;
case EXCP_TLBL:
case EXCP_TLBS:
case EXCP_CpU:
case EXCP_RI:
info.si_signo = TARGET_SIGILL;
......
......@@ -243,6 +243,12 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
return ret;
}
#if defined(CONFIG_USER_ONLY)
void do_interrupt (CPUState *env)
{
env->exception_index = EXCP_NONE;
}
#else
void do_interrupt (CPUState *env)
{
target_ulong offset;
......@@ -409,3 +415,4 @@ void do_interrupt (CPUState *env)
}
env->exception_index = EXCP_NONE;
}
#endif /* !defined(CONFIG_USER_ONLY) */
......@@ -4072,6 +4072,7 @@ void cpu_reset (CPUMIPSState *env)
tlb_flush(env, 1);
/* Minimal init */
#if !defined(CONFIG_USER_ONLY)
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
* come back to the jump. */
......@@ -4098,9 +4099,11 @@ void cpu_reset (CPUMIPSState *env)
/* Count register increments in debug mode, EJTAG version 1 */
env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
env->CP0_PRid = MIPS_CPU;
#endif
env->exception_index = EXCP_NONE;
#if defined(CONFIG_USER_ONLY)
env->hflags |= MIPS_HFLAG_UM;
env->user_mode_only = 1;
#endif
#ifdef MIPS_USES_FPU
env->fcr0 = MIPS_FCR0;
......
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