Commit b8a9e8f1 authored by bellard's avatar bellard

initial user mmu support


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1270 c046a42c-6fe2-441c-8c8c-71466251a162
parent 4955a2cd
......@@ -24,8 +24,10 @@
#include "cpu-defs.h"
#define EXCP_UDEF 1 /* undefined instruction */
#define EXCP_SWI 2 /* software interrupt */
#define EXCP_UDEF 1 /* undefined instruction */
#define EXCP_SWI 2 /* software interrupt */
#define EXCP_PREFETCH_ABORT 3
#define EXCP_DATA_ABORT 4
typedef struct CPUARMState {
uint32_t regs[16];
......@@ -39,6 +41,9 @@ typedef struct CPUARMState {
int thumb; /* 0 = arm mode, 1 = thumb mode */
/* coprocessor 15 (MMU) status */
uint32_t cp15_6;
/* exception/interrupt handling */
jmp_buf jmp_env;
int exception_index;
......
......@@ -48,3 +48,6 @@ static inline void env_to_regs(void)
static inline void regs_to_env(void)
{
}
int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int is_user, int is_softmmu);
......@@ -424,6 +424,7 @@ static void disas_arm_insn(DisasContext *s)
gen_op_movl_T0_psr();
gen_movl_reg_T0(s, rd);
}
break;
case 0x1:
if (op1 == 1) {
/* branch/exchange thumb (bx). */
......@@ -1576,3 +1577,23 @@ target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
return addr;
}
#if defined(CONFIG_USER_ONLY)
int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int is_user, int is_softmmu)
{
env->cp15_6 = address;
if (rw == 2) {
env->exception_index = EXCP_PREFETCH_ABORT;
} else {
env->exception_index = EXCP_DATA_ABORT;
}
return 1;
}
#else
#error not implemented
#endif
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