Commit aa1f17c1 authored by ths's avatar ths
Browse files

Spelling fixes, by Stefan Weil.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3066 c046a42c-6fe2-441c-8c8c-71466251a162
parent 4a1a1707
......@@ -1295,7 +1295,7 @@ static int hdev_open(BlockDriverState *bs, const char *filename, int flags)
#if 0
/***********************************************/
/* removable device additionnal commands */
/* removable device additional commands */
static int raw_is_inserted(BlockDriverState *bs)
{
......
......@@ -421,7 +421,7 @@ extern int generic_symbol_at_address
/* Call this macro to initialize only the internal variables for the
disassembler. Architecture dependent things such as byte order, or machine
variant are not touched by this macro. This makes things much easier for
GDB which must initialize these things seperatly. */
GDB which must initialize these things separately. */
#define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
(INFO).fprintf_func = (FPRINTF_FUNC), \
......
......@@ -1248,12 +1248,12 @@ int gdbserver_start(int port)
return 0;
}
#else
static int gdb_chr_can_recieve(void *opaque)
static int gdb_chr_can_receive(void *opaque)
{
return 1;
}
static void gdb_chr_recieve(void *opaque, const uint8_t *buf, int size)
static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
{
GDBState *s = opaque;
int i;
......@@ -1304,7 +1304,7 @@ int gdbserver_start(const char *port)
}
s->env = first_cpu; /* XXX: allow to change CPU */
s->chr = chr;
qemu_chr_add_handlers(chr, gdb_chr_can_recieve, gdb_chr_recieve,
qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
gdb_chr_event, s);
qemu_add_vm_stop_handler(gdb_vm_stopped, s);
return 0;
......
......@@ -10,7 +10,7 @@ enum i2c_event {
I2C_START_RECV,
I2C_START_SEND,
I2C_FINISH,
I2C_NACK /* Masker NACKed a recieve byte. */
I2C_NACK /* Masker NACKed a receive byte. */
};
typedef struct i2c_slave i2c_slave;
......
......@@ -1567,7 +1567,7 @@ static void ide_atapi_cmd(IDEState *s)
buf[1] = 0x80; /* removable */
buf[2] = 0x00; /* ISO */
buf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */
buf[4] = 31; /* additionnal length */
buf[4] = 31; /* additional length */
buf[5] = 0; /* reserved */
buf[6] = 0; /* reserved */
buf[7] = 0; /* reserved */
......
......@@ -176,7 +176,7 @@ static void pl011_write(void *opaque, target_phys_addr_t offset,
}
}
static int pl011_can_recieve(void *opaque)
static int pl011_can_receive(void *opaque)
{
pl011_state *s = (pl011_state *)opaque;
......@@ -186,7 +186,7 @@ static int pl011_can_recieve(void *opaque)
return s->read_count < 1;
}
static void pl011_recieve(void *opaque, const uint8_t *buf, int size)
static void pl011_receive(void *opaque, const uint8_t *buf, int size)
{
pl011_state *s = (pl011_state *)opaque;
int slot;
......@@ -241,7 +241,7 @@ void pl011_init(uint32_t base, qemu_irq irq,
s->cr = 0x300;
s->flags = 0x90;
if (chr){
qemu_chr_add_handlers(chr, pl011_can_recieve, pl011_recieve,
qemu_chr_add_handlers(chr, pl011_can_receive, pl011_receive,
pl011_event, s);
}
/* ??? Save/restore. */
......
......@@ -160,7 +160,7 @@ static void pl181_send_command(pl181_state *s)
s->response[2] = RWORD(8);
s->response[3] = RWORD(12) & ~1;
}
DPRINTF("Response recieved\n");
DPRINTF("Response received\n");
s->status |= PL181_STATUS_CMDRESPEND;
#undef RWORD
} else {
......@@ -174,7 +174,7 @@ error:
s->status |= PL181_STATUS_CMDTIMEOUT;
}
/* Transfer data between teh card and the FIFO. This is complicated by
/* Transfer data between the card and the FIFO. This is complicated by
the FIFO holding 32-bit words and the card taking data in single byte
chunks. FIFO bytes are transferred in little-endian order. */
......
......@@ -790,7 +790,7 @@ static int rtl8139_can_receive(void *opaque)
RTL8139State *s = opaque;
int avail;
/* Recieve (drop) packets if card is disabled. */
/* Receive (drop) packets if card is disabled. */
if (!s->clock_enabled)
return 1;
if (!rtl8139_receiver_enabled(s))
......
......@@ -140,7 +140,7 @@ int usb_generic_handle_packet(USBDevice *s, USBPacket *p)
s->setup_state = SETUP_STATE_IDLE;
/* transfer OK */
} else {
/* ignore additionnal output */
/* ignore additional output */
}
break;
case SETUP_STATE_DATA:
......
......@@ -244,7 +244,7 @@ void host_to_target_siginfo(target_siginfo_t *tinfo, const siginfo_t *info)
}
/* XXX: we support only POSIX RT signals are used. */
/* XXX: find a solution for 64 bit (additionnal malloced data is needed) */
/* XXX: find a solution for 64 bit (additional malloced data is needed) */
void target_to_host_siginfo(siginfo_t *info, const target_siginfo_t *tinfo)
{
info->si_signo = tswap32(tinfo->si_signo);
......
......@@ -560,7 +560,7 @@ static char *const reg_names[] =
};
/* Name of register halves for MAC/EMAC.
Seperate from reg_names since 'spu', 'fpl' look weird. */
Separate from reg_names since 'spu', 'fpl' look weird. */
static char *const reg_half_names[] =
{
"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
......
......@@ -121,7 +121,7 @@
#define VIP_MASK 0x00100000
#define ID_MASK 0x00200000
/* hidden flags - used internally by qemu to represent additionnal cpu
/* hidden flags - used internally by qemu to represent additional cpu
states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid
using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
with eflags. */
......
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