Commit 970a87a6 authored by bellard's avatar bellard
Browse files

new segment access


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@255 c046a42c-6fe2-441c-8c8c-71466251a162
parent d8bc1fd0
...@@ -178,21 +178,21 @@ int cpu_exec(CPUState *env1) ...@@ -178,21 +178,21 @@ int cpu_exec(CPUState *env1)
/* we compute the CPU state. We assume it will not /* we compute the CPU state. We assume it will not
change during the whole generated block. */ change during the whole generated block. */
#if defined(TARGET_I386) #if defined(TARGET_I386)
flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT; flags = env->segs[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT;
flags |= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT; flags |= env->segs[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT;
flags |= (((unsigned long)env->seg_cache[R_DS].base | flags |= (((unsigned long)env->segs[R_DS].base |
(unsigned long)env->seg_cache[R_ES].base | (unsigned long)env->segs[R_ES].base |
(unsigned long)env->seg_cache[R_SS].base) != 0) << (unsigned long)env->segs[R_SS].base) != 0) <<
GEN_FLAG_ADDSEG_SHIFT; GEN_FLAG_ADDSEG_SHIFT;
if (!(env->eflags & VM_MASK)) { if (!(env->eflags & VM_MASK)) {
flags |= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT; flags |= (env->segs[R_CS].selector & 3) << GEN_FLAG_CPL_SHIFT;
} else { } else {
/* NOTE: a dummy CPL is kept */ /* NOTE: a dummy CPL is kept */
flags |= (1 << GEN_FLAG_VM_SHIFT); flags |= (1 << GEN_FLAG_VM_SHIFT);
flags |= (3 << GEN_FLAG_CPL_SHIFT); flags |= (3 << GEN_FLAG_CPL_SHIFT);
} }
flags |= (env->eflags & (IOPL_MASK | TF_MASK)); flags |= (env->eflags & (IOPL_MASK | TF_MASK));
cs_base = env->seg_cache[R_CS].base; cs_base = env->segs[R_CS].base;
pc = cs_base + env->eip; pc = cs_base + env->eip;
#elif defined(TARGET_ARM) #elif defined(TARGET_ARM)
flags = 0; flags = 0;
...@@ -347,13 +347,13 @@ void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) ...@@ -347,13 +347,13 @@ void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
if (env->eflags & VM_MASK) { if (env->eflags & VM_MASK) {
SegmentCache *sc; SegmentCache *sc;
selector &= 0xffff; selector &= 0xffff;
sc = &env->seg_cache[seg_reg]; sc = &env->segs[seg_reg];
/* NOTE: in VM86 mode, limit and seg_32bit are never reloaded, /* NOTE: in VM86 mode, limit and seg_32bit are never reloaded,
so we must load them here */ so we must load them here */
sc->base = (void *)(selector << 4); sc->base = (void *)(selector << 4);
sc->limit = 0xffff; sc->limit = 0xffff;
sc->seg_32bit = 0; sc->seg_32bit = 0;
env->segs[seg_reg] = selector; sc->selector = selector;
} else { } else {
load_seg(seg_reg, selector, 0); load_seg(seg_reg, selector, 0);
} }
...@@ -426,7 +426,7 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address, ...@@ -426,7 +426,7 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
return 0; return 0;
#if defined(TARGET_I386) #if defined(TARGET_I386)
env->eip = found_pc - tb->cs_base; env->eip = found_pc - tb->cs_base;
env->cr2 = address; env->cr[2] = address;
/* we restore the process signal mask as the sigreturn should /* we restore the process signal mask as the sigreturn should
do it (XXX: use sigsetjmp) */ do it (XXX: use sigsetjmp) */
sigprocmask(SIG_SETMASK, old_set, NULL); sigprocmask(SIG_SETMASK, old_set, NULL);
......
...@@ -176,7 +176,7 @@ void cpu_loop(CPUX86State *env) ...@@ -176,7 +176,7 @@ void cpu_loop(CPUX86State *env)
info.si_code = TARGET_SEGV_MAPERR; info.si_code = TARGET_SEGV_MAPERR;
else else
info.si_code = TARGET_SEGV_ACCERR; info.si_code = TARGET_SEGV_ACCERR;
info._sifields._sigfault._addr = env->cr2; info._sifields._sigfault._addr = env->cr[2];
queue_signal(info.si_signo, &info); queue_signal(info.si_signo, &info);
break; break;
case EXCP00_DIVZ: case EXCP00_DIVZ:
...@@ -231,7 +231,7 @@ void cpu_loop(CPUX86State *env) ...@@ -231,7 +231,7 @@ void cpu_loop(CPUX86State *env)
/* just indicate that signals should be handled asap */ /* just indicate that signals should be handled asap */
break; break;
default: default:
pc = env->seg_cache[R_CS].base + env->eip; pc = env->segs[R_CS].base + env->eip;
fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n", fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
(long)pc, trapnr); (long)pc, trapnr);
abort(); abort();
......
...@@ -828,7 +828,7 @@ void OPPROTO glue(glue(op_bsr, SUFFIX), _T0_cc)(void) ...@@ -828,7 +828,7 @@ void OPPROTO glue(glue(op_bsr, SUFFIX), _T0_cc)(void)
#define STRING_SUFFIX _a32 #define STRING_SUFFIX _a32
#define SI_ADDR (uint8_t *)A0 + ESI #define SI_ADDR (uint8_t *)A0 + ESI
#define DI_ADDR env->seg_cache[R_ES].base + EDI #define DI_ADDR env->segs[R_ES].base + EDI
#define INC_SI() ESI += inc #define INC_SI() ESI += inc
#define INC_DI() EDI += inc #define INC_DI() EDI += inc
#define CX ECX #define CX ECX
...@@ -837,7 +837,7 @@ void OPPROTO glue(glue(op_bsr, SUFFIX), _T0_cc)(void) ...@@ -837,7 +837,7 @@ void OPPROTO glue(glue(op_bsr, SUFFIX), _T0_cc)(void)
#define STRING_SUFFIX _a16 #define STRING_SUFFIX _a16
#define SI_ADDR (uint8_t *)A0 + (ESI & 0xffff) #define SI_ADDR (uint8_t *)A0 + (ESI & 0xffff)
#define DI_ADDR env->seg_cache[R_ES].base + (EDI & 0xffff) #define DI_ADDR env->segs[R_ES].base + (EDI & 0xffff)
#define INC_SI() ESI = (ESI & ~0xffff) | ((ESI + inc) & 0xffff) #define INC_SI() ESI = (ESI & ~0xffff) | ((ESI + inc) & 0xffff)
#define INC_DI() EDI = (EDI & ~0xffff) | ((EDI + inc) & 0xffff) #define INC_DI() EDI = (EDI & ~0xffff) | ((EDI + inc) & 0xffff)
#define CX (ECX & 0xffff) #define CX (ECX & 0xffff)
......
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