Add statics and missing #includes for prototypes.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3683 c046a42c-6fe2-441c-8c8c-71466251a162

audio/audio.c

@@ -238,7 +238,7 @@ static char *audio_alloc_prefix (const char *s)
     return r;
 }
 
-const char *audio_audfmt_to_string (audfmt_e fmt)
+static const char *audio_audfmt_to_string (audfmt_e fmt)
 {
     switch (fmt) {
     case AUD_FMT_U8:
@@ -264,7 +264,8 @@ const char *audio_audfmt_to_string (audfmt_e fmt)
     return "S16";
 }
 
-audfmt_e audio_string_to_audfmt (const char *s, audfmt_e defval, int *defaultp)
+static audfmt_e audio_string_to_audfmt (const char *s, audfmt_e defval,
+                                        int *defaultp)
 {
     if (!strcasecmp (s, "u8")) {
         *defaultp = 0;

block-vvfat.c

@@ -175,7 +175,7 @@ static inline int array_roll(array_t* array,int index_to,int index_from,int coun
     return 0;
 }
 
-inline int array_remove_slice(array_t* array,int index, int count)
+static inline int array_remove_slice(array_t* array,int index, int count)
 {
     assert(index >=0);
     assert(count > 0);
@@ -186,13 +186,13 @@ inline int array_remove_slice(array_t* array,int index, int count)
     return 0;
 }
 
-int array_remove(array_t* array,int index)
+static int array_remove(array_t* array,int index)
 {
     return array_remove_slice(array, index, 1);
 }
 
 /* return the index for a given member */
-int array_index(array_t* array, void* pointer)
+static int array_index(array_t* array, void* pointer)
 {
     size_t offset = (char*)pointer - array->pointer;
     assert(offset >= 0);

block.c

@@ -124,7 +124,7 @@ void path_combine(char *dest, int dest_size,
 }
 
 
-void bdrv_register(BlockDriver *bdrv)
+static void bdrv_register(BlockDriver *bdrv)
 {
     if (!bdrv->bdrv_aio_read) {
         /* add AIO emulation layer */

console.c

@@ -61,7 +61,7 @@ typedef struct QEMUFIFO {
     int count, wptr, rptr;
 } QEMUFIFO;
 
-int qemu_fifo_write(QEMUFIFO *f, const uint8_t *buf, int len1)
+static int qemu_fifo_write(QEMUFIFO *f, const uint8_t *buf, int len1)
 {
     int l, len;
 
@@ -84,7 +84,7 @@ int qemu_fifo_write(QEMUFIFO *f, const uint8_t *buf, int len1)
     return len1;
 }
 
-int qemu_fifo_read(QEMUFIFO *f, uint8_t *buf, int len1)
+static int qemu_fifo_read(QEMUFIFO *f, uint8_t *buf, int len1)
 {
     int l, len;
 

dyngen.c

@@ -232,7 +232,7 @@ enum {
 
 int do_swap;
 
-void __attribute__((noreturn)) __attribute__((format (printf, 1, 2))) error(const char *fmt, ...)
+static void __attribute__((noreturn)) __attribute__((format (printf, 1, 2))) error(const char *fmt, ...)
 {
     va_list ap;
     va_start(ap, fmt);
@@ -243,7 +243,7 @@ void __attribute__((noreturn)) __attribute__((format (printf, 1, 2))) error(cons
     exit(1);
 }
 
-void *load_data(int fd, long offset, unsigned int size)
+static void *load_data(int fd, long offset, unsigned int size)
 {
     char *data;
 

elf_ops.h

@@ -138,9 +138,9 @@ static int glue(load_symbols, SZ)(struct elfhdr *ehdr, int fd, int must_swab)
     return -1;
 }
 
-int glue(load_elf, SZ)(int fd, int64_t virt_to_phys_addend,
-                       int must_swab, uint64_t *pentry,
-                       uint64_t *lowaddr, uint64_t *highaddr)
+static int glue(load_elf, SZ)(int fd, int64_t virt_to_phys_addend,
+                              int must_swab, uint64_t *pentry,
+                              uint64_t *lowaddr, uint64_t *highaddr)
 {
     struct elfhdr ehdr;
     struct elf_phdr *phdr = NULL, *ph;

hw/arm_sysctl.c

@@ -8,7 +8,7 @@
  */
 
 #include "hw.h"
-#include "arm-misc.h"
+#include "primecell.h"
 #include "sysemu.h"
 
 #define LOCK_VALUE 0xa05f

hw/arm_timer.c

@@ -8,8 +8,8 @@
  */
 
 #include "hw.h"
-#include "arm-misc.h"
 #include "qemu-timer.h"
+#include "primecell.h"
 
 /* Common timer implementation.  */
 
@@ -43,7 +43,7 @@ static void arm_timer_update(arm_timer_state *s)
     }
 }
 
-uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
+static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
 {
     arm_timer_state *s = (arm_timer_state *)opaque;
 

hw/gt64xxx.c

@@ -908,7 +908,7 @@ static void pci_gt64120_set_irq(qemu_irq *pic, int irq_num, int level)
 }
 
 
-void gt64120_reset(void *opaque)
+static void gt64120_reset(void *opaque)
 {
     GT64120State *s = opaque;
 

hw/i8259.c

@@ -178,7 +178,7 @@ void pic_update_irq(PicState2 *s)
 int64_t irq_time[16];
 #endif
 
-void i8259_set_irq(void *opaque, int irq, int level)
+static void i8259_set_irq(void *opaque, int irq, int level)
 {
     PicState2 *s = opaque;
 

hw/ide.c

@@ -30,6 +30,7 @@
 #include "block.h"
 #include "qemu-timer.h"
 #include "sysemu.h"
+#include "ppc_mac.h"
 
 /* debug IDE devices */
 //#define DEBUG_IDE

hw/mc146818rtc.c

@@ -390,7 +390,7 @@ void rtc_set_date(RTCState *s, const struct tm *tm)
 #define REG_IBM_CENTURY_BYTE        0x32
 #define REG_IBM_PS2_CENTURY_BYTE    0x37
 
-void rtc_set_date_from_host(RTCState *s)
+static void rtc_set_date_from_host(RTCState *s)
 {
     time_t ti;
     struct tm *tm;
@@ -498,22 +498,22 @@ RTCState *rtc_init(int base, qemu_irq irq)
 }
 
 /* Memory mapped interface */
-uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
 {
     RTCState *s = opaque;
 
     return cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
 }
 
-void cmos_mm_writeb (void *opaque,
-                     target_phys_addr_t addr, uint32_t value)
+static void cmos_mm_writeb (void *opaque,
+                            target_phys_addr_t addr, uint32_t value)
 {
     RTCState *s = opaque;
 
     cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
 }
 
-uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
 {
     RTCState *s = opaque;
     uint32_t val;
@@ -525,8 +525,8 @@ uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
     return val;
 }
 
-void cmos_mm_writew (void *opaque,
-                     target_phys_addr_t addr, uint32_t value)
+static void cmos_mm_writew (void *opaque,
+                            target_phys_addr_t addr, uint32_t value)
 {
     RTCState *s = opaque;
 #ifdef TARGET_WORDS_BIGENDIAN
@@ -535,7 +535,7 @@ void cmos_mm_writew (void *opaque,
     cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
 }
 
-uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
 {
     RTCState *s = opaque;
     uint32_t val;
@@ -547,8 +547,8 @@ uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
     return val;
 }
 
-void cmos_mm_writel (void *opaque,
-                     target_phys_addr_t addr, uint32_t value)
+static void cmos_mm_writel (void *opaque,
+                            target_phys_addr_t addr, uint32_t value)
 {
     RTCState *s = opaque;
 #ifdef TARGET_WORDS_BIGENDIAN

hw/mcf_fec.c

@@ -251,7 +251,7 @@ static uint32_t mcf_fec_read(void *opaque, target_phys_addr_t addr)
     }
 }
 
-void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value)
+static void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value)
 {
     mcf_fec_state *s = (mcf_fec_state *)opaque;
     switch (addr & 0x3ff) {

hw/mips_malta.c

@@ -398,7 +398,7 @@ static CPUWriteMemoryFunc *malta_fpga_write[] = {
    malta_fpga_writel
 };
 
-void malta_fpga_reset(void *opaque)
+static void malta_fpga_reset(void *opaque)
 {
     MaltaFPGAState *s = opaque;
 
@@ -415,7 +415,7 @@ void malta_fpga_reset(void *opaque)
     malta_fpga_update_display(s);
 }
 
-MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
+static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
 {
     MaltaFPGAState *s;
     CharDriverState *uart_chr;

hw/ne2000.c

@@ -23,6 +23,7 @@
  */
 #include "hw.h"
 #include "pci.h"
+#include "pc.h"
 #include "net.h"
 
 /* debug NE2000 card */

hw/nvram.h

@@ -37,5 +37,6 @@ void m48t59_toggle_lock (void *private, int lock);
 m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
                        uint32_t io_base, uint16_t size,
                        int type);
+void m48t59_set_addr (void *opaque, uint32_t addr);
 
 #endif /* !NVRAM_H */

hw/omap.c

@@ -3041,7 +3041,7 @@ static CPUWriteMemoryFunc *omap_mpuio_writefn[] = {
     omap_badwidth_write16,
 };
 
-void omap_mpuio_reset(struct omap_mpuio_s *s)
+static void omap_mpuio_reset(struct omap_mpuio_s *s)
 {
     s->inputs = 0;
     s->outputs = 0;
@@ -3257,7 +3257,7 @@ static CPUWriteMemoryFunc *omap_gpio_writefn[] = {
     omap_badwidth_write16,
 };
 
-void omap_gpio_reset(struct omap_gpio_s *s)
+static void omap_gpio_reset(struct omap_gpio_s *s)
 {
     s->inputs = 0;
     s->outputs = ~0;
@@ -3429,7 +3429,7 @@ static CPUWriteMemoryFunc *omap_uwire_writefn[] = {
     omap_badwidth_write16,
 };
 
-void omap_uwire_reset(struct omap_uwire_s *s)
+static void omap_uwire_reset(struct omap_uwire_s *s)
 {
     s->control = 0;
     s->setup[0] = 0;
@@ -3470,7 +3470,7 @@ void omap_uwire_attach(struct omap_uwire_s *s,
 }
 
 /* Pseudonoise Pulse-Width Light Modulator */
-void omap_pwl_update(struct omap_mpu_state_s *s)
+static void omap_pwl_update(struct omap_mpu_state_s *s)
 {
     int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0;
 
@@ -3528,7 +3528,7 @@ static CPUWriteMemoryFunc *omap_pwl_writefn[] = {
     omap_badwidth_write8,
 };
 
-void omap_pwl_reset(struct omap_mpu_state_s *s)
+static void omap_pwl_reset(struct omap_mpu_state_s *s)
 {
     s->pwl.output = 0;
     s->pwl.level = 0;
@@ -3632,7 +3632,7 @@ static CPUWriteMemoryFunc *omap_pwt_writefn[] = {
     omap_badwidth_write8,
 };
 
-void omap_pwt_reset(struct omap_mpu_state_s *s)
+static void omap_pwt_reset(struct omap_mpu_state_s *s)
 {
     s->pwt.frc = 0;
     s->pwt.vrc = 0;
@@ -4037,7 +4037,7 @@ static void omap_rtc_tick(void *opaque)
     qemu_mod_timer(s->clk, s->tick);
 }
 
-void omap_rtc_reset(struct omap_rtc_s *s)
+static void omap_rtc_reset(struct omap_rtc_s *s)
 {
     s->interrupts = 0;
     s->comp_reg = 0;
@@ -4509,14 +4509,14 @@ struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
     return s;
 }
 
-void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
+static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
 {
     struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
 
     omap_mcbsp_rx_start(s);
 }
 
-void omap_mcbsp_i2s_start(void *opaque, int line, int level)
+static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
 {
     struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
 

hw/omap.h

@@ -662,6 +662,9 @@ struct omap_mpu_state_s {
 #  error TARGET_PHYS_ADDR_BITS undefined
 # endif
 
+uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
+void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
+                uint32_t value);
 uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
 void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
                 uint32_t value);

hw/omap_lcdc.c

@@ -114,7 +114,7 @@ static draw_line_func *draw_line_table2[33] = {
     [32]	= draw_line16_32,
 };
 
-void omap_update_display(void *opaque)
+static void omap_update_display(void *opaque)
 {
     struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
     draw_line_func *draw_line;
@@ -289,7 +289,7 @@ static int ppm_save(const char *filename, uint8_t *data,
     return 0;
 }
 
-void omap_screen_dump(void *opaque, const char *filename) {
+static void omap_screen_dump(void *opaque, const char *filename) {
     struct omap_lcd_panel_s *omap_lcd = opaque;
     omap_update_display(opaque);
     if (omap_lcd && omap_lcd->state->data)
@@ -298,12 +298,12 @@ void omap_screen_dump(void *opaque, const char *filename) {
                 omap_lcd->state->linesize);
 }
 
-void omap_invalidate_display(void *opaque) {
+static void omap_invalidate_display(void *opaque) {
     struct omap_lcd_panel_s *omap_lcd = opaque;
     omap_lcd->invalidate = 1;
 }
 
-void omap_lcd_update(struct omap_lcd_panel_s *s) {
+static void omap_lcd_update(struct omap_lcd_panel_s *s) {
     if (!s->enable) {
         s->dma->current_frame = -1;
         s->sync_error = 0;

hw/parallel.c

@@ -458,45 +458,45 @@ ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
 }
 
 /* Memory mapped interface */
-uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
 {
     ParallelState *s = opaque;
 
     return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFF;
 }
 
-void parallel_mm_writeb (void *opaque,
-                       target_phys_addr_t addr, uint32_t value)
+static void parallel_mm_writeb (void *opaque,
+                                target_phys_addr_t addr, uint32_t value)
 {
     ParallelState *s = opaque;
 
     parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFF);
 }
 
-uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
 {
     ParallelState *s = opaque;
 
     return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
 }
 
-void parallel_mm_writew (void *opaque,
-                       target_phys_addr_t addr, uint32_t value)
+static void parallel_mm_writew (void *opaque,
+                                target_phys_addr_t addr, uint32_t value)
 {
     ParallelState *s = opaque;
 
     parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
 }
 
-uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
 {
     ParallelState *s = opaque;
 
     return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift);
 }
 
-void parallel_mm_writel (void *opaque,
-                       target_phys_addr_t addr, uint32_t value)
+static void parallel_mm_writel (void *opaque,
+                                target_phys_addr_t addr, uint32_t value)
 {
     ParallelState *s = opaque;
 

hw/pc.c

@@ -317,7 +317,7 @@ static uint32_t ioport92_read(void *opaque, uint32_t addr)
 /***********************************************************/
 /* Bochs BIOS debug ports */
 
-void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
+static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 {
     static const char shutdown_str[8] = "Shutdown";
     static int shutdown_index = 0;
@@ -361,7 +361,7 @@ void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
     }
 }
 
-void bochs_bios_init(void)
+static void bochs_bios_init(void)
 {
     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
@@ -431,8 +431,8 @@ static void generate_bootsect(uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
     bdrv_set_boot_sector(bs_table[0], bootsect, sizeof(bootsect));
 }
 
-int load_kernel(const char *filename, uint8_t *addr,
-                uint8_t *real_addr)
+static int load_kernel(const char *filename, uint8_t *addr,
+                       uint8_t *real_addr)
 {
     int fd, size;
     int setup_sects;

hw/pci.c

@@ -65,7 +65,7 @@ PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
     return bus;
 }
 
-PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
+static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
 {
     PCIBus *bus;
     bus = qemu_mallocz(sizeof(PCIBus));
@@ -159,7 +159,7 @@ void pci_register_io_region(PCIDevice *pci_dev, int region_num,
     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 }
 
-target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
+static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 {
     return addr + pci_mem_base;
 }
@@ -606,7 +606,7 @@ typedef struct {
     PCIBus *bus;
 } PCIBridge;
 
-void pci_bridge_write_config(PCIDevice *d,
+static void pci_bridge_write_config(PCIDevice *d,
                              uint32_t address, uint32_t val, int len)
 {
     PCIBridge *s = (PCIBridge *)d;

hw/pckbd.c

@@ -290,7 +290,7 @@ static uint32_t kbd_read_data(void *opaque, uint32_t addr)
     return ps2_read_data(s->kbd);
 }
 
-void kbd_write_data(void *opaque, uint32_t addr, uint32_t val)
+static void kbd_write_data(void *opaque, uint32_t addr, uint32_t val)
 {
     KBDState *s = opaque;
 
@@ -385,7 +385,7 @@ void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base)
 }
 
 /* Memory mapped interface */
-uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
 {
     KBDState *s = opaque;
 
@@ -399,7 +399,7 @@ uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
     }
 }
 
-void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
 {
     KBDState *s = opaque;
 

hw/piix_pci.c

@@ -314,7 +314,7 @@ static int piix_load(QEMUFile* f, void *opaque, int version_id)
     return pci_device_load(d, f);
 }
 
-int piix_init(PCIBus *bus, int devfn)
+static int piix_init(PCIBus *bus, int devfn)
 {
     PCIDevice *d;
     uint8_t *pci_conf;

hw/pl061.c

@@ -209,7 +209,7 @@ static void pl061_reset(pl061_state *s)
   s->cr = 0xff;
 }
 
-void pl061_set_irq(void * opaque, int irq, int level)
+static void pl061_set_irq(void * opaque, int irq, int level)
 {
     pl061_state *s = (pl061_state *)opaque;
     uint8_t mask;

hw/pl190.c

@@ -216,7 +216,7 @@ static CPUWriteMemoryFunc *pl190_writefn[] = {
    pl190_write
 };
 
-void pl190_reset(pl190_state *s)
+static void pl190_reset(pl190_state *s)
 {
   int i;
 

hw/pxa2xx_lcd.c

@@ -882,7 +882,7 @@ static void pxa2xx_screen_dump(void *opaque, const char *filename)
     /* TODO */
 }
 
-void pxa2xx_lcdc_orientation(void *opaque, int angle)
+static void pxa2xx_lcdc_orientation(void *opaque, int angle)
 {
     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 

hw/pxa2xx_pcmcia.c

@@ -9,6 +9,7 @@
 
 #include "hw.h"
 #include "pcmcia.h"
+#include "pxa.h"
 
 struct pxa2xx_pcmcia_s {
     struct pcmcia_socket_s slot;

hw/realview_gic.c

@@ -8,7 +8,7 @@
  */
 
 #include "hw.h"
-#include "arm-misc.h"
+#include "primecell.h"
 
 #define GIC_NIRQ 96
 #define NCPU 1

hw/rtl8139.c

@@ -497,7 +497,7 @@ typedef struct RTL8139State {
 
 } RTL8139State;
 
-void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
+static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
 {
     DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
 
@@ -543,7 +543,7 @@ void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
     }
 }
 
-void prom9346_shift_clock(EEprom9346 *eeprom)
+static void prom9346_shift_clock(EEprom9346 *eeprom)
 {
     int bit = eeprom->eedi?1:0;
 
@@ -635,7 +635,7 @@ void prom9346_shift_clock(EEprom9346 *eeprom)
     }
 }
 
-int prom9346_get_wire(RTL8139State *s)
+static int prom9346_get_wire(RTL8139State *s)
 {
     EEprom9346 *eeprom = &s->eeprom;
     if (!eeprom->eecs)
@@ -644,7 +644,8 @@ int prom9346_get_wire(RTL8139State *s)
     return eeprom->eedo;
 }