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Xing Lin
qemu
Commits
83469015
Commit
83469015
authored
Jul 23, 2005
by
bellard
Browse files
sparc64 fixes (Blue Swirl)
git-svn-id:
svn://svn.savannah.nongnu.org/qemu/trunk@1514
c046a42c-6fe2-441c-8c8c-71466251a162
parent
b7c7b181
Changes
15
Hide whitespace changes
Inline
Side-by-side
Makefile.target
View file @
83469015
...
...
@@ -297,7 +297,10 @@ VL_OBJS+= mips_r4k.o dma.o vga.o serial.o ne2000.o i8259.o
endif
ifeq
($(TARGET_BASE_ARCH), sparc)
ifeq
($(TARGET_ARCH), sparc64)
VL_OBJS
+=
sun4u.o m48t08.o magic-load.o slavio_serial.o
VL_OBJS
+=
sun4u.o ide.o ne2000.o pckbd.o vga.o
VL_OBJS
+=
fdc.o mc146818rtc.o serial.o m48t59.o
VL_OBJS
+=
cirrus_vga.o parallel.o
VL_OBJS
+=
magic-load.o
else
VL_OBJS
+=
sun4m.o tcx.o lance.o iommu.o m48t08.o magic-load.o slavio_intctl.o slavio_timer.o slavio_serial.o slavio_misc.o fdc.o esp.o
endif
...
...
configure
View file @
83469015
...
...
@@ -153,6 +153,8 @@ for opt do
;;
--cc
=
*
)
cc
=
`
echo
$opt
|
cut
-d
'='
-f
2
`
;;
--host-cc
=
*
)
host_cc
=
`
echo
$opt
|
cut
-d
'='
-f
2
`
;;
--make
=
*
)
make
=
`
echo
$opt
|
cut
-d
'='
-f
2
`
;;
--extra-cflags
=
*
)
CFLAGS
=
"
${
opt
#--extra-cflags=
}
"
...
...
@@ -339,6 +341,7 @@ echo "Advanced options (experts only):"
echo
" --source-path=PATH path of source code [
$source_path
]"
echo
" --cross-prefix=PREFIX use PREFIX for compile tools [
$cross_prefix
]"
echo
" --cc=CC use C compiler CC [
$cc
]"
echo
" --host-cc=CC use C compiler CC [
$cc
] for dyngen etc."
echo
" --make=MAKE use specified make [
$make
]"
echo
" --static enable static build [
$static
]"
echo
" --enable-mingw32 enable Win32 cross compilation with mingw32"
...
...
@@ -420,6 +423,7 @@ echo "ELF interp prefix $interp_prefix"
fi
echo
"Source path
$source_path
"
echo
"C compiler
$cc
"
echo
"Host C compiler
$host_cc
"
echo
"make
$make
"
echo
"host CPU
$cpu
"
echo
"host big endian
$bigendian
"
...
...
hw/magic-load.c
View file @
83469015
...
...
@@ -139,7 +139,7 @@ int load_elf(const char *filename, uint8_t *addr)
if
(
find_phdr64
(
&
ehdr64
,
fd
,
&
phdr
,
PT_LOAD
))
goto
error
;
retval
=
read_program64
(
fd
,
&
phdr
,
addr
,
ehdr64
.
e_entry
);
retval
=
read_program64
(
fd
,
&
phdr
,
phys_ram_base
+
ehdr64
.
e_entry
,
ehdr64
.
e_entry
);
if
(
retval
<
0
)
goto
error
;
load_symbols64
(
&
ehdr64
,
fd
);
...
...
hw/pci.c
View file @
83469015
...
...
@@ -1291,6 +1291,253 @@ PCIBus *pci_pmac_init(void)
return
s
;
}
/* Ultrasparc APB PCI host */
static
void
pci_apb_config_writel
(
void
*
opaque
,
target_phys_addr_t
addr
,
uint32_t
val
)
{
PCIBus
*
s
=
opaque
;
int
i
;
for
(
i
=
11
;
i
<
32
;
i
++
)
{
if
((
val
&
(
1
<<
i
))
!=
0
)
break
;
}
s
->
config_reg
=
0x80000000
|
(
1
<<
16
)
|
(
val
&
0x7FC
)
|
(
i
<<
11
);
}
static
uint32_t
pci_apb_config_readl
(
void
*
opaque
,
target_phys_addr_t
addr
)
{
PCIBus
*
s
=
opaque
;
uint32_t
val
;
int
devfn
;
devfn
=
(
s
->
config_reg
>>
8
)
&
0xFF
;
val
=
(
1
<<
(
devfn
>>
3
))
|
((
devfn
&
0x07
)
<<
8
)
|
(
s
->
config_reg
&
0xFC
);
return
val
;
}
static
CPUWriteMemoryFunc
*
pci_apb_config_write
[]
=
{
&
pci_apb_config_writel
,
&
pci_apb_config_writel
,
&
pci_apb_config_writel
,
};
static
CPUReadMemoryFunc
*
pci_apb_config_read
[]
=
{
&
pci_apb_config_readl
,
&
pci_apb_config_readl
,
&
pci_apb_config_readl
,
};
static
void
apb_config_writel
(
void
*
opaque
,
target_phys_addr_t
addr
,
uint32_t
val
)
{
//PCIBus *s = opaque;
switch
(
addr
&
0x3f
)
{
case
0x00
:
// Control/Status
case
0x10
:
// AFSR
case
0x18
:
// AFAR
case
0x20
:
// Diagnostic
case
0x28
:
// Target address space
// XXX
default:
break
;
}
}
static
uint32_t
apb_config_readl
(
void
*
opaque
,
target_phys_addr_t
addr
)
{
//PCIBus *s = opaque;
uint32_t
val
;
switch
(
addr
&
0x3f
)
{
case
0x00
:
// Control/Status
case
0x10
:
// AFSR
case
0x18
:
// AFAR
case
0x20
:
// Diagnostic
case
0x28
:
// Target address space
// XXX
default:
val
=
0
;
break
;
}
return
val
;
}
static
CPUWriteMemoryFunc
*
apb_config_write
[]
=
{
&
apb_config_writel
,
&
apb_config_writel
,
&
apb_config_writel
,
};
static
CPUReadMemoryFunc
*
apb_config_read
[]
=
{
&
apb_config_readl
,
&
apb_config_readl
,
&
apb_config_readl
,
};
static
void
pci_apb_writeb
(
void
*
opaque
,
target_phys_addr_t
addr
,
uint32_t
val
)
{
PCIBus
*
s
=
opaque
;
pci_data_write
(
s
,
addr
&
7
,
val
,
1
);
}
static
void
pci_apb_writew
(
void
*
opaque
,
target_phys_addr_t
addr
,
uint32_t
val
)
{
PCIBus
*
s
=
opaque
;
pci_data_write
(
s
,
addr
&
7
,
val
,
2
);
}
static
void
pci_apb_writel
(
void
*
opaque
,
target_phys_addr_t
addr
,
uint32_t
val
)
{
PCIBus
*
s
=
opaque
;
pci_data_write
(
s
,
addr
&
7
,
val
,
4
);
}
static
uint32_t
pci_apb_readb
(
void
*
opaque
,
target_phys_addr_t
addr
)
{
PCIBus
*
s
=
opaque
;
uint32_t
val
;
val
=
pci_data_read
(
s
,
addr
&
7
,
1
);
return
val
;
}
static
uint32_t
pci_apb_readw
(
void
*
opaque
,
target_phys_addr_t
addr
)
{
PCIBus
*
s
=
opaque
;
uint32_t
val
;
val
=
pci_data_read
(
s
,
addr
&
7
,
2
);
return
val
;
}
static
uint32_t
pci_apb_readl
(
void
*
opaque
,
target_phys_addr_t
addr
)
{
PCIBus
*
s
=
opaque
;
uint32_t
val
;
val
=
pci_data_read
(
s
,
addr
,
4
);
return
val
;
}
static
CPUWriteMemoryFunc
*
pci_apb_write
[]
=
{
&
pci_apb_writeb
,
&
pci_apb_writew
,
&
pci_apb_writel
,
};
static
CPUReadMemoryFunc
*
pci_apb_read
[]
=
{
&
pci_apb_readb
,
&
pci_apb_readw
,
&
pci_apb_readl
,
};
static
void
pci_apb_iowriteb
(
void
*
opaque
,
target_phys_addr_t
addr
,
uint32_t
val
)
{
cpu_outb
(
NULL
,
addr
&
0xffff
,
val
);
}
static
void
pci_apb_iowritew
(
void
*
opaque
,
target_phys_addr_t
addr
,
uint32_t
val
)
{
cpu_outw
(
NULL
,
addr
&
0xffff
,
val
);
}
static
void
pci_apb_iowritel
(
void
*
opaque
,
target_phys_addr_t
addr
,
uint32_t
val
)
{
cpu_outl
(
NULL
,
addr
&
0xffff
,
val
);
}
static
uint32_t
pci_apb_ioreadb
(
void
*
opaque
,
target_phys_addr_t
addr
)
{
uint32_t
val
;
val
=
cpu_inb
(
NULL
,
addr
&
0xffff
);
return
val
;
}
static
uint32_t
pci_apb_ioreadw
(
void
*
opaque
,
target_phys_addr_t
addr
)
{
uint32_t
val
;
val
=
cpu_inw
(
NULL
,
addr
&
0xffff
);
return
val
;
}
static
uint32_t
pci_apb_ioreadl
(
void
*
opaque
,
target_phys_addr_t
addr
)
{
uint32_t
val
;
val
=
cpu_inl
(
NULL
,
addr
&
0xffff
);
return
val
;
}
static
CPUWriteMemoryFunc
*
pci_apb_iowrite
[]
=
{
&
pci_apb_iowriteb
,
&
pci_apb_iowritew
,
&
pci_apb_iowritel
,
};
static
CPUReadMemoryFunc
*
pci_apb_ioread
[]
=
{
&
pci_apb_ioreadb
,
&
pci_apb_ioreadw
,
&
pci_apb_ioreadl
,
};
PCIBus
*
pci_apb_init
(
target_ulong
special_base
,
target_ulong
mem_base
)
{
PCIBus
*
s
;
PCIDevice
*
d
;
int
pci_mem_config
,
pci_mem_data
,
apb_config
,
pci_ioport
;
/* Ultrasparc APB main bus */
s
=
pci_register_bus
();
s
->
set_irq
=
pci_set_irq_simple
;
pci_mem_config
=
cpu_register_io_memory
(
0
,
pci_apb_config_read
,
pci_apb_config_write
,
s
);
apb_config
=
cpu_register_io_memory
(
0
,
apb_config_read
,
apb_config_write
,
s
);
pci_mem_data
=
cpu_register_io_memory
(
0
,
pci_apb_read
,
pci_apb_write
,
s
);
pci_ioport
=
cpu_register_io_memory
(
0
,
pci_apb_ioread
,
pci_apb_iowrite
,
s
);
cpu_register_physical_memory
(
special_base
+
0x2000ULL
,
0x40
,
apb_config
);
cpu_register_physical_memory
(
special_base
+
0x1000000ULL
,
0x10
,
pci_mem_config
);
cpu_register_physical_memory
(
special_base
+
0x2000000ULL
,
0x10000
,
pci_ioport
);
cpu_register_physical_memory
(
mem_base
,
0x10000000
,
pci_mem_data
);
// XXX size should be 4G-prom
d
=
pci_register_device
(
s
,
"Advanced PCI Bus"
,
sizeof
(
PCIDevice
),
-
1
,
NULL
,
NULL
);
d
->
config
[
0x00
]
=
0x8e
;
// vendor_id : Sun
d
->
config
[
0x01
]
=
0x10
;
d
->
config
[
0x02
]
=
0x00
;
// device_id
d
->
config
[
0x03
]
=
0xa0
;
d
->
config
[
0x04
]
=
0x06
;
// command = bus master, pci mem
d
->
config
[
0x05
]
=
0x00
;
d
->
config
[
0x06
]
=
0xa0
;
// status = fast back-to-back, 66MHz, no error
d
->
config
[
0x07
]
=
0x03
;
// status = medium devsel
d
->
config
[
0x08
]
=
0x00
;
// revision
d
->
config
[
0x09
]
=
0x00
;
// programming i/f
d
->
config
[
0x0A
]
=
0x00
;
// class_sub = pci host
d
->
config
[
0x0B
]
=
0x06
;
// class_base = PCI_bridge
d
->
config
[
0x0D
]
=
0x10
;
// latency_timer
d
->
config
[
0x0E
]
=
0x00
;
// header_type
return
s
;
}
/***********************************************************/
/* generic PCI irq support */
...
...
hw/sun4u.c
View file @
83469015
...
...
@@ -22,23 +22,18 @@
* THE SOFTWARE.
*/
#include "vl.h"
#include "m48t
08
.h"
#include "m48t
59
.h"
#define KERNEL_LOAD_ADDR 0x00004000
#define CMDLINE_ADDR 0x007ff000
#define INITRD_LOAD_ADDR 0x00800000
#define PROM_ADDR 0xffd00000
#define KERNEL_LOAD_ADDR 0x00404000
#define CMDLINE_ADDR 0x003ff000
#define INITRD_LOAD_ADDR 0x00300000
#define PROM_ADDR 0x1fff0000000ULL
#define APB_SPECIAL_BASE 0x1fe00000000ULL
#define APB_MEM_BASE 0x1ff00000000ULL
#define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
#define PROM_FILENAMEB "proll-sparc64.bin"
#define PROM_FILENAMEE "proll-sparc64.elf"
#define PHYS_JJ_EEPROM 0x71200000
/* m48t08 */
#define PHYS_JJ_IDPROM_OFF 0x1FD8
#define PHYS_JJ_EEPROM_SIZE 0x2000
// IRQs are not PIL ones, but master interrupt controller register
// bits
#define PHYS_JJ_MS_KBD 0x71000000
/* Mouse and keyboard */
#define PHYS_JJ_MS_KBD_IRQ 14
#define PHYS_JJ_SER 0x71100000
/* Serial */
#define PHYS_JJ_SER_IRQ 15
#define NVRAM_SIZE 0x2000
/* TSC handling */
...
...
@@ -70,79 +65,170 @@ void DMA_register_channel (int nchan,
{
}
static
void
nvram_set_word
(
m48t08_t
*
nvram
,
uint32_t
addr
,
uint16_t
value
)
/* NVRAM helpers */
void
NVRAM_set_byte
(
m48t59_t
*
nvram
,
uint32_t
addr
,
uint8_t
value
)
{
m48t
08_write
(
nvram
,
addr
++
,
(
value
>>
8
)
&
0xff
);
m48t
08
_write
(
nvram
,
addr
++
,
value
&
0xff
);
m48t
59_set_addr
(
nvram
,
addr
);
m48t
59
_write
(
nvram
,
value
);
}
static
void
nvram_set_lword
(
m48t
08
_t
*
nvram
,
uint32_t
addr
,
uint32_t
value
)
uint8_t
NVRAM_get_byte
(
m48t
59
_t
*
nvram
,
uint32_t
addr
)
{
m48t08_write
(
nvram
,
addr
++
,
value
>>
24
);
m48t08_write
(
nvram
,
addr
++
,
(
value
>>
16
)
&
0xff
);
m48t08_write
(
nvram
,
addr
++
,
(
value
>>
8
)
&
0xff
);
m48t08_write
(
nvram
,
addr
++
,
value
&
0xff
);
m48t59_set_addr
(
nvram
,
addr
);
return
m48t59_read
(
nvram
);
}
static
void
nvram_set_string
(
m48t08_t
*
nvram
,
uint32_t
addr
,
void
NVRAM_set_word
(
m48t59_t
*
nvram
,
uint32_t
addr
,
uint16_t
value
)
{
m48t59_set_addr
(
nvram
,
addr
);
m48t59_write
(
nvram
,
value
>>
8
);
m48t59_set_addr
(
nvram
,
addr
+
1
);
m48t59_write
(
nvram
,
value
&
0xFF
);
}
uint16_t
NVRAM_get_word
(
m48t59_t
*
nvram
,
uint32_t
addr
)
{
uint16_t
tmp
;
m48t59_set_addr
(
nvram
,
addr
);
tmp
=
m48t59_read
(
nvram
)
<<
8
;
m48t59_set_addr
(
nvram
,
addr
+
1
);
tmp
|=
m48t59_read
(
nvram
);
return
tmp
;
}
void
NVRAM_set_lword
(
m48t59_t
*
nvram
,
uint32_t
addr
,
uint32_t
value
)
{
m48t59_set_addr
(
nvram
,
addr
);
m48t59_write
(
nvram
,
value
>>
24
);
m48t59_set_addr
(
nvram
,
addr
+
1
);
m48t59_write
(
nvram
,
(
value
>>
16
)
&
0xFF
);
m48t59_set_addr
(
nvram
,
addr
+
2
);
m48t59_write
(
nvram
,
(
value
>>
8
)
&
0xFF
);
m48t59_set_addr
(
nvram
,
addr
+
3
);
m48t59_write
(
nvram
,
value
&
0xFF
);
}
uint32_t
NVRAM_get_lword
(
m48t59_t
*
nvram
,
uint32_t
addr
)
{
uint32_t
tmp
;
m48t59_set_addr
(
nvram
,
addr
);
tmp
=
m48t59_read
(
nvram
)
<<
24
;
m48t59_set_addr
(
nvram
,
addr
+
1
);
tmp
|=
m48t59_read
(
nvram
)
<<
16
;
m48t59_set_addr
(
nvram
,
addr
+
2
);
tmp
|=
m48t59_read
(
nvram
)
<<
8
;
m48t59_set_addr
(
nvram
,
addr
+
3
);
tmp
|=
m48t59_read
(
nvram
);
return
tmp
;
}
void
NVRAM_set_string
(
m48t59_t
*
nvram
,
uint32_t
addr
,
const
unsigned
char
*
str
,
uint32_t
max
)
{
unsigned
int
i
;
int
i
;
for
(
i
=
0
;
i
<
max
&&
str
[
i
]
!=
'\0'
;
i
++
)
{
m48t08_write
(
nvram
,
addr
+
i
,
str
[
i
]);
m48t59_set_addr
(
nvram
,
addr
+
i
);
m48t59_write
(
nvram
,
str
[
i
]);
}
m48t08_write
(
nvram
,
addr
+
max
-
1
,
'\0'
);
m48t59_set_addr
(
nvram
,
addr
+
max
-
1
);
m48t59_write
(
nvram
,
'\0'
);
}
static
m48t08_t
*
nvram
;
int
NVRAM_get_string
(
m48t59_t
*
nvram
,
uint8_t
*
dst
,
uint16_t
addr
,
int
max
)
{
int
i
;
memset
(
dst
,
0
,
max
);
for
(
i
=
0
;
i
<
max
;
i
++
)
{
dst
[
i
]
=
NVRAM_get_byte
(
nvram
,
addr
+
i
);
if
(
dst
[
i
]
==
'\0'
)
break
;
}
return
i
;
}
static
uint16_t
NVRAM_crc_update
(
uint16_t
prev
,
uint16_t
value
)
{
uint16_t
tmp
;
uint16_t
pd
,
pd1
,
pd2
;
tmp
=
prev
>>
8
;
pd
=
prev
^
value
;
pd1
=
pd
&
0x000F
;
pd2
=
((
pd
>>
4
)
&
0x000F
)
^
pd1
;
tmp
^=
(
pd1
<<
3
)
|
(
pd1
<<
8
);
tmp
^=
pd2
|
(
pd2
<<
7
)
|
(
pd2
<<
12
);
return
tmp
;
}
uint16_t
NVRAM_compute_crc
(
m48t59_t
*
nvram
,
uint32_t
start
,
uint32_t
count
)
{
uint32_t
i
;
uint16_t
crc
=
0xFFFF
;
int
odd
;
odd
=
count
&
1
;
count
&=
~
1
;
for
(
i
=
0
;
i
!=
count
;
i
++
)
{
crc
=
NVRAM_crc_update
(
crc
,
NVRAM_get_word
(
nvram
,
start
+
i
));
}
if
(
odd
)
{
crc
=
NVRAM_crc_update
(
crc
,
NVRAM_get_byte
(
nvram
,
start
+
i
)
<<
8
);
}
return
crc
;
}
extern
int
nographic
;
static
void
nvram_init
(
m48t08_t
*
nvram
,
uint8_t
*
macaddr
,
const
char
*
cmdline
,
int
boot_device
,
uint32_t
RAM_size
,
uint32_t
kernel_size
,
int
width
,
int
height
,
int
depth
)
{
unsigned
char
tmp
=
0
;
int
i
,
j
;
// Try to match PPC NVRAM
nvram_set_string
(
nvram
,
0x00
,
"QEMU_BIOS"
,
16
);
nvram_set_lword
(
nvram
,
0x10
,
0x00000001
);
/* structure v1 */
// NVRAM_size, arch not applicable
m48t08_write
(
nvram
,
0x2F
,
nographic
&
0xff
);
nvram_set_lword
(
nvram
,
0x30
,
RAM_size
);
m48t08_write
(
nvram
,
0x34
,
boot_device
&
0xff
);
nvram_set_lword
(
nvram
,
0x38
,
KERNEL_LOAD_ADDR
);
nvram_set_lword
(
nvram
,
0x3C
,
kernel_size
);
int
sun4u_NVRAM_set_params
(
m48t59_t
*
nvram
,
uint16_t
NVRAM_size
,
const
unsigned
char
*
arch
,
uint32_t
RAM_size
,
int
boot_device
,
uint32_t
kernel_image
,
uint32_t
kernel_size
,
const
char
*
cmdline
,
uint32_t
initrd_image
,
uint32_t
initrd_size
,
uint32_t
NVRAM_image
,
int
width
,
int
height
,
int
depth
)
{
uint16_t
crc
;
/* Set parameters for Open Hack'Ware BIOS */
NVRAM_set_string
(
nvram
,
0x00
,
"QEMU_BIOS"
,
16
);
NVRAM_set_lword
(
nvram
,
0x10
,
0x00000002
);
/* structure v2 */
NVRAM_set_word
(
nvram
,
0x14
,
NVRAM_size
);
NVRAM_set_string
(
nvram
,
0x20
,
arch
,
16
);
NVRAM_set_byte
(
nvram
,
0x2f
,
nographic
&
0xff
);
NVRAM_set_lword
(
nvram
,
0x30
,
RAM_size
);
NVRAM_set_byte
(
nvram
,
0x34
,
boot_device
);
NVRAM_set_lword
(
nvram
,
0x38
,
kernel_image
);
NVRAM_set_lword
(
nvram
,
0x3C
,
kernel_size
);
if
(
cmdline
)
{
strcpy
(
phys_ram_base
+
CMDLINE_ADDR
,
cmdline
);
nvram_set_lword
(
nvram
,
0x40
,
CMDLINE_ADDR
);
nvram_set_lword
(
nvram
,
0x44
,
strlen
(
cmdline
));
/* XXX: put the cmdline in NVRAM too ? */
strcpy
(
phys_ram_base
+
CMDLINE_ADDR
,
cmdline
);
NVRAM_set_lword
(
nvram
,
0x40
,
CMDLINE_ADDR
);
NVRAM_set_lword
(
nvram
,
0x44
,
strlen
(
cmdline
));
}
else
{
NVRAM_set_lword
(
nvram
,
0x40
,
0
);
NVRAM_set_lword
(
nvram
,
0x44
,
0
);
}
// initrd_image, initrd_size passed differently
nvram_set_word
(
nvram
,
0x54
,
width
);
nvram_set_word
(
nvram
,
0x56
,
height
);
nvram_set_word
(
nvram
,
0x58
,
depth
);
// Sun4m specific use
i
=
0x1fd8
;
m48t08_write
(
nvram
,
i
++
,
0x01
);
m48t08_write
(
nvram
,
i
++
,
0x80
);
/* Sun4m OBP */
j
=
0
;
m48t08_write
(
nvram
,
i
++
,
macaddr
[
j
++
]);
m48t08_write
(
nvram
,
i
++
,
macaddr
[
j
++
]);
m48t08_write
(
nvram
,
i
++
,
macaddr
[
j
++
]);
m48t08_write
(
nvram
,
i
++
,
macaddr
[
j
++
]);
m48t08_write
(
nvram
,
i
++
,
macaddr
[
j
++
]);
m48t08_write
(
nvram
,
i
,
macaddr
[
j
]);
/* Calculate checksum */
for
(
i
=
0x1fd8
;
i
<
0x1fe7
;
i
++
)
{
tmp
^=
m48t08_read
(
nvram
,
i
);
}
m48t08_write
(
nvram
,
0x1fe7
,
tmp
);
NVRAM_set_lword
(
nvram
,
0x48
,
initrd_image
);
NVRAM_set_lword
(
nvram
,
0x4C
,
initrd_size
);
NVRAM_set_lword
(
nvram
,
0x50
,
NVRAM_image
);
NVRAM_set_word
(
nvram
,
0x54
,
width
);
NVRAM_set_word
(
nvram
,
0x56
,
height
);
NVRAM_set_word
(
nvram
,
0x58
,
depth
);
crc
=
NVRAM_compute_crc
(
nvram
,
0x00
,
0xF8
);
NVRAM_set_word
(
nvram
,
0xFC
,
crc
);
return
0
;
}
void
pic_info
()
...
...
@@ -157,21 +243,25 @@ void pic_set_irq(int irq, int level)
{
}
void
vga_update_display
(
)
void
pic_set_irq_new
(
void
*
opaque
,
int
irq
,
int
level
)
{
}
void
vga_invalidate_display
(
)
void
qemu_system_powerdown
(
void
)
{
}
void
vga_screen_dump
(
const
char
*
filename
)
{
}
static
const
int
ide_iobase
[
2
]
=
{
0x1f0
,
0x170
};
static
const
int
ide_iobase2
[
2
]
=
{
0x3f6
,
0x376
};
static
const
int
ide_irq
[
2
]
=
{
14
,
15
};
void
qemu_system_powerdown
(
void
)
{
}
static
const
int
serial_io
[
MAX_SERIAL_PORTS
]
=
{
0x3f8
,
0x2f8
,
0x3e8
,
0x2e8
};
static
const
int
serial_irq
[
MAX_SERIAL_PORTS
]
=
{
4
,
3
,
4
,
3
};
static
const
int
parallel_io
[
MAX_PARALLEL_PORTS
]
=
{
0x378
,
0x278
,
0x3bc
};
static
const
int
parallel_irq
[
MAX_PARALLEL_PORTS
]
=
{
7
,
7
,
7
};
static
fdctrl_t
*
floppy_controller
;
/* Sun4u hardware initialisation */
static
void
sun4u_init
(
int
ram_size
,
int
vga_ram_size
,
int
boot_device
,
...
...
@@ -180,21 +270,18 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
const
char
*
initrd_filename
)
{
char
buf
[
1024
];
m48t59_t
*
nvram
;
int
ret
,
linux_boot
;
unsigned
int
i
;
long
vram_size
=
0x100000
,
prom_offset
,
initrd_size
,
kernel_size
;
long
prom_offset
,
initrd_size
,
kernel_size
;
PCIBus
*
pci_bus
;
linux_boot
=
(
kernel_filename
!=
NULL
);
/* allocate RAM */
cpu_register_physical_memory
(
0
,
ram_size
,
0
);
nvram
=
m48t08_init
(
PHYS_JJ_EEPROM
,
PHYS_JJ_EEPROM_SIZE
);
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
slavio_serial_init
(
PHYS_JJ_SER
,
PHYS_JJ_SER_IRQ
,
serial_hds
[
1
],
serial_hds
[
0
]);
prom_offset
=
ram_size
+
vram_size
;
prom_offset
=
ram_size
+
vga_ram_size
;
snprintf
(
buf
,
sizeof
(
buf
),
"%s/%s"
,
bios_dir
,
PROM_FILENAMEE
);
ret
=
load_elf
(
buf
,
phys_ram_base
+
prom_offset
);
...
...