Commit 77b2bc2c authored by Blue Swirl's avatar Blue Swirl

x86: avoid AREG0 for exceptions

Add an explicit CPUX86State parameter instead of relying on AREG0.

Merge raise_exception_env() to raise_exception(), likewise with
raise_exception_err_env() and raise_exception_err().

Introduce cpu_svm_check_intercept_param() and cpu_vmexit()
as wrappers.
Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
parent 20054ef0
......@@ -289,7 +289,8 @@ int cpu_exec(CPUArchState *env)
#endif
#if defined(TARGET_I386)
if (interrupt_request & CPU_INTERRUPT_INIT) {
svm_check_intercept(env, SVM_EXIT_INIT);
cpu_svm_check_intercept_param(env, SVM_EXIT_INIT,
0);
do_cpu_init(x86_env_get_cpu(env));
env->exception_index = EXCP_HALTED;
cpu_loop_exit(env);
......@@ -298,7 +299,8 @@ int cpu_exec(CPUArchState *env)
} else if (env->hflags2 & HF2_GIF_MASK) {
if ((interrupt_request & CPU_INTERRUPT_SMI) &&
!(env->hflags & HF_SMM_MASK)) {
svm_check_intercept(env, SVM_EXIT_SMI);
cpu_svm_check_intercept_param(env, SVM_EXIT_SMI,
0);
env->interrupt_request &= ~CPU_INTERRUPT_SMI;
do_smm_enter(env);
next_tb = 0;
......@@ -319,7 +321,8 @@ int cpu_exec(CPUArchState *env)
(env->eflags & IF_MASK &&
!(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
int intno;
svm_check_intercept(env, SVM_EXIT_INTR);
cpu_svm_check_intercept_param(env, SVM_EXIT_INTR,
0);
env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
intno = cpu_get_pic_interrupt(env);
qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
......@@ -333,7 +336,8 @@ int cpu_exec(CPUArchState *env)
!(env->hflags & HF_INHIBIT_IRQ_MASK)) {
int intno;
/* FIXME: this should respect TPR */
svm_check_intercept(env, SVM_EXIT_VINTR);
cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
0);
intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
do_interrupt_x86_hardirq(env, intno, 1);
......
......@@ -1074,13 +1074,15 @@ void cpu_x86_inject_mce(Monitor *mon, CPUX86State *cenv, int bank,
/* op_helper.c */
void do_interrupt(CPUX86State *env);
void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
void QEMU_NORETURN raise_exception_env(int exception_index, CPUX86State *nenv);
void QEMU_NORETURN raise_exception_err_env(CPUX86State *nenv, int exception_index,
int error_code);
void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
int error_code);
void do_smm_enter(CPUX86State *env1);
void svm_check_intercept(CPUX86State *env1, uint32_t type);
void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
uint64_t param);
void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1);
uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
......
......@@ -951,7 +951,7 @@ static void breakpoint_handler(CPUX86State *env)
if (env->watchpoint_hit->flags & BP_CPU) {
env->watchpoint_hit = NULL;
if (check_hw_breakpoints(env, 0))
raise_exception_env(EXCP01_DB, env);
raise_exception(env, EXCP01_DB);
else
cpu_resume_from_signal(env, NULL);
}
......@@ -960,7 +960,7 @@ static void breakpoint_handler(CPUX86State *env)
if (bp->pc == env->eip) {
if (bp->flags & BP_CPU) {
check_hw_breakpoints(env, 1);
raise_exception_env(EXCP01_DB, env);
raise_exception(env, EXCP01_DB);
}
break;
}
......
......@@ -63,8 +63,8 @@ DEF_HELPER_1(monitor, void, tl)
DEF_HELPER_1(mwait, void, int)
DEF_HELPER_0(debug, void)
DEF_HELPER_0(reset_rf, void)
DEF_HELPER_2(raise_interrupt, void, int, int)
DEF_HELPER_1(raise_exception, void, int)
DEF_HELPER_3(raise_interrupt, void, env, int, int)
DEF_HELPER_2(raise_exception, void, env, int)
DEF_HELPER_0(cli, void)
DEF_HELPER_0(sti, void)
DEF_HELPER_0(set_inhibit_irq, void)
......
This diff is collapsed.
......@@ -2659,7 +2659,7 @@ static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(cur_eip);
gen_helper_raise_exception(tcg_const_i32(trapno));
gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno));
s->is_jmp = DISAS_TB_JUMP;
}
......@@ -2671,7 +2671,7 @@ static void gen_interrupt(DisasContext *s, int intno,
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(cur_eip);
gen_helper_raise_interrupt(tcg_const_i32(intno),
gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno),
tcg_const_i32(next_eip - cur_eip));
s->is_jmp = DISAS_TB_JUMP;
}
......
......@@ -41,7 +41,7 @@
static void exception_action(CPUArchState *env1)
{
#if defined(TARGET_I386)
raise_exception_err_env(env1, env1->exception_index, env1->error_code);
raise_exception_err(env1, env1->exception_index, env1->error_code);
#else
cpu_loop_exit(env1);
#endif
......
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