Commit 70c0de96 authored by blueswir1's avatar blueswir1
Browse files

Use qemu_irqs between dma controllers and esp, lance


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2873 c046a42c-6fe2-441c-8c8c-71466251a162
parent 2bc1abb7
......@@ -51,6 +51,7 @@ do { printf("ESP: " fmt , ##args); } while (0)
typedef struct ESPState ESPState;
struct ESPState {
qemu_irq irq;
BlockDriverState **bd;
uint8_t rregs[ESP_REGS];
uint8_t wregs[ESP_REGS];
......@@ -126,7 +127,7 @@ static int get_cmd(ESPState *s, uint8_t *buf)
s->rregs[4] = STAT_IN;
s->rregs[5] = INTR_DC;
s->rregs[6] = SEQ_0;
espdma_raise_irq(s->dma_opaque);
qemu_irq_raise(s->irq);
return 0;
}
s->current_dev = s->scsi_dev[target];
......@@ -156,7 +157,7 @@ static void do_cmd(ESPState *s, uint8_t *buf)
}
s->rregs[5] = INTR_BS | INTR_FC;
s->rregs[6] = SEQ_CD;
espdma_raise_irq(s->dma_opaque);
qemu_irq_raise(s->irq);
}
static void handle_satn(ESPState *s)
......@@ -178,7 +179,7 @@ static void handle_satn_stop(ESPState *s)
s->rregs[4] = STAT_IN | STAT_TC | STAT_CD;
s->rregs[5] = INTR_BS | INTR_FC;
s->rregs[6] = SEQ_CD;
espdma_raise_irq(s->dma_opaque);
qemu_irq_raise(s->irq);
}
}
......@@ -198,7 +199,7 @@ static void write_response(ESPState *s)
s->ti_wptr = 0;
s->rregs[7] = 2;
}
espdma_raise_irq(s->dma_opaque);
qemu_irq_raise(s->irq);
}
static void esp_dma_done(ESPState *s)
......@@ -209,7 +210,7 @@ static void esp_dma_done(ESPState *s)
s->rregs[7] = 0;
s->rregs[0] = 0;
s->rregs[1] = 0;
espdma_raise_irq(s->dma_opaque);
qemu_irq_raise(s->irq);
}
static void esp_do_dma(ESPState *s)
......@@ -362,7 +363,7 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
} else {
s->rregs[2] = s->ti_buf[s->ti_rptr++];
}
espdma_raise_irq(s->dma_opaque);
qemu_irq_raise(s->irq);
}
if (s->ti_size == 0) {
s->ti_rptr = 0;
......@@ -373,7 +374,7 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
// interrupt
// Clear interrupt/error status bits
s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE);
espdma_clear_irq(s->dma_opaque);
qemu_irq_lower(s->irq);
break;
default:
break;
......@@ -436,7 +437,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
DPRINTF("Bus reset (%2.2x)\n", val);
s->rregs[5] = INTR_RST;
if (!(s->wregs[8] & 0x40)) {
espdma_raise_irq(s->dma_opaque);
qemu_irq_raise(s->irq);
}
break;
case 0x10:
......@@ -565,7 +566,7 @@ void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id)
}
void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
void *dma_opaque)
void *dma_opaque, qemu_irq irq)
{
ESPState *s;
int esp_io_memory;
......@@ -575,6 +576,7 @@ void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
return NULL;
s->bd = bd;
s->irq = irq;
s->dma_opaque = dma_opaque;
sparc32_dma_set_reset_data(dma_opaque, esp_reset, s);
......
......@@ -2018,7 +2018,7 @@ static CPUWriteMemoryFunc *lance_mem_write[3] = {
(CPUWriteMemoryFunc *)&pcnet_ioport_writew,
};
void *lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
qemu_irq irq)
{
PCNetState *d;
......@@ -2026,7 +2026,7 @@ void *lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
d = qemu_mallocz(sizeof(PCNetState));
if (!d)
return NULL;
return;
lance_io_memory =
cpu_register_io_memory(0, lance_mem_read, lance_mem_write, d);
......@@ -2041,7 +2041,5 @@ void *lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
d->phys_mem_write = ledma_memory_write;
pcnet_common_init(d, nd, "lance");
return d;
}
#endif /* TARGET_SPARC */
......@@ -115,22 +115,18 @@ void ledma_memory_write(void *opaque, target_phys_addr_t addr,
}
}
void espdma_raise_irq(void *opaque)
static void dma_set_irq(void *opaque, int irq, int level)
{
DMAState *s = opaque;
DPRINTF("Raise ESP IRQ\n");
s->dmaregs[0] |= DMA_INTR;
qemu_irq_raise(s->irq);
}
void espdma_clear_irq(void *opaque)
{
DMAState *s = opaque;
s->dmaregs[0] &= ~DMA_INTR;
DPRINTF("Lower ESP IRQ\n");
qemu_irq_lower(s->irq);
if (level) {
DPRINTF("Raise ESP IRQ\n");
s->dmaregs[0] |= DMA_INTR;
qemu_irq_raise(s->irq);
} else {
s->dmaregs[0] &= ~DMA_INTR;
DPRINTF("Lower ESP IRQ\n");
qemu_irq_lower(s->irq);
}
}
void espdma_memory_read(void *opaque, uint8_t *buf, int len)
......@@ -241,7 +237,8 @@ static int dma_load(QEMUFile *f, void *opaque, int version_id)
return 0;
}
void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq irq, void *iommu)
void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
void *iommu, qemu_irq **dev_irq)
{
DMAState *s;
int dma_io_memory;
......@@ -250,7 +247,7 @@ void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq irq, void *iommu)
if (!s)
return NULL;
s->irq = irq;
s->irq = parent_irq;
s->iommu = iommu;
dma_io_memory = cpu_register_io_memory(0, dma_mem_read, dma_mem_write, s);
......@@ -258,6 +255,7 @@ void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq irq, void *iommu)
register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);
qemu_register_reset(dma_reset, s);
*dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);
return s;
}
......
......@@ -262,9 +262,9 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
{
CPUState *env, *envs[MAX_CPUS];
unsigned int i;
void *iommu, *espdma, *ledma, *main_esp, *main_lance = NULL;
void *iommu, *espdma, *ledma, *main_esp;
const sparc_def_t *def;
qemu_irq *slavio_irq;
qemu_irq *slavio_irq, *espdma_irq, *ledma_irq;
/* init CPUs */
sparc_find_by_name(cpu_model, &def);
......@@ -296,9 +296,9 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
}
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
iommu);
iommu, &espdma_irq);
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
slavio_irq[hwdef->le_irq], iommu);
slavio_irq[hwdef->le_irq], iommu, &ledma_irq);
if (graphic_depth != 8 && graphic_depth != 24) {
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
......@@ -309,8 +309,7 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
if (nd_table[0].vlan) {
if (nd_table[0].model == NULL
|| strcmp(nd_table[0].model, "lance") == 0) {
main_lance = lance_init(&nd_table[0], hwdef->le_base, ledma,
slavio_irq[hwdef->le_irq]);
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq);
} else {
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
exit (1);
......@@ -331,7 +330,7 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
serial_hds[1], serial_hds[0]);
fdctrl_init(slavio_irq[hwdef->fd_irq], 0, 1, hwdef->fd_base, fd_table);
main_esp = esp_init(bs_table, hwdef->esp_base, espdma);
main_esp = esp_init(bs_table, hwdef->esp_base, espdma, *espdma_irq);
for (i = 0; i < MAX_DISKS; i++) {
if (bs_table[i]) {
......
......@@ -1046,7 +1046,7 @@ void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
/* pcnet.c */
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
void *lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
qemu_irq irq);
/* vmmouse.c */
......@@ -1263,17 +1263,15 @@ void slavio_set_power_fail(void *opaque, int power_failing);
/* esp.c */
void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
void *dma_opaque);
void *dma_opaque, qemu_irq irq);
/* sparc32_dma.c */
void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq irq, void *iommu);
void ledma_set_irq(void *opaque, int isr);
void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
void *iommu, qemu_irq **dev_irq);
void ledma_memory_read(void *opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int do_bswap);
void ledma_memory_write(void *opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int do_bswap);
void espdma_raise_irq(void *opaque);
void espdma_clear_irq(void *opaque);
void espdma_memory_read(void *opaque, uint8_t *buf, int len);
void espdma_memory_write(void *opaque, uint8_t *buf, int len);
void sparc32_dma_set_reset_data(void *opaque, void (*dev_reset)(void *opaque),
......
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