Commit 607b4b08 authored by Peter Maydell's avatar Peter Maydell Committed by Aurelien Jarno
Browse files

target-arm: Clean up handling of MPIDR



The ARM cp15 register 0,c0,c0,5 is standardised in the v7 architecture
as the MPIDR. Clean up its implementation to remove A9 specific handling.

This commit includes fixing an error in the value returned for the
MPIDR on A9, where we were erroneously claiming a cluster ID of 9.
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
parent e1bbf446
...@@ -1608,12 +1608,28 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) ...@@ -1608,12 +1608,28 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
return 0; return 0;
case 3: /* TLB type register. */ case 3: /* TLB type register. */
return 0; /* No lockable TLB entries. */ return 0; /* No lockable TLB entries. */
case 5: /* CPU ID */ case 5: /* MPIDR */
if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) { /* The MPIDR was standardised in v7; prior to
return env->cpu_index | 0x80000900; * this it was implemented only in the 11MPCore.
} else { * For all other pre-v7 cores it does not exist.
return env->cpu_index; */
if (arm_feature(env, ARM_FEATURE_V7) ||
ARM_CPUID(env) == ARM_CPUID_ARM11MPCORE) {
int mpidr = env->cpu_index;
/* We don't support setting cluster ID ([8..11])
* so these bits always RAZ.
*/
if (arm_feature(env, ARM_FEATURE_V7MP)) {
mpidr |= (1 << 31);
/* Cores which are uniprocessor (non-coherent)
* but still implement the MP extensions set
* bit 30. (For instance, A9UP.) However we do
* not currently model any of those cores.
*/
}
return mpidr;
} }
/* otherwise fall through to the unimplemented-reg case */
default: default:
goto bad_reg; goto bad_reg;
} }
......
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