Skip to content

GitLab

Commit 5fafdf24 authored by ths's avatar ths
Browse files
Options

find -type f | xargs sed -i 's/[\t ]$//g' # on most files 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
parent bd494f4c
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 1351 additions and 1351 deletions
Changelog
View file @ 5fafdf24
......@@ -86,7 +86,7 @@ version 0.8.0:
(Johannes Schindelin)
version 0.7.2:
- x86_64 fixes (Win2000 and Linux 2.6 boot in 32 bit)
- merge self modifying code handling in dirty ram page mecanism.
- MIPS fixes (Ralf Baechle)
......@@ -135,7 +135,7 @@ version 0.6.1:
- Mac OS X port (Pierre d'Herbemont)
- Virtual console support
- Better monitor line edition
- New block device layer
- New block device layer
- New 'qcow' growable disk image support with AES encryption and
transparent decompression
- VMware 3 and 4 read-only disk image support (untested)
......@@ -201,7 +201,7 @@ version 0.5.5:
- FDC fixes for Win98
version 0.5.4:
- qemu-fast fixes
- BIOS area protection fix (aka EMM386.EXE fix) (Mike Nordell)
- keyboard/mouse fix (Mike Nordell)
......@@ -228,7 +228,7 @@ version 0.5.3:
- added accurate CR0.MP/ME/TS emulation
- fixed DMA memory write access (Win95 boot floppy fix)
- graphical x86 linux loader
- command line monitor
- command line monitor
- generic removable device support
- support of CD-ROM change
- multiple network interface support
......@@ -266,7 +266,7 @@ version 0.5.2:
- eflags optimisation fix for string operations
version 0.5.1:
- float access fixes when using soft mmu
- PC emulation support on PowerPC
- A20 support
......@@ -281,7 +281,7 @@ version 0.5.1:
- Major SPARC target fixes (dynamically linked programs begin to work)
version 0.5.0:
- full hardware level VGA emulation
- graphical display with SDL
- added PS/2 mouse and keyboard emulation
......@@ -319,7 +319,7 @@ version 0.4.2:
- SMP kernels can at least be booted
version 0.4.1:
- more accurate timer support in vl.
- more reliable NE2000 probe in vl.
- added 2.5.66 kernel in vl-test.
......@@ -405,7 +405,7 @@ version 0.1.3:
- added bound, cmpxchg8b, cpuid instructions
- added 16 bit addressing support/override for string operations
- poll() fix
version 0.1.2:
- compile fixes
......
Makefile
View file @ 5fafdf24
......@@ -40,7 +40,7 @@ dyngen$(EXESUF): dyngen.c
clean:
# avoid old build problems by removing potentially incorrect old files
rm -f config.mak config.h op-i386.h opc-i386.h gen-op-i386.h op-arm.h opc-arm.h gen-op-arm.h
rm -f config.mak config.h op-i386.h opc-i386.h gen-op-i386.h op-arm.h opc-arm.h gen-op-arm.h
rm -f *.o *.a $(TOOLS) dyngen$(EXESUF) TAGS cscope.* *.pod *~ */*~
$(MAKE) -C tests clean
for d in $(TARGET_DIRS); do \
......@@ -89,7 +89,7 @@ endif
test speed test2: all
$(MAKE) -C tests $@
TAGS:
TAGS:
etags *.[ch] tests/*.[ch]
cscope:
......
Makefile.target
View file @ 5fafdf24
......@@ -269,7 +269,7 @@ OBJS+= libqemu.a
# cpu emulator library
LIBOBJS=exec.o kqemu.o translate-op.o translate-all.o cpu-exec.o\
translate.o op.o
translate.o op.o
ifdef CONFIG_SOFTFLOAT
LIBOBJS+=fpu/softfloat.o
else
......@@ -317,7 +317,7 @@ LIBOBJS+= op_helper.o helper.o alpha_palcode.o
endif
# NOTE: the disassembler code is only needed for debugging
LIBOBJS+=disas.o
LIBOBJS+=disas.o
ifeq ($(findstring i386, $(TARGET_ARCH) $(ARCH)),i386)
USE_I386_DIS=y
endif
......@@ -483,7 +483,7 @@ VL_OBJS+= an5206.o mcf5206.o ptimer.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o
VL_OBJS+= m68k-semi.o
endif
ifdef CONFIG_GDBSTUB
VL_OBJS+=gdbstub.o
VL_OBJS+=gdbstub.o
endif
ifdef CONFIG_SDL
VL_OBJS+=sdl.o x_keymap.o
......@@ -511,7 +511,7 @@ ifdef CONFIG_STATIC
VL_LDFLAGS+=-static
endif
ifndef CONFIG_SOFTMMU
VL_LDFLAGS+=-Wl,-T,$(SRC_PATH)/i386-vl.ld
VL_LDFLAGS+=-Wl,-T,$(SRC_PATH)/i386-vl.ld
endif
ifndef CONFIG_DARWIN
ifndef CONFIG_WIN32
......@@ -561,7 +561,7 @@ depend: $(SRCS)
vldepend: $(VL_OBJS:.o=.c)
$(CC) -MM $(CFLAGS) $(CPPFLAGS) $(BASE_CFLAGS) $^ 1>.depend
# libqemu
# libqemu
libqemu.a: $(LIBOBJS)
rm -f $@
......@@ -665,7 +665,7 @@ $(OBJS) $(LIBOBJS) $(VL_OBJS): config.h ../config-host.h
clean:
rm -f *.o *.a *~ $(PROGS) gen-op.h opc.h op.h nwfpe/*.o slirp/*.o fpu/*.o
install: all
install: all
ifneq ($(PROGS),)
$(INSTALL) -m 755 -s $(PROGS) "$(DESTDIR)$(bindir)"
endif
......
TODO
View file @ 5fafdf24
......@@ -16,7 +16,7 @@ short term:
- do not resize vga if invalid size.
- avoid looping if only exceptions
- TLB code protection support for PPC
- see openMosix Doc
- see openMosix Doc
- disable SMC handling for ARM/SPARC/PPC (not finished)
- see undefined flags for BTx insn
- user/kernel PUSHL/POPL in helper.c
......
aes.c
View file @ 5fafdf24
/**
*
*
* aes.c - integrated in QEMU by Fabrice Bellard from the OpenSSL project.
*/
/*
......@@ -1267,7 +1267,7 @@ void AES_decrypt(const unsigned char *in, unsigned char *out,
void AES_cbc_encrypt(const unsigned char *in, unsigned char *out,
const unsigned long length, const AES_KEY *key,
unsigned char *ivec, const int enc)
unsigned char *ivec, const int enc)
{
unsigned long n;
......@@ -1294,7 +1294,7 @@ void AES_cbc_encrypt(const unsigned char *in, unsigned char *out,
AES_encrypt(tmp, tmp, key);
memcpy(out, tmp, AES_BLOCK_SIZE);
memcpy(ivec, tmp, AES_BLOCK_SIZE);
}
}
} else {
while (len >= AES_BLOCK_SIZE) {
memcpy(tmp, in, AES_BLOCK_SIZE);
......@@ -1312,6 +1312,6 @@ void AES_cbc_encrypt(const unsigned char *in, unsigned char *out,
for(n=0; n < len; ++n)
out[n] = tmp[n] ^ ivec[n];
memcpy(ivec, tmp, AES_BLOCK_SIZE);
}
}
}
}
alpha-dis.c
View file @ 5fafdf24
......@@ -374,7 +374,7 @@ const struct alpha_operand alpha_operands[] =
/* The signed "23-bit" aligned displacement of Branch format insns */
#define BDISP (MDISP + 1)
{ 21, 0, BFD_RELOC_23_PCREL_S2,
{ 21, 0, BFD_RELOC_23_PCREL_S2,
AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
/* The 26-bit PALcode function */
......
arm-dis.c
View file @ 5fafdf24
......@@ -4,17 +4,17 @@
Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
Modification by James G. Smith (jsmith@cygnus.co.uk)
This file is part of libopcodes.
This file is part of libopcodes.
This program is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
......@@ -34,7 +34,7 @@ struct thumb_opcode
};
/* format of the assembler string :
%% %
%<bitfield>d print the bitfield in decimal
%<bitfield>x print the bitfield in hex
......@@ -104,7 +104,7 @@ static struct arm_opcode arm_opcodes[] =
{0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
{0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
{0xf450f000, 0xfc70f000, "pld\t%a"},
/* V5 Instructions. */
{0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
{0xfa000000, 0xfe000000, "blx\t%B"},
......@@ -116,7 +116,7 @@ static struct arm_opcode arm_opcodes[] =
{0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
{0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
/* V5E "El Segundo" Instructions. */
/* V5E "El Segundo" Instructions. */
{0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"},
{0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"},
{0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
......@@ -303,7 +303,7 @@ static struct arm_opcode arm_opcodes[] =
{0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
{0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
{0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
{0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
{0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
{0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
{0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
{0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
......@@ -571,7 +571,7 @@ static boolean force_thumb = false;
static char * arm_fp_const[] =
{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
static char * arm_shift[] =
static char * arm_shift[] =
{"lsl", "lsr", "asr", "ror"};
/* Forward declarations. */
......@@ -621,14 +621,14 @@ arm_decode_shift (given, func, stream)
void * stream;
{
func (stream, "%s", arm_regnames[given & 0xf]);
if ((given & 0xff0) != 0)
{
if ((given & 0x10) == 0)
{
int amount = (given & 0xf80) >> 7;
int shift = (given & 0x60) >> 5;
if (amount == 0)
{
if (shift == 3)
......@@ -636,10 +636,10 @@ arm_decode_shift (given, func, stream)
func (stream, ", rrx");
return;
}
amount = 32;
}
func (stream, ", %s #%d", arm_shift[shift], amount);
}
else
......@@ -666,7 +666,7 @@ print_insn_arm1 (pc, info, given)
if ((given & insn->mask) == insn->value)
{
char * c;
for (c = insn->assembler; *c; c++)
{
if (*c == '%')
......@@ -682,14 +682,14 @@ print_insn_arm1 (pc, info, given)
&& ((given & 0x02000000) == 0))
{
int offset = given & 0xfff;
func (stream, "[pc");
if (given & 0x01000000)
{
if ((given & 0x00800000) == 0)
offset = - offset;
/* Pre-indexed. */
func (stream, ", #%d]", offset);
......@@ -710,13 +710,13 @@ print_insn_arm1 (pc, info, given)
/* ie ignore the offset. */
offset = pc + 8;
}
func (stream, "\t; ");
info->print_address_func (offset, info);
}
else
{
func (stream, "[%s",
func (stream, "[%s",
arm_regnames[(given >> 16) & 0xf]);
if ((given & 0x01000000) != 0)
{
......@@ -736,7 +736,7 @@ print_insn_arm1 (pc, info, given)
arm_decode_shift (given, func, stream);
}
func (stream, "]%s",
func (stream, "]%s",
((given & 0x00200000) != 0) ? "!" : "");
}
else
......@@ -748,13 +748,13 @@ print_insn_arm1 (pc, info, given)
func (stream, "], %s#%d",
(((given & 0x00800000) == 0)
? "-" : ""), offset);
else
else
func (stream, "]");
}
else
{
func (stream, "], %s",
(((given & 0x00800000) == 0)
(((given & 0x00800000) == 0)
? "-" : ""));
arm_decode_shift (given, func, stream);
}
......@@ -767,18 +767,18 @@ print_insn_arm1 (pc, info, given)
{
/* PC relative with immediate offset. */
int offset = ((given & 0xf00) >> 4) | (given & 0xf);
if ((given & 0x00800000) == 0)
offset = -offset;
func (stream, "[pc, #%d]\t; ", offset);
(*info->print_address_func)
(offset + pc + 8, info);
}
else
{
func (stream, "[%s",
func (stream, "[%s",
arm_regnames[(given >> 16) & 0xf]);
if ((given & 0x01000000) != 0)
{
......@@ -801,7 +801,7 @@ print_insn_arm1 (pc, info, given)
arm_regnames[given & 0xf]);
}
func (stream, "]%s",
func (stream, "]%s",
((given & 0x00200000) != 0) ? "!" : "");
}
else
......@@ -815,7 +815,7 @@ print_insn_arm1 (pc, info, given)
func (stream, "], %s#%d",
(((given & 0x00800000) == 0)
? "-" : ""), offset);
else
else
func (stream, "]");
}
else
......@@ -829,7 +829,7 @@ print_insn_arm1 (pc, info, given)
}
}
break;
case 'b':
(*info->print_address_func)
(BDISP (given) * 4 + pc + 8, info);
......@@ -911,7 +911,7 @@ print_insn_arm1 (pc, info, given)
{
bfd_vma address;
bfd_vma offset = 0;
if (given & 0x00800000)
/* Is signed, hi bits should be ones. */
offset = (-1) ^ 0x00ffffff;
......@@ -920,7 +920,7 @@ print_insn_arm1 (pc, info, given)
offset += given & 0x00ffffff;
offset <<= 2;
address = offset + pc + 8;
if (given & 0x01000000)
/* H bit allows addressing to 2-byte boundaries. */
address += 2;
......@@ -976,7 +976,7 @@ print_insn_arm1 (pc, info, given)
func (stream, "3");
}
break;
case 'P':
switch (given & 0x00080080)
{
......@@ -1028,7 +1028,7 @@ print_insn_arm1 (pc, info, given)
}
break;
case '0': case '1': case '2': case '3': case '4':
case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
{
int bitstart = *c++ - '0';
......@@ -1040,44 +1040,44 @@ print_insn_arm1 (pc, info, given)
{
case '-':
c++;
while (*c >= '0' && *c <= '9')
bitend = (bitend * 10) + *c++ - '0';
if (!bitend)
abort ();
switch (*c)
{
case 'r':
{
long reg;
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
func (stream, "%s", arm_regnames[reg]);
}
break;
case 'd':
{
long reg;
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
func (stream, "%d", reg);
}
break;
case 'x':
{
long reg;
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
func (stream, "0x%08x", reg);
/* Some SWI instructions have special
meanings. */
if ((given & 0x0fffffff) == 0x0FF00000)
......@@ -1089,20 +1089,20 @@ print_insn_arm1 (pc, info, given)
case 'X':
{
long reg;
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
func (stream, "%01x", reg & 0xf);
}
break;
case 'f':
{
long reg;
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
if (reg > 7)
func (stream, "#%s",
arm_fp_const[reg & 7]);
......@@ -1163,7 +1163,7 @@ print_insn_arm1 (pc, info, given)
}
break;
default:
abort ();
}
......@@ -1252,7 +1252,7 @@ print_insn_thumb (pc, info, given)
if (!*c) /* Check for empty (not NULL) assembler string. */
{
long offset;
info->bytes_per_chunk = 4;
info->bytes_per_line = 4;
......@@ -1274,16 +1274,16 @@ print_insn_thumb (pc, info, given)
{
info->bytes_per_chunk = 2;
info->bytes_per_line = 4;
given &= 0xffff;
for (; *c; c++)
{
if (*c == '%')
{
int domaskpc = 0;
int domasklr = 0;
switch (*++c)
{
case '%':
......@@ -1293,11 +1293,11 @@ print_insn_thumb (pc, info, given)
case 'S':
{
long reg;
reg = (given >> 3) & 0x7;
if (given & (1 << 6))
reg += 8;
func (stream, "%s", arm_regnames[reg]);
}
break;
......@@ -1305,11 +1305,11 @@ print_insn_thumb (pc, info, given)
case 'D':
{
long reg;
reg = given & 0x7;
if (given & (1 << 7))
reg += 8;
func (stream, "%s", arm_regnames[reg]);
}
break;
......@@ -1331,9 +1331,9 @@ print_insn_thumb (pc, info, given)
{
int started = 0;
int reg;
func (stream, "{");
/* It would be nice if we could spot
ranges, and generate the rS-rE format: */
for (reg = 0; (reg < 8); reg++)
......@@ -1365,12 +1365,12 @@ print_insn_thumb (pc, info, given)
break;
case '0': case '1': case '2': case '3': case '4':
case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
{
int bitstart = *c++ - '0';
int bitend = 0;
while (*c >= '0' && *c <= '9')
bitstart = (bitstart * 10) + *c++ - '0';
......@@ -1379,7 +1379,7 @@ print_insn_thumb (pc, info, given)
case '-':
{
long reg;
c++;
while (*c >= '0' && *c <= '9')
bitend = (bitend * 10) + *c++ - '0';
......@@ -1478,11 +1478,11 @@ parse_arm_disassembler_option (option)
{
if (option == NULL)
return;
if (strneq (option, "reg-names-", 10))
{
int i;
option += 10;
for (i = NUM_ARM_REGNAMES; i--;)
......@@ -1491,7 +1491,7 @@ parse_arm_disassembler_option (option)
regname_selected = i;
break;
}
if (i < 0)
fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
}
......@@ -1501,7 +1501,7 @@ parse_arm_disassembler_option (option)
force_thumb = 0;
else
fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);