Commit 4e1957ac authored by Anthony Liguori's avatar Anthony Liguori

Merge commit 'ff71f2e8' into staging

* commit 'ff71f2e8': (21 commits)
  rtl8139: do the network/host communication only in normal operating mode
  rtl8139: correctly check the opmode
  net: move compute_mcast_idx() to net.h
  rtl8139: support byte read to TxStatus registers
  rtl8139: remove unused marco
  rtl8139: limit transmission buffer size in c+ mode
  pci_regs: Add PCI_EXP_TYPE_PCIE_BRIDGE
  virtio-net: add DATA_VALID flag
  pci_bridge: upper 32 bit are long registers
  pci: fix bridge IO/BASE
  pcie: drop functionality moved to core
  pci: set memory type for memory behind the bridge
  pci: add standard bridge device
  slotid: add slot id capability
  shpc: standard hot plug controller
  pci_bridge: user-friendly default bus name
  pci: make another unused extern function static
  pci: don't export an internal function
  pci_regs: Fix value of PCI_EXP_TYPE_RC_EC.
  pci: Do not check if a bus exist in pci_parse_devaddr.
  ...
parents 6da25bd5 ff71f2e8
......@@ -213,8 +213,10 @@ hw-obj-$(CONFIG_VIRTIO) += virtio-console.o
hw-obj-y += usb/libhw.o
hw-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o
hw-obj-y += fw_cfg.o
hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o
hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o pci_bridge_dev.o
hw-obj-$(CONFIG_PCI) += msix.o msi.o
hw-obj-$(CONFIG_PCI) += shpc.o
hw-obj-$(CONFIG_PCI) += slotid_cap.o
hw-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
hw-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o
hw-obj-y += watchdog.o
......
......@@ -322,33 +322,8 @@ static const uint16_t eepro100_mdi_mask[] = {
0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
};
#define POLYNOMIAL 0x04c11db6
static E100PCIDeviceInfo *eepro100_get_class(EEPRO100State *s);
/* From FreeBSD */
/* XXX: optimize */
static unsigned compute_mcast_idx(const uint8_t * ep)
{
uint32_t crc;
int carry, i, j;
uint8_t b;
crc = 0xffffffff;
for (i = 0; i < 6; i++) {
b = *ep++;
for (j = 0; j < 8; j++) {
carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
crc <<= 1;
b >>= 1;
if (carry) {
crc = ((crc ^ POLYNOMIAL) | carry);
}
}
}
return (crc & BITS(7, 2)) >> 2;
}
/* Read a 16 bit control/status (CSR) register. */
static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
{
......
......@@ -150,30 +150,6 @@ static void ne2000_update_irq(NE2000State *s)
qemu_set_irq(s->irq, (isr != 0));
}
#define POLYNOMIAL 0x04c11db6
/* From FreeBSD */
/* XXX: optimize */
static int compute_mcast_idx(const uint8_t *ep)
{
uint32_t crc;
int carry, i, j;
uint8_t b;
crc = 0xffffffff;
for (i = 0; i < 6; i++) {
b = *ep++;
for (j = 0; j < 8; j++) {
carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
crc <<= 1;
b >>= 1;
if (carry)
crc = ((crc ^ POLYNOMIAL) | carry);
}
}
return (crc >> 26);
}
static int ne2000_buffer_full(NE2000State *s)
{
int avail, index, boundary;
......
......@@ -351,31 +351,6 @@ static int open_eth_can_receive(VLANClientState *nc)
(rx_desc(s)->len_flags & RXD_E);
}
#define POLYNOMIAL 0x04c11db6
/* From FreeBSD */
/* XXX: optimize */
static unsigned compute_mcast_idx(const uint8_t *ep)
{
uint32_t crc;
int carry, i, j;
uint8_t b;
crc = 0xffffffff;
for (i = 0; i < 6; i++) {
b = *ep++;
for (j = 0; j < 8; j++) {
carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
crc <<= 1;
b >>= 1;
if (carry) {
crc = ((crc ^ POLYNOMIAL) | carry);
}
}
}
return crc >> 26;
}
static ssize_t open_eth_receive(VLANClientState *nc,
const uint8_t *buf, size_t size)
{
......
......@@ -63,6 +63,7 @@ struct BusInfo pci_bus_info = {
}
};
static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
static void pci_update_mappings(PCIDevice *d);
static void pci_set_irq(void *opaque, int irq_num, int level);
static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
......@@ -478,7 +479,7 @@ static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
* Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
* [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
*/
int pci_parse_devaddr(const char *addr, int *domp, int *busp,
static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
unsigned int *slotp, unsigned int *funcp)
{
const char *p;
......@@ -529,10 +530,6 @@ int pci_parse_devaddr(const char *addr, int *domp, int *busp,
if (*e)
return -1;
/* Note: QEMU doesn't implement domains other than 0 */
if (!pci_find_bus(pci_find_root_bus(dom), bus))
return -1;
*domp = dom;
*busp = bus;
*slotp = slot;
......@@ -562,7 +559,7 @@ PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
if (!devaddr) {
*devfnp = -1;
return pci_find_bus(pci_find_root_bus(0), 0);
return pci_find_bus_nr(pci_find_root_bus(0), 0);
}
if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
......@@ -570,7 +567,7 @@ PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
}
*devfnp = PCI_DEVFN(slot, 0);
return pci_find_bus(pci_find_root_bus(dom), bus);
return pci_find_bus_nr(pci_find_root_bus(dom), bus);
}
static void pci_init_cmask(PCIDevice *dev)
......@@ -636,8 +633,8 @@ static void pci_init_mask_bridge(PCIDevice *d)
memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
/* Supported memory and i/o types */
d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_32;
d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_32;
d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
PCI_PREF_RANGE_TYPE_64);
pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
......@@ -666,8 +663,11 @@ static void pci_init_mask_bridge(PCIDevice *d)
pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
PCI_BRIDGE_CTL_DISCARD_STATUS);
d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
PCI_PREF_RANGE_TYPE_MASK);
pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
PCI_PREF_RANGE_TYPE_MASK);
}
static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
......@@ -1143,7 +1143,7 @@ static void pci_for_each_device_under_bus(PCIBus *bus,
void pci_for_each_device(PCIBus *bus, int bus_num,
void (*fn)(PCIBus *b, PCIDevice *d))
{
bus = pci_find_bus(bus, bus_num);
bus = pci_find_bus_nr(bus, bus_num);
if (bus) {
pci_for_each_device_under_bus(bus, fn);
......@@ -1230,7 +1230,7 @@ static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
if (dev->config[PCI_SECONDARY_BUS] != 0) {
PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
if (child_bus) {
info->has_devices = true;
info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
......@@ -1309,7 +1309,7 @@ static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
{
PciInfo *info = NULL;
bus = pci_find_bus(bus, bus_num);
bus = pci_find_bus_nr(bus, bus_num);
if (bus) {
info = g_malloc0(sizeof(*info));
info->bus = bus_num;
......@@ -1419,7 +1419,7 @@ static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
bus_num <= dev->config[PCI_SUBORDINATE_BUS];
}
PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
{
PCIBus *sec;
......@@ -1455,7 +1455,7 @@ PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
{
bus = pci_find_bus(bus, bus_num);
bus = pci_find_bus_nr(bus, bus_num);
if (!bus)
return NULL;
......
......@@ -126,6 +126,11 @@ enum {
/* command register SERR bit enabled */
#define QEMU_PCI_CAP_SERR_BITNR 4
QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
/* Standard hot plug controller. */
#define QEMU_PCI_SHPC_BITNR 5
QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
#define QEMU_PCI_SLOTID_BITNR 6
QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
};
#define TYPE_PCI_DEVICE "pci-device"
......@@ -230,6 +235,9 @@ struct PCIDevice {
/* PCI Express */
PCIExpressDevice exp;
/* SHPC */
SHPCDevice *shpc;
/* Location of option rom */
char *romfile;
bool has_rom;
......@@ -299,13 +307,10 @@ int pci_bus_num(PCIBus *s);
void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
PCIBus *pci_find_root_bus(int domain);
int pci_find_domain(const PCIBus *bus);
PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
int pci_qdev_find_device(const char *id, PCIDevice **pdev);
PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
int pci_parse_devaddr(const char *addr, int *domp, int *busp,
unsigned int *slotp, unsigned int *funcp);
int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
unsigned *slotp);
......
......@@ -249,8 +249,8 @@ void pci_bridge_disable_base_limit(PCIDevice *dev)
PCI_PREF_RANGE_MASK & 0xffff);
pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
PCI_PREF_RANGE_MASK & 0xffff);
pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0);
pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0);
pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
}
/* reset bridge specific configuration registers */
......@@ -285,8 +285,8 @@ void pci_bridge_reset_reg(PCIDevice *dev)
PCI_PREF_RANGE_MASK & 0xffff);
pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
PCI_PREF_RANGE_MASK & 0xffff);
pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0);
pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0);
pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
pci_set_word(conf + PCI_BRIDGE_CONTROL, 0);
}
......@@ -305,8 +305,8 @@ int pci_bridge_initfn(PCIDevice *dev)
PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
PCIBus *sec_bus = &br->sec_bus;
pci_set_word(dev->config + PCI_STATUS,
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
pci_word_test_and_set_mask(dev->config + PCI_STATUS,
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
dev->config[PCI_HEADER_TYPE] =
(dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
......@@ -314,6 +314,16 @@ int pci_bridge_initfn(PCIDevice *dev)
pci_set_word(dev->config + PCI_SEC_STATUS,
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
/*
* If we don't specify the name, the bus will be addressed as <id>.0, where
* id is the device id.
* Since PCI Bridge devices have a single bus each, we don't need the index:
* let users address the bus using the device name.
*/
if (!br->bus_name && dev->qdev.id && *dev->qdev.id) {
br->bus_name = dev->qdev.id;
}
qbus_create_inplace(&sec_bus->qbus, &pci_bus_info, &dev->qdev,
br->bus_name);
sec_bus->parent_dev = dev;
......
/*
* Standard PCI Bridge Device
*
* Copyright (c) 2011 Red Hat Inc. Author: Michael S. Tsirkin <mst@redhat.com>
*
* http://www.pcisig.com/specifications/conventional/pci_to_pci_bridge_architecture/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "pci_bridge.h"
#include "pci_ids.h"
#include "msi.h"
#include "shpc.h"
#include "slotid_cap.h"
#include "memory.h"
#include "pci_internals.h"
#define REDHAT_PCI_VENDOR_ID 0x1b36
#define PCI_BRIDGE_DEV_VENDOR_ID REDHAT_PCI_VENDOR_ID
#define PCI_BRIDGE_DEV_DEVICE_ID 0x1
struct PCIBridgeDev {
PCIBridge bridge;
MemoryRegion bar;
uint8_t chassis_nr;
#define PCI_BRIDGE_DEV_F_MSI_REQ 0
uint32_t flags;
};
typedef struct PCIBridgeDev PCIBridgeDev;
/* Mapping mandated by PCI-to-PCI Bridge architecture specification,
* revision 1.2 */
/* Table 9-1: Interrupt Binding for Devices Behind a Bridge */
static int pci_bridge_dev_map_irq_fn(PCIDevice *dev, int irq_num)
{
return (irq_num + PCI_SLOT(dev->devfn)) % PCI_NUM_PINS;
}
static int pci_bridge_dev_initfn(PCIDevice *dev)
{
PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
int err;
pci_bridge_map_irq(br, NULL, pci_bridge_dev_map_irq_fn);
err = pci_bridge_initfn(dev);
if (err) {
goto bridge_error;
}
memory_region_init(&bridge_dev->bar, "shpc-bar", shpc_bar_size(dev));
err = shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0);
if (err) {
goto shpc_error;
}
err = slotid_cap_init(dev, 0, bridge_dev->chassis_nr, 0);
if (err) {
goto slotid_error;
}
if ((bridge_dev->flags & (1 << PCI_BRIDGE_DEV_F_MSI_REQ)) &&
msi_supported) {
err = msi_init(dev, 0, 1, true, true);
if (err < 0) {
goto msi_error;
}
}
/* TODO: spec recommends using 64 bit prefetcheable BAR.
* Check whether that works well. */
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
PCI_BASE_ADDRESS_MEM_TYPE_64, &bridge_dev->bar);
dev->config[PCI_INTERRUPT_PIN] = 0x1;
return 0;
msi_error:
slotid_cap_cleanup(dev);
slotid_error:
shpc_cleanup(dev, &bridge_dev->bar);
shpc_error:
memory_region_destroy(&bridge_dev->bar);
bridge_error:
return err;
}
static int pci_bridge_dev_exitfn(PCIDevice *dev)
{
PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
int ret;
if (msi_present(dev)) {
msi_uninit(dev);
}
slotid_cap_cleanup(dev);
shpc_cleanup(dev, &bridge_dev->bar);
memory_region_destroy(&bridge_dev->bar);
ret = pci_bridge_exitfn(dev);
assert(!ret);
return 0;
}
static void pci_bridge_dev_write_config(PCIDevice *d,
uint32_t address, uint32_t val, int len)
{
pci_bridge_write_config(d, address, val, len);
if (msi_present(d)) {
msi_write_config(d, address, val, len);
}
shpc_cap_write_config(d, address, val, len);
}
static void qdev_pci_bridge_dev_reset(DeviceState *qdev)
{
PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
pci_bridge_reset(qdev);
if (msi_present(dev)) {
msi_reset(dev);
}
shpc_reset(dev);
}
static Property pci_bridge_dev_properties[] = {
/* Note: 0 is not a legal chassis number. */
DEFINE_PROP_UINT8("chassis_nr", PCIBridgeDev, chassis_nr, 0),
DEFINE_PROP_BIT("msi", PCIBridgeDev, flags, PCI_BRIDGE_DEV_F_MSI_REQ, true),
DEFINE_PROP_END_OF_LIST(),
};
static const VMStateDescription pci_bridge_dev_vmstate = {
.name = "pci_bridge",
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(bridge.dev, PCIBridgeDev),
SHPC_VMSTATE(bridge.dev.shpc, PCIBridgeDev),
VMSTATE_END_OF_LIST()
}
};
static void pci_bridge_dev_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_bridge_dev_initfn;
k->exit = pci_bridge_dev_exitfn;
k->config_write = pci_bridge_dev_write_config;
k->vendor_id = PCI_BRIDGE_DEV_VENDOR_ID;
k->device_id = PCI_BRIDGE_DEV_DEVICE_ID;
k->class_id = PCI_CLASS_BRIDGE_PCI;
k->is_bridge = 1,
dc->desc = "Standard PCI Bridge";
dc->reset = qdev_pci_bridge_dev_reset;
dc->props = pci_bridge_dev_properties;
dc->vmsd = &pci_bridge_dev_vmstate;
}
static TypeInfo pci_bridge_dev_info = {
.name = "pci-bridge",
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIBridgeDev),
.class_init = pci_bridge_dev_class_init,
};
static void pci_bridge_dev_register(void)
{
type_register_static(&pci_bridge_dev_info);
}
type_init(pci_bridge_dev_register);
......@@ -392,8 +392,9 @@
#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
#define PCI_EXP_TYPE_RC_EC 0x10 /* Root Complex Event Collector */
#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */
#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
#define PCI_EXP_DEVCAP 4 /* Device capabilities */
......
......@@ -27,23 +27,13 @@ void pcie_port_init_reg(PCIDevice *d)
pci_set_word(d->config + PCI_STATUS, 0);
pci_set_word(d->config + PCI_SEC_STATUS, 0);
/* Unlike conventional pci bridge, some bits are hardwared to 0. */
/* Unlike conventional pci bridge, some bits are hardwired to 0. */
pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
PCI_BRIDGE_CTL_PARITY |
PCI_BRIDGE_CTL_ISA |
PCI_BRIDGE_CTL_VGA |
PCI_BRIDGE_CTL_SERR |
PCI_BRIDGE_CTL_BUS_RESET);
/* 7.5.3.5 Prefetchable Memory Base Limit
* The Prefetchable Memory Base and Prefetchable Memory Limit registers
* must indicate that 64-bit addresses are supported, as defined in
* PCI-to-PCI Bridge Architecture Specification, Revision 1.2.
*/
pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
PCI_PREF_RANGE_TYPE_64);
pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
PCI_PREF_RANGE_TYPE_64);
}
/**************************************************************************
......
......@@ -65,9 +65,6 @@
#define PCI_FREQUENCY 33000000L
/* debug RTL8139 card C+ mode only */
//#define DEBUG_RTL8139CP 1
#define SET_MASKED(input, mask, curr) \
( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
......@@ -335,8 +332,10 @@ enum CSCRBits {
};
enum Cfg9346Bits {
Cfg9346_Lock = 0x00,
Cfg9346_Unlock = 0xC0,
Cfg9346_Normal = 0x00,
Cfg9346_Autoload = 0x40,
Cfg9346_Programming = 0x80,
Cfg9346_ConfigWrite = 0xC0,
};
typedef enum {
......@@ -711,30 +710,6 @@ static void rtl8139_update_irq(RTL8139State *s)
qemu_set_irq(s->dev.irq[0], (isr != 0));
}
#define POLYNOMIAL 0x04c11db6
/* From FreeBSD */
/* XXX: optimize */
static int compute_mcast_idx(const uint8_t *ep)
{
uint32_t crc;
int carry, i, j;
uint8_t b;
crc = 0xffffffff;
for (i = 0; i < 6; i++) {
b = *ep++;
for (j = 0; j < 8; j++) {
carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
crc <<= 1;
b >>= 1;
if (carry)
crc = ((crc ^ POLYNOMIAL) | carry);
}
}
return (crc >> 26);
}
static int rtl8139_RxWrap(RTL8139State *s)
{
/* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
......@@ -816,6 +791,9 @@ static int rtl8139_can_receive(VLANClientState *nc)
return 1;
if (!rtl8139_receiver_enabled(s))
return 1;
/* network/host communication happens only in normal mode */
if ((s->Cfg9346 & Chip9346_op_mask) != Cfg9346_Normal)
return 0;
if (rtl8139_cp_receiver_enabled(s)) {
/* ??? Flow control not implemented in c+ mode.
......@@ -858,6 +836,12 @@ static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_
return -1;
}
/* check whether we are in normal mode */
if ((s->Cfg9346 & Chip9346_op_mask) != Cfg9346_Normal) {
DPRINTF("not in normal op mode\n");
return -1;
}
/* XXX: check this */
if (s->RxConfig & AcceptAllPhys) {
/* promiscuous: receive all */
......@@ -1478,7 +1462,7 @@ static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
static int rtl8139_config_writable(RTL8139State *s)
{
if (s->Cfg9346 & Cfg9346_Unlock)
if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite)
{
return 1;
}
......@@ -2061,13 +2045,12 @@ static int rtl8139_cplus_transmit_one(RTL8139State *s)
s->cplus_txbuffer_len);
}
while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
{
s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
s->cplus_txbuffer = g_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
DPRINTF("+++ C+ mode transmission buffer space changed to %d\n",
s->cplus_txbuffer_len);
/* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */
txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset;
DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor"
"length to %d\n", txsize);
}
if (!s->cplus_txbuffer)
......@@ -2499,11 +2482,30 @@ static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32
rtl8139_transmit(s);
}
static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint8_t addr, int size)
{
uint32_t ret = s->TxStatus[txRegOffset/4];
uint32_t reg = (addr - TxStatus0) / 4;
uint32_t offset = addr & 0x3;
uint32_t ret = 0;
DPRINTF("TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret);
if (addr & (size - 1)) {
DPRINTF("not implemented read for TxStatus addr=0x%x size=0x%x\n", addr,
size);
return ret;
}
switch (size) {
case 1: /* fall through */
case 2: /* fall through */
case 4:
ret = (s->TxStatus[reg] >> offset * 8) & ((1 << (size * 8)) - 1);
DPRINTF("TxStatus[%d] read addr=0x%x size=0x%x val=0x%08x\n", reg, addr,
size, ret);
break;
default:
DPRINTF("unsupported size 0x%x of TxStatus reading\n", size);
break;
}
return ret;
}
......@@ -2974,6 +2976,9 @@ static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
case MAR0 ... MAR0+7:
ret = s->mult[addr - MAR0];
break;
case TxStatus0 ... TxStatus0+4*4-1:
ret = rtl8139_TxStatus_read(s, addr, 1);
break;
case ChipCmd:
ret = rtl8139_ChipCmd_read(s);
break;
......@@ -3037,6 +3042,9 @@ static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
switch (addr)
{
case TxAddr0 ... TxAddr0+4*4-1:
ret = rtl8139_TxStatus_read(s, addr, 2);
break;
case IntrMask:
ret = rtl8139_IntrMask_read(s);
break;
......@@ -3127,7 +3135,7 @@ static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
break;
case TxStatus0 ... TxStatus0+4*4-1:
ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
ret = rtl8139_TxStatus_read(s, addr, 4);
break;
case TxAddr0 ... TxAddr0+4*4-1:
......
This diff is collapsed.
#ifndef SHPC_H
#define SHPC_H
#include "qemu-common.h"
#include "memory.h"
#include "vmstate.h"
struct SHPCDevice {
/* Capability offset in device's config space */
int cap;
/* # of hot-pluggable slots */
int nslots;
/* SHPC WRS: working register set */
uint8_t *config;
/* Used to enable checks on load. Note that writable bits are
* never checked even if set in cmask. */
uint8_t *cmask;
/* Used to implement R/W bytes */
uint8_t *wmask;
/* Used to implement RW1C(Write 1 to Clear) bytes */
uint8_t *w1cmask;
/* MMIO for the SHPC BAR */
MemoryRegion mmio;
/* Bus controlled by this SHPC */
PCIBus *sec_bus;
/* MSI already requested for this event */
int msi_requested;
};
void shpc_reset(PCIDevice *d);
int shpc_bar_size(PCIDevice *dev);
int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned off);
void shpc_cleanup(PCIDevice *dev, MemoryRegion *bar);
void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len);
extern VMStateInfo shpc_vmstate_info;
#define SHPC_VMSTATE(_field, _type) \
VMSTATE_BUFFER_UNSAFE_INFO(_field, _type, 0, shpc_vmstate_info, 0)
#endif
#include "slotid_cap.h"
#include "pci.h"
#define SLOTID_CAP_LENGTH 4
#define SLOTID_NSLOTS_SHIFT (ffs(PCI_SID_ESR_NSLOTS) - 1)
int slotid_cap_init(PCIDevice *d, int nslots,
uint8_t chassis,
unsigned offset)
{