Commit 2e134c9c authored by bellard's avatar bellard
Browse files

64-bit multiplication fix (Ulrich Hecht)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@446 c046a42c-6fe2-441c-8c8c-71466251a162
parent 5391d806
...@@ -368,7 +368,7 @@ void OPPROTO op_mul_T0_T1(void) ...@@ -368,7 +368,7 @@ void OPPROTO op_mul_T0_T1(void)
void OPPROTO op_mull_T0_T1(void) void OPPROTO op_mull_T0_T1(void)
{ {
uint64_t res; uint64_t res;
res = T0 * T1; res = (uint64_t)T0 * (uint64_t)T1;
T1 = res >> 32; T1 = res >> 32;
T0 = res; T0 = res;
} }
...@@ -377,7 +377,7 @@ void OPPROTO op_mull_T0_T1(void) ...@@ -377,7 +377,7 @@ void OPPROTO op_mull_T0_T1(void)
void OPPROTO op_imull_T0_T1(void) void OPPROTO op_imull_T0_T1(void)
{ {
uint64_t res; uint64_t res;
res = (int32_t)T0 * (int32_t)T1; res = (int64_t)T0 * (int64_t)T1;
T1 = res >> 32; T1 = res >> 32;
T0 = res; T0 = res;
} }
......
...@@ -516,9 +516,9 @@ static void disas_arm_insn(DisasContext *s) ...@@ -516,9 +516,9 @@ static void disas_arm_insn(DisasContext *s)
gen_movl_T0_reg(s, rs); gen_movl_T0_reg(s, rs);
gen_movl_T1_reg(s, rm); gen_movl_T1_reg(s, rm);
if (insn & (1 << 22)) if (insn & (1 << 22))
gen_op_mull_T0_T1();
else
gen_op_imull_T0_T1(); gen_op_imull_T0_T1();
else
gen_op_mull_T0_T1();
if (insn & (1 << 21)) if (insn & (1 << 21))
gen_op_addq_T0_T1(rn, rd); gen_op_addq_T0_T1(rn, rd);
if (insn & (1 << 20)) if (insn & (1 << 20))
......
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