Commit 27c7ca7e authored by bellard's avatar bellard
Browse files

SHIX board emulation (Samuel Tardieu)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1862 c046a42c-6fe2-441c-8c8c-71466251a162
parent fdf9b3e8
......@@ -6,6 +6,7 @@ version 0.8.1:
- IDE LBA48 support (Jens Axboe)
- SSE3 support
- Solaris port (Ben Taylor)
- Preliminary SH4 target (Samuel Tardieu)
version 0.8.0:
......
......@@ -476,10 +476,10 @@ ifeq ($(TARGET_ARCH), sh4)
op.o: op.c op_mem.c cpu.h
op_helper.o: op_helper.c exec.h cpu.h
helper.o: helper.c exec.h cpu.h
sh7750.o: sh7750.c sh7750.h sh7750_regs.h sh7750_regnames.h cpu.h
shix.o: shix.c sh7750.h sh7750_regs.h sh7750_regnames.h tc58128.h
sh7750.o: sh7750.c sh7750_regs.h sh7750_regnames.h cpu.h
shix.o: shix.c sh7750_regs.h sh7750_regnames.h
sh7750_regnames.o: sh7750_regnames.c sh7750_regnames.h sh7750_regs.h
tc58128.o: tc58128.c tc58128.h sh7750.h
tc58128.o: tc58128.c
endif
%.o: %.c
......
This diff is collapsed.
#include "vl.h"
#include "sh7750_regs.h"
#define REGNAME(r) {r, #r},
typedef struct {
uint32_t regaddr;
const char *regname;
} regname_t;
static regname_t regnames[] = {
REGNAME(SH7750_PTEH_A7)
REGNAME(SH7750_PTEL_A7)
REGNAME(SH7750_PTEA_A7)
REGNAME(SH7750_TTB_A7)
REGNAME(SH7750_TEA_A7)
REGNAME(SH7750_MMUCR_A7)
REGNAME(SH7750_CCR_A7)
REGNAME(SH7750_QACR0_A7)
REGNAME(SH7750_QACR1_A7)
REGNAME(SH7750_TRA_A7)
REGNAME(SH7750_EXPEVT_A7)
REGNAME(SH7750_INTEVT_A7)
REGNAME(SH7750_STBCR_A7)
REGNAME(SH7750_STBCR2_A7)
REGNAME(SH7750_FRQCR_A7)
REGNAME(SH7750_WTCNT_A7)
REGNAME(SH7750_WTCSR_A7)
REGNAME(SH7750_R64CNT_A7)
REGNAME(SH7750_RSECCNT_A7)
REGNAME(SH7750_RMINCNT_A7)
REGNAME(SH7750_RHRCNT_A7)
REGNAME(SH7750_RWKCNT_A7)
REGNAME(SH7750_RDAYCNT_A7)
REGNAME(SH7750_RMONCNT_A7)
REGNAME(SH7750_RYRCNT_A7)
REGNAME(SH7750_RSECAR_A7)
REGNAME(SH7750_RMINAR_A7)
REGNAME(SH7750_RHRAR_A7)
REGNAME(SH7750_RWKAR_A7)
REGNAME(SH7750_RDAYAR_A7)
REGNAME(SH7750_RMONAR_A7)
REGNAME(SH7750_RCR1_A7)
REGNAME(SH7750_RCR2_A7)
REGNAME(SH7750_TOCR_A7)
REGNAME(SH7750_TSTR_A7)
REGNAME(SH7750_TCOR0_A7)
REGNAME(SH7750_TCOR1_A7)
REGNAME(SH7750_TCOR2_A7)
REGNAME(SH7750_TCNT0_A7)
REGNAME(SH7750_TCNT1_A7)
REGNAME(SH7750_TCNT2_A7)
REGNAME(SH7750_TCR0_A7)
REGNAME(SH7750_TCR1_A7)
REGNAME(SH7750_TCR2_A7)
REGNAME(SH7750_TCPR2_A7)
REGNAME(SH7750_BCR1_A7)
REGNAME(SH7750_BCR2_A7)
REGNAME(SH7750_WCR1_A7)
REGNAME(SH7750_WCR2_A7)
REGNAME(SH7750_WCR3_A7)
REGNAME(SH7750_MCR_A7)
REGNAME(SH7750_PCR_A7)
REGNAME(SH7750_RTCSR_A7)
REGNAME(SH7750_RTCNT_A7)
REGNAME(SH7750_RTCOR_A7)
REGNAME(SH7750_RFCR_A7)
REGNAME(SH7750_SAR0_A7)
REGNAME(SH7750_SAR1_A7)
REGNAME(SH7750_SAR2_A7)
REGNAME(SH7750_SAR3_A7)
REGNAME(SH7750_DAR0_A7)
REGNAME(SH7750_DAR1_A7)
REGNAME(SH7750_DAR2_A7)
REGNAME(SH7750_DAR3_A7)
REGNAME(SH7750_DMATCR0_A7)
REGNAME(SH7750_DMATCR1_A7)
REGNAME(SH7750_DMATCR2_A7)
REGNAME(SH7750_DMATCR3_A7)
REGNAME(SH7750_CHCR0_A7)
REGNAME(SH7750_CHCR1_A7)
REGNAME(SH7750_CHCR2_A7)
REGNAME(SH7750_CHCR3_A7)
REGNAME(SH7750_DMAOR_A7)
REGNAME(SH7750_SCRDR1_A7)
REGNAME(SH7750_SCRDR2_A7)
REGNAME(SH7750_SCTDR1_A7)
REGNAME(SH7750_SCTDR2_A7)
REGNAME(SH7750_SCSMR1_A7)
REGNAME(SH7750_SCSMR2_A7)
REGNAME(SH7750_SCSCR1_A7)
REGNAME(SH7750_SCSCR2_A7)
REGNAME(SH7750_SCSSR1_A7)
REGNAME(SH7750_SCSFR2_A7)
REGNAME(SH7750_SCSPTR1_A7)
REGNAME(SH7750_SCSPTR2_A7)
REGNAME(SH7750_SCBRR1_A7)
REGNAME(SH7750_SCBRR2_A7)
REGNAME(SH7750_SCFCR2_A7)
REGNAME(SH7750_SCFDR2_A7)
REGNAME(SH7750_SCLSR2_A7)
REGNAME(SH7750_SCSCMR1_A7)
REGNAME(SH7750_PCTRA_A7)
REGNAME(SH7750_PDTRA_A7)
REGNAME(SH7750_PCTRB_A7)
REGNAME(SH7750_PDTRB_A7)
REGNAME(SH7750_GPIOIC_A7)
REGNAME(SH7750_ICR_A7)
REGNAME(SH7750_IPRA_A7)
REGNAME(SH7750_IPRB_A7)
REGNAME(SH7750_IPRC_A7)
REGNAME(SH7750_BCR3_A7)
REGNAME(SH7750_BCR4_A7)
REGNAME(SH7750_PRECHARGE0_A7)
REGNAME(SH7750_PRECHARGE1_A7) {(uint32_t) - 1, 0}
};
const char *regname(uint32_t addr)
{
unsigned int i;
for (i = 0; regnames[i].regaddr != (uint32_t) - 1; i++) {
if (regnames[i].regaddr == addr)
return regnames[i].regname;
}
return "<unknown reg>";
}
#ifndef _SH7750_REGNAMES_H
#define _SH7750_REGNAMES_H
const char *regname(uint32_t addr);
#endif /* _SH7750_REGNAMES_H */
This diff is collapsed.
/*
* SHIX 2.0 board description
*
* Copyright (c) 2005 Samuel Tardieu
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
/*
Shix 2.0 board by Alexis Polti, described at
http://perso.enst.fr/~polti/realisations/shix20/
More information in target-sh4/README.sh4
*/
#include "vl.h"
#define BIOS_FILENAME "shix_bios.bin"
#define BIOS_ADDRESS 0xA0000000
void DMA_run(void)
{
/* XXXXX */
}
void irq_info(void)
{
/* XXXXX */
}
void pic_set_irq(int irq, int level)
{
/* XXXXX */
}
void pic_info()
{
/* XXXXX */
}
void vga_update_display()
{
/* XXXXX */
}
void vga_invalidate_display()
{
/* XXXXX */
}
void vga_screen_dump(const char *filename)
{
/* XXXXX */
}
void shix_init(int ram_size, int vga_ram_size, int boot_device,
DisplayState * ds, const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename)
{
int ret;
CPUState *env;
struct SH7750State *s;
printf("Initializing CPU\n");
env = cpu_init();
/* Allocate memory space */
printf("Allocating ROM\n");
cpu_register_physical_memory(0x00000000, 0x00004000, IO_MEM_ROM);
printf("Allocating SDRAM 1\n");
cpu_register_physical_memory(0x08000000, 0x01000000, 0x00004000);
printf("Allocating SDRAM 2\n");
cpu_register_physical_memory(0x0c000000, 0x01000000, 0x01004000);
/* Load BIOS in 0 (and access it through P2, 0xA0000000) */
printf("%s: load BIOS '%s'\n", __func__, BIOS_FILENAME);
ret = load_image(BIOS_FILENAME, phys_ram_base);
if (ret < 0) { /* Check bios size */
fprintf(stderr, "ret=%d\n", ret);
fprintf(stderr, "qemu: could not load SHIX bios '%s'\n",
BIOS_FILENAME);
exit(1);
}
/* Register peripherals */
s = sh7750_init(env);
/* XXXXX Check success */
tc58128_init(s, "shix_linux_nand.bin", NULL);
fprintf(stderr, "initialization terminated\n");
}
QEMUMachine shix_machine = {
"shix",
"shix card",
shix_init
};
#include <assert.h>
#include "vl.h"
#define CE1 0x0100
#define CE2 0x0200
#define RE 0x0400
#define WE 0x0800
#define ALE 0x1000
#define CLE 0x2000
#define RDY1 0x4000
#define RDY2 0x8000
#define RDY(n) ((n) == 0 ? RDY1 : RDY2)
typedef enum { WAIT, READ1, READ2, READ3 } state_t;
typedef struct {
uint8_t *flash_contents;
state_t state;
uint32_t address;
uint8_t address_cycle;
} tc58128_dev;
static tc58128_dev tc58128_devs[2];
#define FLASH_SIZE (16*1024*1024)
void init_dev(tc58128_dev * dev, char *filename)
{
int ret, blocks;
dev->state = WAIT;
dev->flash_contents = qemu_mallocz(FLASH_SIZE);
memset(dev->flash_contents, 0xff, FLASH_SIZE);
if (!dev->flash_contents) {
fprintf(stderr, "could not alloc memory for flash\n");
exit(1);
}
if (filename) {
/* Load flash image skipping the first block */
ret = load_image(filename, dev->flash_contents + 528 * 32);
if (ret < 0) {
fprintf(stderr, "ret=%d\n", ret);
fprintf(stderr, "qemu: could not load flash image %s\n",
filename);
exit(1);
} else {
/* Build first block with number of blocks */
blocks = (ret + 528 * 32 - 1) / (528 * 32);
dev->flash_contents[0] = blocks & 0xff;
dev->flash_contents[1] = (blocks >> 8) & 0xff;
dev->flash_contents[2] = (blocks >> 16) & 0xff;
dev->flash_contents[3] = (blocks >> 24) & 0xff;
fprintf(stderr, "loaded %d bytes for %s into flash\n", ret,
filename);
}
}
}
void handle_command(tc58128_dev * dev, uint8_t command)
{
switch (command) {
case 0xff:
fprintf(stderr, "reset flash device\n");
dev->state = WAIT;
break;
case 0x00:
fprintf(stderr, "read mode 1\n");
dev->state = READ1;
dev->address_cycle = 0;
break;
case 0x01:
fprintf(stderr, "read mode 2\n");
dev->state = READ2;
dev->address_cycle = 0;
break;
case 0x50:
fprintf(stderr, "read mode 3\n");
dev->state = READ3;
dev->address_cycle = 0;
break;
default:
fprintf(stderr, "unknown flash command 0x%02x\n", command);
assert(0);
}
}
void handle_address(tc58128_dev * dev, uint8_t data)
{
switch (dev->state) {
case READ1:
case READ2:
case READ3:
switch (dev->address_cycle) {
case 0:
dev->address = data;
if (dev->state == READ2)
dev->address |= 0x100;
else if (dev->state == READ3)
dev->address |= 0x200;
break;
case 1:
dev->address += data * 528 * 0x100;
break;
case 2:
dev->address += data * 528;
fprintf(stderr, "address pointer in flash: 0x%08x\n",
dev->address);
break;
default:
/* Invalid data */
assert(0);
}
dev->address_cycle++;
break;
default:
assert(0);
}
}
uint8_t handle_read(tc58128_dev * dev)
{
#if 0
if (dev->address % 0x100000 == 0)
fprintf(stderr, "reading flash at address 0x%08x\n", dev->address);
#endif
return dev->flash_contents[dev->address++];
}
/* We never mark the device as busy, so interrupts cannot be triggered
XXXXX */
int tc58128_cb(uint16_t porta, uint16_t portb,
uint16_t * periph_pdtra, uint16_t * periph_portadir,
uint16_t * periph_pdtrb, uint16_t * periph_portbdir)
{
int dev;
if ((porta & CE1) == 0)
dev = 0;
else if ((porta & CE2) == 0)
dev = 1;
else
return 0; /* No device selected */
if ((porta & RE) && (porta & WE)) {
/* Nothing to do, assert ready and return to input state */
*periph_portadir &= 0xff00;
*periph_portadir |= RDY(dev);
*periph_pdtra |= RDY(dev);
return 1;
}
if (porta & CLE) {
/* Command */
assert((porta & WE) == 0);
handle_command(&tc58128_devs[dev], porta & 0x00ff);
} else if (porta & ALE) {
assert((porta & WE) == 0);
handle_address(&tc58128_devs[dev], porta & 0x00ff);
} else if ((porta & RE) == 0) {
*periph_portadir |= 0x00ff;
*periph_pdtra &= 0xff00;
*periph_pdtra |= handle_read(&tc58128_devs[dev]);
} else {
assert(0);
}
return 1;
}
static sh7750_io_device tc58128 = {
RE | WE, /* Port A triggers */
0, /* Port B triggers */
tc58128_cb /* Callback */
};
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2)
{
init_dev(&tc58128_devs[0], zone1);
init_dev(&tc58128_devs[1], zone2);
return sh7750_register_io_device(s, &tc58128);
}
qemu target: sh4
author: Samuel Tardieu <sam@rfc1149.net>
last modified: Tue Dec 6 07:22:44 CET 2005
The sh4 target is not ready at all yet for integration in qemu. This
file describes the current state of implementation.
Most places requiring attention and/or modification can be detected by
looking for "XXXXX" or "assert (0)".
The sh4 core is located in target-sh4/*, while the 7750 peripheral
features (IO ports for example) are located in hw/sh7750.[ch]. The
main board description is in hw/shix.c, and the NAND flash in
hw/tc58128.[ch].
All the shortcomings indicated here will eventually be resolved. This
is a work in progress. Features are added in a semi-random order: if a
point is blocking to progress on booting the Linux kernel for the shix
board, it is addressed first; if feedback is necessary and no progress
can be made on blocking points until it is received, a random feature
is worked on.
Goals
-----
The primary model being worked on is the soft MMU target to be able to
emulate the Shix 2.0 board by Alexis Polti, described at
http://perso.enst.fr/~polti/realisations/shix20/
Ultimately, qemu will be coupled with a system C or a verilog
simulator to simulate the whole board functionalities.
A sh4 user-mode has also somewhat started but will be worked on
afterwards. The goal is to automate tests for GNAT (GNU Ada) compiler
that I ported recently to the sh4-linux target.
Registers
---------
16 general purpose registers are available at any time. The first 8
registers are banked and the non-directly visible ones can be accessed
by privileged instructions. In qemu, we define 24 general purpose
registers and the code generation use either [0-7]+[8-15] or
[16-23]+[8-15] depending on the MD and RB flags in the sr
configuration register.
Instructions
------------
Most sh4 instructions have been implemented. The missing ones at this
time are:
- FPU related instructions
- LDTLB to load a new MMU entry
- SLEEP to put the processor in sleep mode
Most instructions could be optimized a lot. This will be worked on
after the current model is fully functional unless debugging
convenience requires that it is done early.
Many instructions did not have a chance to be tested yet. The plan is
to implement unit and regression testing of those in the future.
MMU
---
The MMU is implemented in the sh4 core. MMU management has not been
tested at all yet. In the sh7750, it can be manipulated through memory
mapped registers and this part has not yet been implemented.
Exceptions
----------
Exceptions are implemented as described in the sh4 reference manual
but have not been tested yet. They do not use qemu EXCP_ features
yet.
IRQ
---
IRQ are not implemented yet.
Peripheral features
-------------------
+ Serial ports
Configuration and use of the first serial port (SCI) without
interrupts is supported. Input has not yet been tested.
Configuration of the second serial port (SCIF) is supported. FIFO
handling infrastructure has been started but is not completed yet.
+ GPIO ports
GPIO ports have been implemented. A registration function allows
external modules to register interest in some port changes (see
hw/tc58128.[ch] for an example) and will be called back. Interrupt
generation is not yet supported but some infrastructure is in place
for this purpose. Note that in the current model a peripheral module
cannot directly simulate a H->L->H input port transition and have an
interrupt generated on the low level.
+ TC58128 NAND flash
TC58128 NAND flash is partially implemented through GPIO ports. It
supports reading from flash.
GDB
---
GDB remote target support has been implemented and lightly tested.
Files
-----
File names are harcoded at this time. The bootloader must be stored in
shix_bios.bin in the current directory. The initial Linux image must
be stored in shix_linux_nand.bin in the current directory in NAND
format. Test files can be obtained from
http://perso.enst.fr/~polti/robot/ as well as the various datasheets I
use.
qemu disk parameter on the command line is unused. You can supply any
existing image and it will be ignored. As the goal is to simulate an
embedded target, it is not clear how this parameter will be handled in
the future.
To build an ELF kernel image from the NAND image, 16 bytes have to be
stripped off the end of every 528 bytes, keeping only 512 of them. The
following Python code snippet does it:
#! /usr/bin/python
def denand (infd, outfd):
while True:
d = infd.read (528)
if not d: return
outfd.write (d[:512])
if __name__ == '__main__':
import sys
denand (open (sys.argv[1], 'rb'),
open (sys.argv[2], 'wb'))
Style isssues
-------------
There is currently a mix between my style (space before opening
parenthesis) and qemu style. This will be resolved before final
integration is proposed.
......@@ -4863,6 +4863,8 @@ void register_machines(void)
qemu_register_machine(&integratorcp926_machine);
qemu_register_machine(&integratorcp1026_machine);
qemu_register_machine(&versatilepb_machine);
#elif defined(TARGET_SH4)
qemu_register_machine(&shix_machine);
#else
#error unsupported CPU
#endif
......
......@@ -842,6 +842,9 @@ extern QEMUMachine heathrow_machine;
/* mips_r4k.c */
extern QEMUMachine mips_machine;
/* shix.c */
extern QEMUMachine shix_machine;
#ifdef TARGET_PPC
ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq);
#endif
......@@ -1016,6 +1019,28 @@ void *pl190_init(uint32_t base, void *parent, int irq, int fiq);
void sp804_init(uint32_t base, void *pic, int irq);
void icp_pit_init(uint32_t base, void *pic, int irq);
/* sh7750.c */
struct SH7750State;
struct SH7750State *sh7750_init(CPUSH4State * cpu);
typedef struct {
/* The callback will be triggered if any of the designated lines change */
uint16_t portamask_trigger;
uint16_t portbmask_trigger;
/* Return 0 if no action was taken */