Commit 27103424 authored by Andreas Färber's avatar Andreas Färber

cpu: Move exception_index field from CPU_COMMON to CPUState

Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
parent 6f03bef0
......@@ -41,7 +41,7 @@ void cpu_resume_from_signal(CPUArchState *env, void *puc)
/* XXX: restore cpu registers saved in host registers */
env->exception_index = -1;
cpu->exception_index = -1;
siglongjmp(cpu->jmp_env, 1);
}
#endif
......@@ -282,16 +282,16 @@ int cpu_exec(CPUArchState *env)
#else
#error unsupported target CPU
#endif
env->exception_index = -1;
cpu->exception_index = -1;
/* prepare setjmp context for exception handling */
for(;;) {
if (sigsetjmp(cpu->jmp_env, 0) == 0) {
/* if an exception is pending, we execute it here */
if (env->exception_index >= 0) {
if (env->exception_index >= EXCP_INTERRUPT) {
if (cpu->exception_index >= 0) {
if (cpu->exception_index >= EXCP_INTERRUPT) {
/* exit request from the cpu execution loop */
ret = env->exception_index;
ret = cpu->exception_index;
if (ret == EXCP_DEBUG) {
cpu_handle_debug_exception(env);
}
......@@ -304,11 +304,11 @@ int cpu_exec(CPUArchState *env)
#if defined(TARGET_I386)
cc->do_interrupt(cpu);
#endif
ret = env->exception_index;
ret = cpu->exception_index;
break;
#else
cc->do_interrupt(cpu);
env->exception_index = -1;
cpu->exception_index = -1;
#endif
}
}
......@@ -323,7 +323,7 @@ int cpu_exec(CPUArchState *env)
}
if (interrupt_request & CPU_INTERRUPT_DEBUG) {
cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
env->exception_index = EXCP_DEBUG;
cpu->exception_index = EXCP_DEBUG;
cpu_loop_exit(env);
}
#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
......@@ -332,7 +332,7 @@ int cpu_exec(CPUArchState *env)
if (interrupt_request & CPU_INTERRUPT_HALT) {
cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
cpu->halted = 1;
env->exception_index = EXCP_HLT;
cpu->exception_index = EXCP_HLT;
cpu_loop_exit(env);
}
#endif
......@@ -347,7 +347,7 @@ int cpu_exec(CPUArchState *env)
cpu_svm_check_intercept_param(env, SVM_EXIT_INIT,
0);
do_cpu_init(x86_cpu);
env->exception_index = EXCP_HALTED;
cpu->exception_index = EXCP_HALTED;
cpu_loop_exit(env);
} else if (interrupt_request & CPU_INTERRUPT_SIPI) {
do_cpu_sipi(x86_cpu);
......@@ -419,7 +419,7 @@ int cpu_exec(CPUArchState *env)
#elif defined(TARGET_LM32)
if ((interrupt_request & CPU_INTERRUPT_HARD)
&& (env->ie & IE_IE)) {
env->exception_index = EXCP_IRQ;
cpu->exception_index = EXCP_IRQ;
cc->do_interrupt(cpu);
next_tb = 0;
}
......@@ -428,7 +428,7 @@ int cpu_exec(CPUArchState *env)
&& (env->sregs[SR_MSR] & MSR_IE)
&& !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
&& !(env->iflags & (D_FLAG | IMM_FLAG))) {
env->exception_index = EXCP_IRQ;
cpu->exception_index = EXCP_IRQ;
cc->do_interrupt(cpu);
next_tb = 0;
}
......@@ -436,7 +436,7 @@ int cpu_exec(CPUArchState *env)
if ((interrupt_request & CPU_INTERRUPT_HARD) &&
cpu_mips_hw_interrupts_pending(env)) {
/* Raise it */
env->exception_index = EXCP_EXT_INTERRUPT;
cpu->exception_index = EXCP_EXT_INTERRUPT;
env->error_code = 0;
cc->do_interrupt(cpu);
next_tb = 0;
......@@ -453,7 +453,7 @@ int cpu_exec(CPUArchState *env)
idx = EXCP_TICK;
}
if (idx >= 0) {
env->exception_index = idx;
cpu->exception_index = idx;
cc->do_interrupt(cpu);
next_tb = 0;
}
......@@ -468,7 +468,7 @@ int cpu_exec(CPUArchState *env)
if (((type == TT_EXTINT) &&
cpu_pil_allowed(env, pil)) ||
type != TT_EXTINT) {
env->exception_index = env->interrupt_index;
cpu->exception_index = env->interrupt_index;
cc->do_interrupt(cpu);
next_tb = 0;
}
......@@ -477,7 +477,7 @@ int cpu_exec(CPUArchState *env)
#elif defined(TARGET_ARM)
if (interrupt_request & CPU_INTERRUPT_FIQ
&& !(env->daif & PSTATE_F)) {
env->exception_index = EXCP_FIQ;
cpu->exception_index = EXCP_FIQ;
cc->do_interrupt(cpu);
next_tb = 0;
}
......@@ -493,14 +493,14 @@ int cpu_exec(CPUArchState *env)
if (interrupt_request & CPU_INTERRUPT_HARD
&& ((IS_M(env) && env->regs[15] < 0xfffffff0)
|| !(env->daif & PSTATE_I))) {
env->exception_index = EXCP_IRQ;
cpu->exception_index = EXCP_IRQ;
cc->do_interrupt(cpu);
next_tb = 0;
}
#elif defined(TARGET_UNICORE32)
if (interrupt_request & CPU_INTERRUPT_HARD
&& !(env->uncached_asr & ASR_I)) {
env->exception_index = UC32_EXCP_INTR;
cpu->exception_index = UC32_EXCP_INTR;
cc->do_interrupt(cpu);
next_tb = 0;
}
......@@ -535,7 +535,7 @@ int cpu_exec(CPUArchState *env)
}
}
if (idx >= 0) {
env->exception_index = idx;
cpu->exception_index = idx;
env->error_code = 0;
cc->do_interrupt(cpu);
next_tb = 0;
......@@ -545,7 +545,7 @@ int cpu_exec(CPUArchState *env)
if (interrupt_request & CPU_INTERRUPT_HARD
&& (env->pregs[PR_CCS] & I_FLAG)
&& !env->locked_irq) {
env->exception_index = EXCP_IRQ;
cpu->exception_index = EXCP_IRQ;
cc->do_interrupt(cpu);
next_tb = 0;
}
......@@ -557,7 +557,7 @@ int cpu_exec(CPUArchState *env)
m_flag_archval = M_FLAG_V32;
}
if ((env->pregs[PR_CCS] & m_flag_archval)) {
env->exception_index = EXCP_NMI;
cpu->exception_index = EXCP_NMI;
cc->do_interrupt(cpu);
next_tb = 0;
}
......@@ -571,7 +571,7 @@ int cpu_exec(CPUArchState *env)
hardware doesn't rely on this, so we
provide/save the vector when the interrupt is
first signalled. */
env->exception_index = env->pending_vector;
cpu->exception_index = env->pending_vector;
do_interrupt_m68k_hardirq(env);
next_tb = 0;
}
......@@ -583,7 +583,7 @@ int cpu_exec(CPUArchState *env)
}
#elif defined(TARGET_XTENSA)
if (interrupt_request & CPU_INTERRUPT_HARD) {
env->exception_index = EXC_IRQ;
cpu->exception_index = EXC_IRQ;
cc->do_interrupt(cpu);
next_tb = 0;
}
......@@ -599,7 +599,7 @@ int cpu_exec(CPUArchState *env)
}
if (unlikely(cpu->exit_request)) {
cpu->exit_request = 0;
env->exception_index = EXCP_INTERRUPT;
cpu->exception_index = EXCP_INTERRUPT;
cpu_loop_exit(env);
}
spin_lock(&tcg_ctx.tb_ctx.tb_lock);
......@@ -669,7 +669,7 @@ int cpu_exec(CPUArchState *env)
/* Execute remaining instructions. */
cpu_exec_nocache(env, insns_left, tb);
}
env->exception_index = EXCP_INTERRUPT;
cpu->exception_index = EXCP_INTERRUPT;
next_tb = 0;
cpu_loop_exit(env);
}
......
......@@ -1595,7 +1595,7 @@ static void check_watchpoint(int offset, int len_mask, int flags)
env->watchpoint_hit = wp;
tb_check_watchpoint(env);
if (wp->flags & BP_STOP_BEFORE_ACCESS) {
env->exception_index = EXCP_DEBUG;
cpu->exception_index = EXCP_DEBUG;
cpu_loop_exit(env);
} else {
cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
......
......@@ -472,14 +472,13 @@ static void ppce500_cpu_reset_sec(void *opaque)
{
PowerPCCPU *cpu = opaque;
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
cpu_reset(cs);
/* Secondary CPU starts in halted state for now. Needs to change when
implementing non-kernel boot. */
cs->halted = 1;
env->exception_index = EXCP_HLT;
cs->exception_index = EXCP_HLT;
}
static void ppce500_cpu_reset(void *opaque)
......
......@@ -117,7 +117,7 @@ static void spin_kick(void *data)
mmubooke_create_initial_mapping(env, 0, map_start, map_size);
cpu->halted = 0;
env->exception_index = -1;
cpu->exception_index = -1;
cpu->stopped = false;
qemu_cpu_kick(cpu);
}
......
......@@ -529,7 +529,7 @@ static target_ulong h_cede(PowerPCCPU *cpu, sPAPREnvironment *spapr,
hreg_compute_hflags(env);
if (!cpu_has_work(cs)) {
cs->halted = 1;
env->exception_index = EXCP_HLT;
cs->exception_index = EXCP_HLT;
cs->exit_request = 1;
}
return H_SUCCESS;
......
......@@ -135,25 +135,23 @@ static unsigned s390_running_cpus;
void s390_add_running_cpu(S390CPU *cpu)
{
CPUState *cs = CPU(cpu);
CPUS390XState *env = &cpu->env;
if (cs->halted) {
s390_running_cpus++;
cs->halted = 0;
env->exception_index = -1;
cs->exception_index = -1;
}
}
unsigned s390_del_running_cpu(S390CPU *cpu)
{
CPUState *cs = CPU(cpu);
CPUS390XState *env = &cpu->env;
if (cs->halted == 0) {
assert(s390_running_cpus >= 1);
s390_running_cpus--;
cs->halted = 1;
env->exception_index = EXCP_HLT;
cs->exception_index = EXCP_HLT;
}
return s390_running_cpus;
}
......@@ -196,7 +194,7 @@ void s390_init_cpus(const char *cpu_model, uint8_t *storage_keys)
ipi_states[i] = cpu;
cs->halted = 1;
cpu->env.exception_index = EXCP_HLT;
cs->exception_index = EXCP_HLT;
cpu->env.storage_keys = storage_keys;
}
}
......
......@@ -139,9 +139,6 @@ typedef struct CPUWatchpoint {
QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
CPUWatchpoint *watchpoint_hit; \
\
/* Core interrupt code */ \
int exception_index; \
\
/* user data */ \
void *opaque; \
......
......@@ -249,6 +249,7 @@ struct CPUState {
icount_decr_u16 u16;
} icount_decr;
uint32_t can_do_io;
int32_t exception_index; /* used by m68k TCG */
};
QTAILQ_HEAD(CPUTailQ, CPUState);
......
......@@ -774,8 +774,9 @@ static int
setup_sigcontext(struct target_sigcontext *sc, struct target_fpstate *fpstate,
CPUX86State *env, abi_ulong mask, abi_ulong fpstate_addr)
{
int err = 0;
uint16_t magic;
CPUState *cs = CPU(x86_env_get_cpu(env));
int err = 0;
uint16_t magic;
/* already locked in setup_frame() */
err |= __put_user(env->segs[R_GS].selector, (unsigned int *)&sc->gs);
......@@ -790,7 +791,7 @@ setup_sigcontext(struct target_sigcontext *sc, struct target_fpstate *fpstate,
err |= __put_user(env->regs[R_EDX], &sc->edx);
err |= __put_user(env->regs[R_ECX], &sc->ecx);
err |= __put_user(env->regs[R_EAX], &sc->eax);
err |= __put_user(env->exception_index, &sc->trapno);
err |= __put_user(cs->exception_index, &sc->trapno);
err |= __put_user(env->error_code, &sc->err);
err |= __put_user(env->eip, &sc->eip);
err |= __put_user(env->segs[R_CS].selector, (unsigned int *)&sc->cs);
......
......@@ -173,7 +173,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
{
AlphaCPU *cpu = ALPHA_CPU(cs);
cpu->env.exception_index = EXCP_MMFAULT;
cs->exception_index = EXCP_MMFAULT;
cpu->env.trap_arg0 = address;
return 1;
}
......@@ -338,7 +338,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int rw,
fail = get_physical_address(env, addr, 1 << rw, mmu_idx, &phys, &prot);
if (unlikely(fail >= 0)) {
env->exception_index = EXCP_MMFAULT;
cs->exception_index = EXCP_MMFAULT;
env->trap_arg0 = addr;
env->trap_arg1 = fail;
env->trap_arg2 = (rw == 2 ? -1 : rw);
......@@ -355,7 +355,7 @@ void alpha_cpu_do_interrupt(CPUState *cs)
{
AlphaCPU *cpu = ALPHA_CPU(cs);
CPUAlphaState *env = &cpu->env;
int i = env->exception_index;
int i = cs->exception_index;
if (qemu_loglevel_mask(CPU_LOG_INT)) {
static int count;
......@@ -406,7 +406,7 @@ void alpha_cpu_do_interrupt(CPUState *cs)
++count, name, env->error_code, env->pc, env->ir[IR_SP]);
}
env->exception_index = -1;
cs->exception_index = -1;
#if !defined(CONFIG_USER_ONLY)
switch (i) {
......@@ -508,7 +508,10 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
We expect that ENV->PC has already been updated. */
void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error)
{
env->exception_index = excp;
AlphaCPU *cpu = alpha_env_get_cpu(env);
CPUState *cs = CPU(cpu);
cs->exception_index = excp;
env->error_code = error;
cpu_loop_exit(env);
}
......@@ -517,7 +520,10 @@ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error)
void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr,
int excp, int error)
{
env->exception_index = excp;
AlphaCPU *cpu = alpha_env_get_cpu(env);
CPUState *cs = CPU(cpu);
cs->exception_index = excp;
env->error_code = error;
if (retaddr) {
cpu_restore_state(env, retaddr);
......
......@@ -99,6 +99,8 @@ uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
static void do_unaligned_access(CPUAlphaState *env, target_ulong addr,
int is_write, int is_user, uintptr_t retaddr)
{
AlphaCPU *cpu = alpha_env_get_cpu(env);
CPUState *cs = CPU(cpu);
uint64_t pc;
uint32_t insn;
......@@ -112,7 +114,7 @@ static void do_unaligned_access(CPUAlphaState *env, target_ulong addr,
env->trap_arg0 = addr;
env->trap_arg1 = insn >> 26; /* opcode */
env->trap_arg2 = (insn >> 21) & 31; /* dest regno */
env->exception_index = EXCP_UNALIGN;
cs->exception_index = EXCP_UNALIGN;
env->error_code = 0;
cpu_loop_exit(env);
}
......
......@@ -2649,10 +2649,7 @@ uint32_t HELPER(rbit)(uint32_t x)
void arm_cpu_do_interrupt(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
env->exception_index = -1;
cs->exception_index = -1;
}
int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
......@@ -2662,10 +2659,10 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
CPUARMState *env = &cpu->env;
if (rw == 2) {
env->exception_index = EXCP_PREFETCH_ABORT;
cs->exception_index = EXCP_PREFETCH_ABORT;
env->cp15.c6_insn = address;
} else {
env->exception_index = EXCP_DATA_ABORT;
cs->exception_index = EXCP_DATA_ABORT;
env->cp15.c6_data = address;
}
return 1;
......@@ -2851,7 +2848,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
uint32_t lr;
uint32_t addr;
arm_log_exception(env->exception_index);
arm_log_exception(cs->exception_index);
lr = 0xfffffff1;
if (env->v7m.current_sp)
......@@ -2863,7 +2860,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
handle it. */
/* TODO: Need to escalate if the current priority is higher than the
one we're raising. */
switch (env->exception_index) {
switch (cs->exception_index) {
case EXCP_UDEF:
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
return;
......@@ -2895,7 +2892,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
do_v7m_exception_exit(env);
return;
default:
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
return; /* Never happens. Keep compiler happy. */
}
......@@ -2936,10 +2933,10 @@ void arm_cpu_do_interrupt(CPUState *cs)
assert(!IS_M(env));
arm_log_exception(env->exception_index);
arm_log_exception(cs->exception_index);
/* TODO: Vectored interrupt controller. */
switch (env->exception_index) {
switch (cs->exception_index) {
case EXCP_UDEF:
new_mode = ARM_CPU_MODE_UND;
addr = 0x04;
......@@ -3020,7 +3017,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
offset = 4;
break;
default:
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
return; /* Never happens. Keep compiler happy. */
}
/* High vectors. */
......@@ -3650,13 +3647,13 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
if (access_type == 2) {
env->cp15.c5_insn = ret;
env->cp15.c6_insn = address;
env->exception_index = EXCP_PREFETCH_ABORT;
cs->exception_index = EXCP_PREFETCH_ABORT;
} else {
env->cp15.c5_data = ret;
if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
env->cp15.c5_data |= (1 << 11);
env->cp15.c6_data = address;
env->exception_index = EXCP_DATA_ABORT;
cs->exception_index = EXCP_DATA_ABORT;
}
return 1;
}
......
......@@ -24,7 +24,10 @@
static void raise_exception(CPUARMState *env, int tt)
{
env->exception_index = tt;
ARMCPU *cpu = arm_env_get_cpu(env);
CPUState *cs = CPU(cpu);
cs->exception_index = tt;
cpu_loop_exit(env);
}
......@@ -75,15 +78,16 @@ void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
ARMCPU *cpu = arm_env_get_cpu(env);
CPUState *cs = CPU(cpu);
int ret;
ret = arm_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
ret = arm_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
}
raise_exception(env, env->exception_index);
raise_exception(env, cs->exception_index);
}
}
#endif
......@@ -221,23 +225,27 @@ void HELPER(wfi)(CPUARMState *env)
{
CPUState *cs = CPU(arm_env_get_cpu(env));
env->exception_index = EXCP_HLT;
cs->exception_index = EXCP_HLT;
cs->halted = 1;
cpu_loop_exit(env);
}
void HELPER(wfe)(CPUARMState *env)
{
CPUState *cs = CPU(arm_env_get_cpu(env));
/* Don't actually halt the CPU, just yield back to top
* level loop
*/
env->exception_index = EXCP_YIELD;
cs->exception_index = EXCP_YIELD;
cpu_loop_exit(env);
}
void HELPER(exception)(CPUARMState *env, uint32_t excp)
{
env->exception_index = excp;
CPUState *cs = CPU(arm_env_get_cpu(env));
cs->exception_index = excp;
cpu_loop_exit(env);
}
......
......@@ -41,7 +41,7 @@ void cris_cpu_do_interrupt(CPUState *cs)
CRISCPU *cpu = CRIS_CPU(cs);
CPUCRISState *env = &cpu->env;
env->exception_index = -1;
cs->exception_index = -1;
env->pregs[PR_ERP] = env->pc;
}
......@@ -55,7 +55,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
{
CRISCPU *cpu = CRIS_CPU(cs);
cpu->env.exception_index = 0xaa;
cs->exception_index = 0xaa;
cpu->env.pregs[PR_EDA] = address;
cpu_dump_state(cs, stderr, fprintf, 0);
return 1;
......@@ -88,7 +88,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
rw, mmu_idx, 0);
if (miss) {
if (env->exception_index == EXCP_BUSFAULT) {
if (cs->exception_index == EXCP_BUSFAULT) {
cpu_abort(env,
"CRIS: Illegal recursive bus fault."
"addr=%" VADDR_PRIx " rw=%d\n",
......@@ -96,7 +96,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
}
env->pregs[PR_EDA] = address;
env->exception_index = EXCP_BUSFAULT;
cs->exception_index = EXCP_BUSFAULT;
env->fault_vector = res.bf_vec;
r = 1;
} else {
......@@ -125,7 +125,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs)
int ex_vec = -1;
D_LOG("exception index=%d interrupt_req=%d\n",
env->exception_index,
cs->exception_index,
cs->interrupt_request);
if (env->dslot) {
......@@ -134,7 +134,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs)
}
assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
switch (env->exception_index) {
switch (cs->exception_index) {
case EXCP_BREAK:
/* These exceptions are genereated by the core itself.
ERP should point to the insn following the brk. */
......@@ -187,10 +187,10 @@ void cris_cpu_do_interrupt(CPUState *cs)
int ex_vec = -1;
D_LOG("exception index=%d interrupt_req=%d\n",
env->exception_index,
cs->exception_index,
cs->interrupt_request);
switch (env->exception_index) {
switch (cs->exception_index) {
case EXCP_BREAK:
/* These exceptions are genereated by the core itself.
ERP should point to the insn following the brk. */
......@@ -253,7 +253,7 @@ void cris_cpu_do_interrupt(CPUState *cs)
/* Clear the excption_index to avoid spurios hw_aborts for recursive
bus faults. */
env->exception_index = -1;
cs->exception_index = -1;
D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
__func__, env->pc, ex_vec,
......
......@@ -79,8 +79,10 @@ void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx,
void helper_raise_exception(CPUCRISState *env, uint32_t index)
{
env->exception_index = index;
cpu_loop_exit(env);
CPUState *cs = CPU(cris_env_get_cpu(env));
cs->exception_index = index;
cpu_loop_exit(env);
}
void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
......
......@@ -94,6 +94,8 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno,
int is_int, int error_code,
int next_eip_addend)
{
CPUState *cs = CPU(x86_env_get_cpu(env));
if (!is_int) {
cpu_svm_check_intercept_param(env, SVM_EXIT_EXCP_BASE + intno,
error_code);
......@@ -102,7 +104,7 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno,
cpu_svm_check_intercept_param(env, SVM_EXIT_SWINT, 0);
}
env->exception_index = intno;
cs->exception_index = intno;
env->error_code = error_code;
env->exception_is_int = is_int;
env->exception_next_eip = env->eip + next_eip_addend;
......
......@@ -496,7 +496,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
env->cr[2] = addr;
env->error_code = (is_write << PG_ERROR_W_BIT);
env->error_code |= PG_ERROR_U_MASK;
env->exception_index = EXCP0E_PAGE;
cs->exception_index = EXCP0E_PAGE;
return 1;
}
......@@ -561,7 +561,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
sext = (int64_t)addr >> 47;
if (sext != 0 && sext != -1) {
env->error_code = 0;
env->exception_index = EXCP0D_GPF;
cs->exception_index = EXCP0D_GPF;
return 1;
}
......@@ -892,7 +892,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
env->cr[2] = addr;
}
env->error_code = error_code;
env->exception_index = EXCP0E_PAGE;
cs->exception_index = EXCP0E_PAGE;
return 1;
}
......
......@@ -136,15 +136,16 @@ void tlb_fill(CPUX86State *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
X86CPU *cpu = x86_env_get_cpu(env);
CPUState *cs = CPU(cpu);
int ret;
ret = x86_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
ret = x86_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (ret) {
if (retaddr) {
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
}
raise_exception_err(env, env->exception_index, env->error_code);
raise_exception_err(env, cs->exception_index, env->error_code);
}
}
#endif
......@@ -568,10 +568,11 @@ void helper_rdmsr(CPUX86State *env)
static void do_pause(X86CPU *cpu)
{
CPUState *cs = CPU(cpu);
CPUX86State *env = &cpu->env;
/* Just let another CPU run. */
env->exception_index = EXCP_INTERRUPT;
cs->exception_index = EXCP_INTERRUPT;
cpu_loop_exit(env);
}
......@@ -582,7 +583,7 @@ static void do_hlt(X86CPU *cpu)
env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
cs->halted = 1;
env->exception_index = EXCP_HLT;
cs->exception_index = EXCP_HLT;
cpu_loop_exit(env);
}
......@@ -638,6 +639,8 @@ void helper_pause(CPUX86State *env, int next_eip_addend)
void helper_debug(CPUX86State *env)
{
env->exception_index = EXCP_DEBUG;