Commit 1a855029 authored by Aurelien Jarno's avatar Aurelien Jarno
Browse files

target-arm: fix bug in translation of REVSH



The translation of REVSH shifted the low byte 8 steps left before performing
an 8-bit sign extend, causing this part of the expression to alwas be 0.
Reported-by: default avatarJohan Bengtsson <teofrastius@gmail.com>
Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
parent 5697f6ae
......@@ -250,13 +250,9 @@ static void gen_rev16(TCGv var)
/* Byteswap low halfword and sign extend. */
static void gen_revsh(TCGv var)
{
TCGv tmp = new_tmp();
tcg_gen_shri_i32(tmp, var, 8);
tcg_gen_andi_i32(tmp, tmp, 0x00ff);
tcg_gen_shli_i32(var, var, 8);
tcg_gen_ext8s_i32(var, var);
tcg_gen_or_i32(var, var, tmp);
dead_tmp(tmp);
tcg_gen_ext16u_i32(var, var);
tcg_gen_bswap16_i32(var, var);
tcg_gen_ext16s_i32(var, var);
}
/* Unsigned bitfield extract. */
......
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