Commit 0dbcf95a authored by Michael Tokarev's avatar Michael Tokarev Committed by Peter Maydell

libvixl: fix 64bit constants usage

Since commit 999b53ec:
 Author: Claudio Fontana <claudio.fontana@linaro.org>
 Date:   Wed Feb 5 17:27:28 2014 +0000

    disas: Implement disassembly output for A64

    Use libvixl to implement disassembly output in debug
    logs for A64, for use with both AArch64 hosts and targets.

disas/libvixl/ contains functions which uses 64bit constants
without using appropriate suffixes, which fails on 32bits.

Fix this by using ULL suffix.
Signed-off-by: default avatarMichael Tokarev <mjt@tls.msk.ru>
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 078a1c37
......@@ -269,19 +269,19 @@ bool Disassembler::IsMovzMovnImm(unsigned reg_size, uint64_t value) {
((reg_size == kWRegSize) && (value <= 0xffffffff)));
// Test for movz: 16 bits set at positions 0, 16, 32 or 48.
if (((value & 0xffffffffffff0000UL) == 0UL) ||
((value & 0xffffffff0000ffffUL) == 0UL) ||
((value & 0xffff0000ffffffffUL) == 0UL) ||
((value & 0x0000ffffffffffffUL) == 0UL)) {
if (((value & 0xffffffffffff0000ULL) == 0ULL) ||
((value & 0xffffffff0000ffffULL) == 0ULL) ||
((value & 0xffff0000ffffffffULL) == 0ULL) ||
((value & 0x0000ffffffffffffULL) == 0ULL)) {
return true;
}
// Test for movn: NOT(16 bits set at positions 0, 16, 32 or 48).
if ((reg_size == kXRegSize) &&
(((value & 0xffffffffffff0000UL) == 0xffffffffffff0000UL) ||
((value & 0xffffffff0000ffffUL) == 0xffffffff0000ffffUL) ||
((value & 0xffff0000ffffffffUL) == 0xffff0000ffffffffUL) ||
((value & 0x0000ffffffffffffUL) == 0x0000ffffffffffffUL))) {
(((value & 0xffffffffffff0000ULL) == 0xffffffffffff0000ULL) ||
((value & 0xffffffff0000ffffULL) == 0xffffffff0000ffffULL) ||
((value & 0xffff0000ffffffffULL) == 0xffff0000ffffffffULL) ||
((value & 0x0000ffffffffffffULL) == 0x0000ffffffffffffULL))) {
return true;
}
if ((reg_size == kWRegSize) &&
......
......@@ -95,7 +95,7 @@ int CountSetBits(uint64_t value, int width) {
ASSERT((width == 32) || (width == 64));
// Mask out unused bits to ensure that they are not counted.
value &= (0xffffffffffffffffUL >> (64-width));
value &= (0xffffffffffffffffULL >> (64-width));
// Add up the set bits.
// The algorithm works by adding pairs of bit fields together iteratively,
......@@ -108,12 +108,18 @@ int CountSetBits(uint64_t value, int width) {
// value = h+g+f+e d+c+b+a
// \ |
// value = h+g+f+e+d+c+b+a
value = ((value >> 1) & 0x5555555555555555) + (value & 0x5555555555555555);
value = ((value >> 2) & 0x3333333333333333) + (value & 0x3333333333333333);
value = ((value >> 4) & 0x0f0f0f0f0f0f0f0f) + (value & 0x0f0f0f0f0f0f0f0f);
value = ((value >> 8) & 0x00ff00ff00ff00ff) + (value & 0x00ff00ff00ff00ff);
value = ((value >> 16) & 0x0000ffff0000ffff) + (value & 0x0000ffff0000ffff);
value = ((value >> 32) & 0x00000000ffffffff) + (value & 0x00000000ffffffff);
value = ((value >> 1) & 0x5555555555555555ULL) +
(value & 0x5555555555555555ULL);
value = ((value >> 2) & 0x3333333333333333ULL) +
(value & 0x3333333333333333ULL);
value = ((value >> 4) & 0x0f0f0f0f0f0f0f0fULL) +
(value & 0x0f0f0f0f0f0f0f0fULL);
value = ((value >> 8) & 0x00ff00ff00ff00ffULL) +
(value & 0x00ff00ff00ff00ffULL);
value = ((value >> 16) & 0x0000ffff0000ffffULL) +
(value & 0x0000ffff0000ffffULL);
value = ((value >> 32) & 0x00000000ffffffffULL) +
(value & 0x00000000ffffffffULL);
return value;
}
......
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