Commit 0bacd130 authored by aliguori's avatar aliguori

Handle suspend in qemu (Gleb Natapov)

Reset a PC and tell BIOS that resume from ram is required on the next boot.
Signed-off-by: default avatarGleb Natapov <gleb@redhat.com>
Signed-off-by: default avatarAnthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6080 c046a42c-6fe2-441c-8c8c-71466251a162
parent 6f484e73
......@@ -53,6 +53,8 @@ typedef struct PIIX4PMState {
qemu_irq irq;
} PIIX4PMState;
#define RSM_STS (1 << 15)
#define PWRBTN_STS (1 << 8)
#define RTC_EN (1 << 10)
#define PWRBTN_EN (1 << 8)
#define GBL_EN (1 << 5)
......@@ -151,6 +153,14 @@ static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
case 0: /* soft power off */
qemu_system_shutdown_request();
break;
case 1:
/* RSM_STS should be set on resume. Pretend that resume
was caused by power button */
s->pmsts |= (RSM_STS | PWRBTN_STS);
qemu_system_reset_request();
#if defined(TARGET_I386)
cmos_set_s3_resume();
#endif
default:
break;
}
......@@ -471,6 +481,17 @@ static int pm_load(QEMUFile* f,void* opaque,int version_id)
return 0;
}
static void piix4_reset(void *opaque)
{
PIIX4PMState *s = opaque;
uint8_t *pci_conf = s->dev.config;
pci_conf[0x58] = 0;
pci_conf[0x59] = 0;
pci_conf[0x5a] = 0;
pci_conf[0x5b] = 0;
}
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq)
{
......@@ -527,6 +548,8 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
s->smbus = i2c_init_bus();
s->irq = sci_irq;
qemu_register_reset(piix4_reset, s);
return s->smbus;
}
......
......@@ -1135,6 +1135,14 @@ static void pc_init_isa(ram_addr_t ram_size, int vga_ram_size,
initrd_filename, 0, cpu_model);
}
/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
BIOS will read it and start S3 resume at POST Entry */
void cmos_set_s3_resume(void)
{
if (rtc_state)
rtc_set_memory(rtc_state, 0xF, 0xFE);
}
QEMUMachine pc_machine = {
.name = "pc",
.desc = "Standard PC",
......
......@@ -82,6 +82,7 @@ RTCState *rtc_init(int base, qemu_irq irq);
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
void rtc_set_memory(RTCState *s, int addr, int val);
void rtc_set_date(RTCState *s, const struct tm *tm);
void cmos_set_s3_resume(void);
/* pc.c */
extern int fd_bootchk;
......
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