Commit 05ed9a99 authored by Peter Maydell's avatar Peter Maydell Committed by Aurelien Jarno
Browse files

target-arm: Set privileged bit in TB flags correctly for M profile



M profile ARM cores don't have a CPSR mode field. Set the bit in the
TB flags that indicates non-user mode correctly for these cores.
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
parent 98eac7ca
......@@ -485,13 +485,19 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
int privmode;
*pc = env->regs[15];
*cs_base = 0;
*flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
| (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
| (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
| (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT);
if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
if (arm_feature(env, ARM_FEATURE_M)) {
privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
} else {
privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
}
if (privmode) {
*flags |= ARM_TBFLAG_PRIV_MASK;
}
if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
......
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