Commit 05168674 authored by Richard Henderson's avatar Richard Henderson Committed by Aurelien Jarno
Browse files

target-mips: Streamline indexed cp1 memory addressing.



We've already eliminated both base and index being zero.
Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
parent 13d24f49
......@@ -7742,8 +7742,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
} else if (index == 0) {
gen_load_gpr(t0, base);
} else {
gen_load_gpr(t0, index);
gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
}
/* Don't do NOP if destination is zero: we must perform the actual
memory access. */
......
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