• Paolo Bonzini's avatar
    apic: fix loss of IPI due to masked ExtINT · 8092cb71
    Paolo Bonzini authored
    
    
    This patch fixes an obscure failure of the QNX kernel on QEMU x86 SMP.
    In QNX, all hardware interrupts come via the PIC, and are delivered by
    the cpu 0 LAPIC in ExtINT mode, while IPIs are delivered by the LAPIC
    in fixed mode.
    
    This bug happens as follows:
    - cpu 0 masks a particular PIC interrupt
    - IPI sent to cpu 0 (CPU_INTERRUPT_HARD is set)
    - before the IPI is accepted, the masked interrupt line is asserted by the
    device
    
    Since the interrupt is masked, apic_deliver_pic_intr will clear
    CPU_INTERRUPT_HARD. The IPI will still be set in the APIC irr, but since
    CPU_INTERRUPT_HARD is not set the cpu will not notice. Depending on the
    scenario this can cause a system hang, i.e. if cpu 0 is expected to unmask
    the interrupt.
    
    In order to fix this, do a full check of the APIC before an EXTINT
    is acknowledged.  This can result in clearing CPU_INTERRUPT_HARD, but
    can also result in delivering the lost IPI.
    Reported-by: default avatarRichard Bilson <rbilson@qnx.com>
    Tested-by: default avatarRichard Bilson <rbilson@qnx.com>
    Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
    8092cb71