pci.c 41.3 KB
Newer Older
bellard's avatar
bellard committed
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
/*
 * QEMU PCI bus manager
 *
 * Copyright (c) 2004 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

//#define DEBUG_PCI

28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
#define PCI_VENDOR_ID		0x00	/* 16 bits */
#define PCI_DEVICE_ID		0x02	/* 16 bits */
#define PCI_COMMAND		0x04	/* 16 bits */
#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
#define PCI_MIN_GNT		0x3e	/* 8 bits */
#define PCI_MAX_LAT		0x3f	/* 8 bits */

/* just used for simpler irq handling. */
#define PCI_DEVICES_MAX 64
#define PCI_IRQ_WORDS   ((PCI_DEVICES_MAX + 31) / 32)

43
44
45
46
47
48
49
50
struct PCIBus {
    int bus_num;
    int devfn_min;
    void (*set_irq)(PCIDevice *pci_dev, int irq_num, int level);
    uint32_t config_reg; /* XXX: suppress */
    openpic_t *openpic; /* XXX: suppress */
    PCIDevice *devices[256];
};
bellard's avatar
bellard committed
51
52

target_phys_addr_t pci_mem_base;
53
54
static int pci_irq_index;
static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS];
55
56
57
58
59
60
61
62
63
static PCIBus *first_bus;

static PCIBus *pci_register_bus(void)
{
    PCIBus *bus;
    bus = qemu_mallocz(sizeof(PCIBus));
    first_bus = bus;
    return bus;
}
bellard's avatar
bellard committed
64
65

/* -1 for devfn means auto assign */
66
67
PCIDevice *pci_register_device(PCIBus *bus, const char *name, 
                               int instance_size, int devfn,
bellard's avatar
bellard committed
68
69
70
                               PCIConfigReadFunc *config_read, 
                               PCIConfigWriteFunc *config_write)
{
71
    PCIDevice *pci_dev;
bellard's avatar
bellard committed
72

73
74
75
    if (pci_irq_index >= PCI_DEVICES_MAX)
        return NULL;
    
bellard's avatar
bellard committed
76
    if (devfn < 0) {
77
78
        for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
            if (!bus->devices[devfn])
bellard's avatar
bellard committed
79
80
81
82
83
84
85
86
                goto found;
        }
        return NULL;
    found: ;
    }
    pci_dev = qemu_mallocz(instance_size);
    if (!pci_dev)
        return NULL;
87
    pci_dev->bus = bus;
bellard's avatar
bellard committed
88
89
    pci_dev->devfn = devfn;
    pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
90
91
92
93
94

    if (!config_read)
        config_read = pci_default_read_config;
    if (!config_write)
        config_write = pci_default_write_config;
bellard's avatar
bellard committed
95
96
    pci_dev->config_read = config_read;
    pci_dev->config_write = config_write;
97
    pci_dev->irq_index = pci_irq_index++;
98
    bus->devices[devfn] = pci_dev;
bellard's avatar
bellard committed
99
100
101
102
103
104
105
106
107
    return pci_dev;
}

void pci_register_io_region(PCIDevice *pci_dev, int region_num, 
                            uint32_t size, int type, 
                            PCIMapIORegionFunc *map_func)
{
    PCIIORegion *r;

108
    if ((unsigned int)region_num >= PCI_NUM_REGIONS)
bellard's avatar
bellard committed
109
110
111
112
113
114
115
116
        return;
    r = &pci_dev->io_regions[region_num];
    r->addr = -1;
    r->size = size;
    r->type = type;
    r->map_func = map_func;
}

117
static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val)
bellard's avatar
bellard committed
118
{
119
    PCIBus *s = opaque;
bellard's avatar
bellard committed
120
121
122
    s->config_reg = val;
}

123
static uint32_t pci_addr_readl(void* opaque, uint32_t addr)
bellard's avatar
bellard committed
124
{
125
    PCIBus *s = opaque;
bellard's avatar
bellard committed
126
127
128
    return s->config_reg;
}

129
130
131
132
static void pci_update_mappings(PCIDevice *d)
{
    PCIIORegion *r;
    int cmd, i;
133
    uint32_t last_addr, new_addr, config_ofs;
134
135
    
    cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
136
    for(i = 0; i < PCI_NUM_REGIONS; i++) {
137
        r = &d->io_regions[i];
138
139
140
141
142
        if (i == PCI_ROM_SLOT) {
            config_ofs = 0x30;
        } else {
            config_ofs = 0x10 + i * 4;
        }
143
144
145
146
        if (r->size != 0) {
            if (r->type & PCI_ADDRESS_SPACE_IO) {
                if (cmd & PCI_COMMAND_IO) {
                    new_addr = le32_to_cpu(*(uint32_t *)(d->config + 
147
                                                         config_ofs));
148
149
150
151
152
153
154
155
156
157
158
159
160
                    new_addr = new_addr & ~(r->size - 1);
                    last_addr = new_addr + r->size - 1;
                    /* NOTE: we have only 64K ioports on PC */
                    if (last_addr <= new_addr || new_addr == 0 ||
                        last_addr >= 0x10000) {
                        new_addr = -1;
                    }
                } else {
                    new_addr = -1;
                }
            } else {
                if (cmd & PCI_COMMAND_MEMORY) {
                    new_addr = le32_to_cpu(*(uint32_t *)(d->config + 
161
162
163
164
                                                         config_ofs));
                    /* the ROM slot has a specific enable bit */
                    if (i == PCI_ROM_SLOT && !(new_addr & 1))
                        goto no_mem_map;
165
166
167
168
169
170
171
172
173
174
175
                    new_addr = new_addr & ~(r->size - 1);
                    last_addr = new_addr + r->size - 1;
                    /* NOTE: we do not support wrapping */
                    /* XXX: as we cannot support really dynamic
                       mappings, we handle specific values as invalid
                       mappings. */
                    if (last_addr <= new_addr || new_addr == 0 ||
                        last_addr == -1) {
                        new_addr = -1;
                    }
                } else {
176
                no_mem_map:
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
                    new_addr = -1;
                }
            }
            /* now do the real mapping */
            if (new_addr != r->addr) {
                if (r->addr != -1) {
                    if (r->type & PCI_ADDRESS_SPACE_IO) {
                        int class;
                        /* NOTE: specific hack for IDE in PC case:
                           only one byte must be mapped. */
                        class = d->config[0x0a] | (d->config[0x0b] << 8);
                        if (class == 0x0101 && r->size == 4) {
                            isa_unassign_ioport(r->addr + 2, 1);
                        } else {
                            isa_unassign_ioport(r->addr, r->size);
                        }
                    } else {
                        cpu_register_physical_memory(r->addr + pci_mem_base, 
                                                     r->size, 
                                                     IO_MEM_UNASSIGNED);
                    }
                }
                r->addr = new_addr;
                if (r->addr != -1) {
                    r->map_func(d, i, r->addr, r->size, r->type);
                }
            }
        }
    }
}

uint32_t pci_default_read_config(PCIDevice *d, 
                                 uint32_t address, int len)
bellard's avatar
bellard committed
210
{
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
    uint32_t val;
    switch(len) {
    case 1:
        val = d->config[address];
        break;
    case 2:
        val = le16_to_cpu(*(uint16_t *)(d->config + address));
        break;
    default:
    case 4:
        val = le32_to_cpu(*(uint32_t *)(d->config + address));
        break;
    }
    return val;
}

void pci_default_write_config(PCIDevice *d, 
                              uint32_t address, uint32_t val, int len)
{
    int can_write, i;
bellard's avatar
bellard committed
231
    uint32_t end, addr;
232

233
234
    if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) || 
                     (address >= 0x30 && address < 0x34))) {
235
236
237
        PCIIORegion *r;
        int reg;

238
239
240
241
242
        if ( address >= 0x30 ) {
            reg = PCI_ROM_SLOT;
        }else{
            reg = (address - 0x10) >> 2;
        }
243
244
245
246
        r = &d->io_regions[reg];
        if (r->size == 0)
            goto default_config;
        /* compute the stored value */
247
248
249
250
251
252
253
254
        if (reg == PCI_ROM_SLOT) {
            /* keep ROM enable bit */
            val &= (~(r->size - 1)) | 1;
        } else {
            val &= ~(r->size - 1);
            val |= r->type;
        }
        *(uint32_t *)(d->config + address) = cpu_to_le32(val);
255
        pci_update_mappings(d);
bellard's avatar
bellard committed
256
        return;
257
258
259
    }
 default_config:
    /* not efficient, but simple */
bellard's avatar
bellard committed
260
    addr = address;
261
262
    for(i = 0; i < len; i++) {
        /* default read/write accesses */
263
        switch(d->config[0x0e]) {
264
        case 0x00:
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
        case 0x80:
            switch(addr) {
            case 0x00:
            case 0x01:
            case 0x02:
            case 0x03:
            case 0x08:
            case 0x09:
            case 0x0a:
            case 0x0b:
            case 0x0e:
            case 0x10 ... 0x27: /* base */
            case 0x30 ... 0x33: /* rom */
            case 0x3d:
                can_write = 0;
                break;
            default:
                can_write = 1;
                break;
            }
285
286
            break;
        default:
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
        case 0x01:
            switch(addr) {
            case 0x00:
            case 0x01:
            case 0x02:
            case 0x03:
            case 0x08:
            case 0x09:
            case 0x0a:
            case 0x0b:
            case 0x0e:
            case 0x38 ... 0x3b: /* rom */
            case 0x3d:
                can_write = 0;
                break;
            default:
                can_write = 1;
                break;
            }
306
307
308
            break;
        }
        if (can_write) {
bellard's avatar
bellard committed
309
            d->config[addr] = val;
310
        }
bellard's avatar
bellard committed
311
        addr++;
312
313
314
315
316
317
318
        val >>= 8;
    }

    end = address + len;
    if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
        /* if the command register is modified, we must modify the mappings */
        pci_update_mappings(d);
bellard's avatar
bellard committed
319
320
321
322
323
324
    }
}

static void pci_data_write(void *opaque, uint32_t addr, 
                           uint32_t val, int len)
{
325
326
327
    PCIBus *s = opaque;
    PCIDevice *pci_dev;
    int config_addr, bus_num;
bellard's avatar
bellard committed
328
329
330
331
332
333
334
335
336
337
338
    
#if defined(DEBUG_PCI) && 0
    printf("pci_data_write: addr=%08x val=%08x len=%d\n",
           s->config_reg, val, len);
#endif
    if (!(s->config_reg & (1 << 31))) {
        return;
    }
    if ((s->config_reg & 0x3) != 0) {
        return;
    }
339
340
    bus_num = (s->config_reg >> 16) & 0xff;
    if (bus_num != 0)
bellard's avatar
bellard committed
341
        return;
342
    pci_dev = s->devices[(s->config_reg >> 8) & 0xff];
bellard's avatar
bellard committed
343
344
345
346
347
348
349
    if (!pci_dev)
        return;
    config_addr = (s->config_reg & 0xfc) | (addr & 3);
#if defined(DEBUG_PCI)
    printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
           pci_dev->name, config_addr, val, len);
#endif
350
    pci_dev->config_write(pci_dev, config_addr, val, len);
bellard's avatar
bellard committed
351
352
353
354
355
}

static uint32_t pci_data_read(void *opaque, uint32_t addr, 
                              int len)
{
356
357
358
    PCIBus *s = opaque;
    PCIDevice *pci_dev;
    int config_addr, bus_num;
bellard's avatar
bellard committed
359
360
361
362
363
364
    uint32_t val;

    if (!(s->config_reg & (1 << 31)))
        goto fail;
    if ((s->config_reg & 0x3) != 0)
        goto fail;
365
366
    bus_num = (s->config_reg >> 16) & 0xff;
    if (bus_num != 0)
bellard's avatar
bellard committed
367
        goto fail;
368
    pci_dev = s->devices[(s->config_reg >> 8) & 0xff];
bellard's avatar
bellard committed
369
370
    if (!pci_dev) {
    fail:
371
372
373
374
375
376
377
378
379
380
381
382
        switch(len) {
        case 1:
            val = 0xff;
            break;
        case 2:
            val = 0xffff;
            break;
        default:
        case 4:
            val = 0xffffffff;
            break;
        }
bellard's avatar
bellard committed
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
        goto the_end;
    }
    config_addr = (s->config_reg & 0xfc) | (addr & 3);
    val = pci_dev->config_read(pci_dev, config_addr, len);
#if defined(DEBUG_PCI)
    printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
           pci_dev->name, config_addr, val, len);
#endif
 the_end:
#if defined(DEBUG_PCI) && 0
    printf("pci_data_read: addr=%08x val=%08x len=%d\n",
           s->config_reg, val, len);
#endif
    return val;
}

static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val)
{
    pci_data_write(opaque, addr, val, 1);
}

static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val)
{
    pci_data_write(opaque, addr, val, 2);
}

static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val)
{
    pci_data_write(opaque, addr, val, 4);
}

static uint32_t pci_data_readb(void* opaque, uint32_t addr)
{
    return pci_data_read(opaque, addr, 1);
}

static uint32_t pci_data_readw(void* opaque, uint32_t addr)
{
    return pci_data_read(opaque, addr, 2);
}

static uint32_t pci_data_readl(void* opaque, uint32_t addr)
{
    return pci_data_read(opaque, addr, 4);
}

/* i440FX PCI bridge */

431
432
433
static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level);

PCIBus *i440fx_init(void)
bellard's avatar
bellard committed
434
{
435
    PCIBus *s;
bellard's avatar
bellard committed
436
437
    PCIDevice *d;

438
439
440
    s = pci_register_bus();
    s->set_irq = piix3_set_irq;

441
442
    register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s);
    register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s);
bellard's avatar
bellard committed
443
444
445
446
447
448
449
450

    register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
    register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
    register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);
    register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);
    register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);
    register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);

451
    d = pci_register_device(s, "i440FX", sizeof(PCIDevice), 0, 
452
                            NULL, NULL);
bellard's avatar
bellard committed
453
454
455
456
457
458

    d->config[0x00] = 0x86; // vendor_id
    d->config[0x01] = 0x80;
    d->config[0x02] = 0x37; // device_id
    d->config[0x03] = 0x12;
    d->config[0x08] = 0x02; // revision
bellard's avatar
bellard committed
459
    d->config[0x0a] = 0x00; // class_sub = host2pci
bellard's avatar
bellard committed
460
    d->config[0x0b] = 0x06; // class_base = PCI_bridge
bellard's avatar
bellard committed
461
    d->config[0x0e] = 0x00; // header_type
462
    return s;
bellard's avatar
bellard committed
463
464
}

465
466
467
468
469
470
471
472
/* PIIX3 PCI to ISA bridge */

typedef struct PIIX3State {
    PCIDevice dev;
} PIIX3State;

PIIX3State *piix3_state;

473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
/* return the global irq number corresponding to a given device irq
   pin. We could also use the bus number to have a more precise
   mapping. */
static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
{
    int slot_addend;
    slot_addend = (pci_dev->devfn >> 3);
    return (irq_num + slot_addend) & 3;
}

static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level)
{
    int irq_index, shift, pic_irq, pic_level;
    uint32_t *p;

    irq_num = pci_slot_get_pirq(pci_dev, irq_num);
    irq_index = pci_dev->irq_index;
    p = &pci_irq_levels[irq_num][irq_index >> 5];
    shift = (irq_index & 0x1f);
    *p = (*p & ~(1 << shift)) | (level << shift);

    /* now we change the pic irq level according to the piix irq mappings */
    pic_irq = piix3_state->dev.config[0x60 + irq_num];
    if (pic_irq < 16) {
        /* the pic level is the logical OR of all the PCI irqs mapped
           to it */
        pic_level = 0;
#if (PCI_IRQ_WORDS == 2)
        pic_level = ((pci_irq_levels[irq_num][0] | 
                      pci_irq_levels[irq_num][1]) != 0);
#else
        {
            int i;
            pic_level = 0;
            for(i = 0; i < PCI_IRQ_WORDS; i++) {
                if (pci_irq_levels[irq_num][i]) {
                    pic_level = 1;
                    break;
                }
            }
        }
#endif
        pic_set_irq(pic_irq, pic_level);
    }
}

519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
static void piix3_reset(PIIX3State *d)
{
    uint8_t *pci_conf = d->dev.config;

    pci_conf[0x04] = 0x07; // master, memory and I/O
    pci_conf[0x05] = 0x00;
    pci_conf[0x06] = 0x00;
    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
    pci_conf[0x4c] = 0x4d;
    pci_conf[0x4e] = 0x03;
    pci_conf[0x4f] = 0x00;
    pci_conf[0x60] = 0x80;
    pci_conf[0x69] = 0x02;
    pci_conf[0x70] = 0x80;
    pci_conf[0x76] = 0x0c;
    pci_conf[0x77] = 0x0c;
    pci_conf[0x78] = 0x02;
    pci_conf[0x79] = 0x00;
    pci_conf[0x80] = 0x00;
    pci_conf[0x82] = 0x00;
    pci_conf[0xa0] = 0x08;
    pci_conf[0xa0] = 0x08;
    pci_conf[0xa2] = 0x00;
    pci_conf[0xa3] = 0x00;
    pci_conf[0xa4] = 0x00;
    pci_conf[0xa5] = 0x00;
    pci_conf[0xa6] = 0x00;
    pci_conf[0xa7] = 0x00;
    pci_conf[0xa8] = 0x0f;
    pci_conf[0xaa] = 0x00;
    pci_conf[0xab] = 0x00;
    pci_conf[0xac] = 0x00;
    pci_conf[0xae] = 0x00;
}

554
void piix3_init(PCIBus *bus)
555
556
557
558
{
    PIIX3State *d;
    uint8_t *pci_conf;

559
560
    d = (PIIX3State *)pci_register_device(bus, "PIIX3", sizeof(PIIX3State),
                                          -1, NULL, NULL);
561
562
563
564
565
566
567
568
569
570
571
572
573
574
    piix3_state = d;
    pci_conf = d->dev.config;

    pci_conf[0x00] = 0x86; // Intel
    pci_conf[0x01] = 0x80;
    pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
    pci_conf[0x03] = 0x70;
    pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
    pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
    pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic

    piix3_reset(d);
}

bellard's avatar
bellard committed
575
576
/* PREP pci init */

577
static inline void set_config(PCIBus *s, target_phys_addr_t addr)
bellard's avatar
bellard committed
578
579
580
581
582
583
584
585
586
587
588
{
    int devfn, i;

    for(i = 0; i < 11; i++) {
        if ((addr & (1 << (11 + i))) != 0)
            break;
    }
    devfn = ((addr >> 8) & 7) | (i << 3);
    s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8);
}

589
static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
bellard's avatar
bellard committed
590
{
591
    PCIBus *s = opaque;
bellard's avatar
bellard committed
592
593
594
595
    set_config(s, addr);
    pci_data_write(s, addr, val, 1);
}

596
static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
bellard's avatar
bellard committed
597
{
598
    PCIBus *s = opaque;
bellard's avatar
bellard committed
599
600
601
602
603
604
605
    set_config(s, addr);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap16(val);
#endif
    pci_data_write(s, addr, val, 2);
}

606
static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
bellard's avatar
bellard committed
607
{
608
    PCIBus *s = opaque;
bellard's avatar
bellard committed
609
610
611
612
613
614
615
    set_config(s, addr);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    pci_data_write(s, addr, val, 4);
}

616
static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
bellard's avatar
bellard committed
617
{
618
    PCIBus *s = opaque;
bellard's avatar
bellard committed
619
620
621
622
623
624
    uint32_t val;
    set_config(s, addr);
    val = pci_data_read(s, addr, 1);
    return val;
}

625
static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
bellard's avatar
bellard committed
626
{
627
    PCIBus *s = opaque;
bellard's avatar
bellard committed
628
629
630
631
632
633
634
635
636
    uint32_t val;
    set_config(s, addr);
    val = pci_data_read(s, addr, 2);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap16(val);
#endif
    return val;
}

637
static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
bellard's avatar
bellard committed
638
{
639
    PCIBus *s = opaque;
bellard's avatar
bellard committed
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
    uint32_t val;
    set_config(s, addr);
    val = pci_data_read(s, addr, 4);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    return val;
}

static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
    &PPC_PCIIO_writeb,
    &PPC_PCIIO_writew,
    &PPC_PCIIO_writel,
};

static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
    &PPC_PCIIO_readb,
    &PPC_PCIIO_readw,
    &PPC_PCIIO_readl,
};

661
662
663
664
665
666
667
668
static void prep_set_irq(PCIDevice *d, int irq_num, int level)
{
    /* XXX: we do not simulate the hardware - we rely on the BIOS to
       set correctly for irq line field */
    pic_set_irq(d->config[PCI_INTERRUPT_LINE], level);
}

PCIBus *pci_prep_init(void)
bellard's avatar
bellard committed
669
{
670
    PCIBus *s;
bellard's avatar
bellard committed
671
672
673
    PCIDevice *d;
    int PPC_io_memory;

674
675
676
    s = pci_register_bus();
    s->set_irq = prep_set_irq;

677
678
    PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read, 
                                           PPC_PCIIO_write, s);
bellard's avatar
bellard committed
679
680
    cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);

681
    d = pci_register_device(s, "PREP PCI Bridge", sizeof(PCIDevice), 0,
bellard's avatar
bellard committed
682
683
684
685
686
687
688
689
690
691
692
                            NULL, NULL);

    /* XXX: put correct IDs */
    d->config[0x00] = 0x11; // vendor_id
    d->config[0x01] = 0x10;
    d->config[0x02] = 0x26; // device_id
    d->config[0x03] = 0x00;
    d->config[0x08] = 0x02; // revision
    d->config[0x0a] = 0x04; // class_sub = pci2pci
    d->config[0x0b] = 0x06; // class_base = PCI_bridge
    d->config[0x0e] = 0x01; // header_type
693
    return s;
bellard's avatar
bellard committed
694
695
696
697
698
}


/* pmac pci init */

699
#if 0
bellard's avatar
bellard committed
700
701
702
/* Grackle PCI host */
static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
                                       uint32_t val)
bellard's avatar
bellard committed
703
{
704
    PCIBus *s = opaque;
bellard's avatar
bellard committed
705
706
707
708
709
710
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    s->config_reg = val;
}

bellard's avatar
bellard committed
711
static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
bellard's avatar
bellard committed
712
{
713
    PCIBus *s = opaque;
bellard's avatar
bellard committed
714
715
716
717
718
719
720
721
722
    uint32_t val;

    val = s->config_reg;
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    return val;
}

bellard's avatar
bellard committed
723
724
725
726
static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
    &pci_grackle_config_writel,
    &pci_grackle_config_writel,
    &pci_grackle_config_writel,
bellard's avatar
bellard committed
727
728
};

bellard's avatar
bellard committed
729
730
731
732
static CPUReadMemoryFunc *pci_grackle_config_read[] = {
    &pci_grackle_config_readl,
    &pci_grackle_config_readl,
    &pci_grackle_config_readl,
bellard's avatar
bellard committed
733
734
};

bellard's avatar
bellard committed
735
736
static void pci_grackle_writeb (void *opaque, target_phys_addr_t addr,
                                uint32_t val)
bellard's avatar
bellard committed
737
{
738
    PCIBus *s = opaque;
bellard's avatar
bellard committed
739
740
741
    pci_data_write(s, addr, val, 1);
}

bellard's avatar
bellard committed
742
743
static void pci_grackle_writew (void *opaque, target_phys_addr_t addr,
                                uint32_t val)
bellard's avatar
bellard committed
744
{
745
    PCIBus *s = opaque;
bellard's avatar
bellard committed
746
747
748
749
750
751
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap16(val);
#endif
    pci_data_write(s, addr, val, 2);
}

bellard's avatar
bellard committed
752
753
static void pci_grackle_writel (void *opaque, target_phys_addr_t addr,
                                uint32_t val)
bellard's avatar
bellard committed
754
{
755
    PCIBus *s = opaque;
bellard's avatar
bellard committed
756
757
758
759
760
761
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    pci_data_write(s, addr, val, 4);
}

bellard's avatar
bellard committed
762
static uint32_t pci_grackle_readb (void *opaque, target_phys_addr_t addr)
bellard's avatar
bellard committed
763
{
764
    PCIBus *s = opaque;
bellard's avatar
bellard committed
765
766
767
768
769
    uint32_t val;
    val = pci_data_read(s, addr, 1);
    return val;
}

bellard's avatar
bellard committed
770
static uint32_t pci_grackle_readw (void *opaque, target_phys_addr_t addr)
bellard's avatar
bellard committed
771
{
772
    PCIBus *s = opaque;
bellard's avatar
bellard committed
773
774
775
776
777
778
779
780
    uint32_t val;
    val = pci_data_read(s, addr, 2);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap16(val);
#endif
    return val;
}

bellard's avatar
bellard committed
781
782
static uint32_t pci_grackle_readl (void *opaque, target_phys_addr_t addr)
{
783
    PCIBus *s = opaque;
bellard's avatar
bellard committed
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
    uint32_t val;

    val = pci_data_read(s, addr, 4);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    return val;
}

static CPUWriteMemoryFunc *pci_grackle_write[] = {
    &pci_grackle_writeb,
    &pci_grackle_writew,
    &pci_grackle_writel,
};

static CPUReadMemoryFunc *pci_grackle_read[] = {
    &pci_grackle_readb,
    &pci_grackle_readw,
    &pci_grackle_readl,
};
804
#endif
bellard's avatar
bellard committed
805
806
807
808
809

/* Uninorth PCI host (for all Mac99 and newer machines */
static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
                                         uint32_t val)
{
810
    PCIBus *s = opaque;
bellard's avatar
bellard committed
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
    int i;

#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif

    for (i = 11; i < 32; i++) {
        if ((val & (1 << i)) != 0)
            break;
    }
#if 0
    s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11);
#else
    s->config_reg = 0x80000000 | (0 << 16) | (val & 0x7FC) | (i << 11);
#endif
}

static uint32_t pci_unin_main_config_readl (void *opaque,
                                            target_phys_addr_t addr)
{
831
    PCIBus *s = opaque;
bellard's avatar
bellard committed
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
    uint32_t val;
    int devfn;

    devfn = (s->config_reg >> 8) & 0xFF;
    val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif

    return val;
}

static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
    &pci_unin_main_config_writel,
    &pci_unin_main_config_writel,
    &pci_unin_main_config_writel,
};

static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
    &pci_unin_main_config_readl,
    &pci_unin_main_config_readl,
    &pci_unin_main_config_readl,
};

static void pci_unin_main_writeb (void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
859
    PCIBus *s = opaque;
bellard's avatar
bellard committed
860
861
862
863
864
865
    pci_data_write(s, addr & 7, val, 1);
}

static void pci_unin_main_writew (void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
866
    PCIBus *s = opaque;
bellard's avatar
bellard committed
867
868
869
870
871
872
873
874
875
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap16(val);
#endif
    pci_data_write(s, addr & 7, val, 2);
}

static void pci_unin_main_writel (void *opaque, target_phys_addr_t addr,
                                uint32_t val)
{
876
    PCIBus *s = opaque;
bellard's avatar
bellard committed
877
878
879
880
881
882
883
884
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    pci_data_write(s, addr & 7, val, 4);
}

static uint32_t pci_unin_main_readb (void *opaque, target_phys_addr_t addr)
{
885
    PCIBus *s = opaque;
bellard's avatar
bellard committed
886
887
888
889
890
891
892
893
894
    uint32_t val;

    val = pci_data_read(s, addr & 7, 1);

    return val;
}

static uint32_t pci_unin_main_readw (void *opaque, target_phys_addr_t addr)
{
895
    PCIBus *s = opaque;
bellard's avatar
bellard committed
896
897
898
899
900
901
902
903
904
905
906
    uint32_t val;

    val = pci_data_read(s, addr & 7, 2);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap16(val);
#endif

    return val;
}

static uint32_t pci_unin_main_readl (void *opaque, target_phys_addr_t addr)
bellard's avatar
bellard committed
907
{
908
    PCIBus *s = opaque;
bellard's avatar
bellard committed
909
910
911
912
913
914
    uint32_t val;

    val = pci_data_read(s, addr, 4);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
bellard's avatar
bellard committed
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930

    return val;
}

static CPUWriteMemoryFunc *pci_unin_main_write[] = {
    &pci_unin_main_writeb,
    &pci_unin_main_writew,
    &pci_unin_main_writel,
};

static CPUReadMemoryFunc *pci_unin_main_read[] = {
    &pci_unin_main_readb,
    &pci_unin_main_readw,
    &pci_unin_main_readl,
};

931
932
#if 0

bellard's avatar
bellard committed
933
934
935
static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
                                    uint32_t val)
{
936
    PCIBus *s = opaque;
bellard's avatar
bellard committed
937
938
939
940
941
942
943
944
945
946

#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    s->config_reg = 0x80000000 | (val & ~0x00000001);
}

static uint32_t pci_unin_config_readl (void *opaque,
                                       target_phys_addr_t addr)
{
947
    PCIBus *s = opaque;
bellard's avatar
bellard committed
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
    uint32_t val;

    val = (s->config_reg | 0x00000001) & ~0x80000000;
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif

    return val;
}

static CPUWriteMemoryFunc *pci_unin_config_write[] = {
    &pci_unin_config_writel,
    &pci_unin_config_writel,
    &pci_unin_config_writel,
};

static CPUReadMemoryFunc *pci_unin_config_read[] = {
    &pci_unin_config_readl,
    &pci_unin_config_readl,
    &pci_unin_config_readl,
};

static void pci_unin_writeb (void *opaque, target_phys_addr_t addr,
                             uint32_t val)
{
973
    PCIBus *s = opaque;
bellard's avatar
bellard committed
974
975
976
977
978
979
    pci_data_write(s, addr & 3, val, 1);
}

static void pci_unin_writew (void *opaque, target_phys_addr_t addr,
                             uint32_t val)
{
980
    PCIBus *s = opaque;
bellard's avatar
bellard committed
981
982
983
984
985
986
987
988
989
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap16(val);
#endif
    pci_data_write(s, addr & 3, val, 2);
}

static void pci_unin_writel (void *opaque, target_phys_addr_t addr,
                             uint32_t val)
{
990
    PCIBus *s = opaque;
bellard's avatar
bellard committed
991
992
993
994
995
996
997
998
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    pci_data_write(s, addr & 3, val, 4);
}

static uint32_t pci_unin_readb (void *opaque, target_phys_addr_t addr)
{
999
    PCIBus *s = opaque;
bellard's avatar
bellard committed
1000
1001
1002
1003
1004
1005
1006
1007
1008
    uint32_t val;

    val = pci_data_read(s, addr & 3, 1);

    return val;
}

static uint32_t pci_unin_readw (void *opaque, target_phys_addr_t addr)
{
1009
    PCIBus *s = opaque;
bellard's avatar
bellard committed
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
    uint32_t val;

    val = pci_data_read(s, addr & 3, 2);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap16(val);
#endif

    return val;
}

static uint32_t pci_unin_readl (void *opaque, target_phys_addr_t addr)
{
1022
    PCIBus *s = opaque;
bellard's avatar
bellard committed
1023
1024
1025
1026
1027
1028
1029
    uint32_t val;

    val = pci_data_read(s, addr & 3, 4);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif

bellard's avatar
bellard committed
1030
1031
1032
    return val;
}

bellard's avatar
bellard committed
1033
1034
1035
1036
static CPUWriteMemoryFunc *pci_unin_write[] = {
    &pci_unin_writeb,
    &pci_unin_writew,
    &pci_unin_writel,
bellard's avatar
bellard committed
1037
1038
};

bellard's avatar
bellard committed
1039
1040
1041
1042
static CPUReadMemoryFunc *pci_unin_read[] = {
    &pci_unin_readb,
    &pci_unin_readw,
    &pci_unin_readl,
bellard's avatar
bellard committed
1043
};
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
#endif

static void pmac_set_irq(PCIDevice *d, int irq_num, int level)
{
    openpic_t *openpic;
    /* XXX: we do not simulate the hardware - we rely on the BIOS to
       set correctly for irq line field */
    openpic = d->bus->openpic;
#ifdef TARGET_PPC
    if (openpic)
        openpic_set_irq(openpic, d->config[PCI_INTERRUPT_LINE], level);
#endif
}

void pci_pmac_set_openpic(PCIBus *bus, openpic_t *openpic)
{
    bus->openpic = openpic;
}
bellard's avatar
bellard committed
1062

1063
PCIBus *pci_pmac_init(void)
bellard's avatar
bellard committed
1064
{
1065
    PCIBus *s;
bellard's avatar
bellard committed
1066
1067
1068
    PCIDevice *d;
    int pci_mem_config, pci_mem_data;

bellard's avatar
bellard committed
1069
1070
    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
1071
1072
1073
    s = pci_register_bus();
    s->set_irq = pmac_set_irq;

bellard's avatar
bellard committed
1074
1075
1076
1077
1078
1079
    pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read, 
                                            pci_unin_main_config_write, s);
    pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
                                          pci_unin_main_write, s);
    cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config);
    cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data);
1080
1081
1082
    s->devfn_min = 11 << 3;
    d = pci_register_device(s, "Uni-north main", sizeof(PCIDevice), 
                            11 << 3, NULL, NULL);
bellard's avatar
bellard committed
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
    d->config[0x00] = 0x6b; // vendor_id : Apple
    d->config[0x01] = 0x10;
    d->config[0x02] = 0x1F; // device_id
    d->config[0x03] = 0x00;
    d->config[0x08] = 0x00; // revision
    d->config[0x0A] = 0x00; // class_sub = pci host
    d->config[0x0B] = 0x06; // class_base = PCI_bridge
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x0E] = 0x00; // header_type
    d->config[0x34] = 0x00; // capabilities_pointer

#if 0 // XXX: not activated as PPC BIOS doesn't handle mutiple buses properly
    /* pci-to-pci bridge */
    d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
                            NULL, NULL);
    d->config[0x00] = 0x11; // vendor_id : TI
    d->config[0x01] = 0x10;
    d->config[0x02] = 0x26; // device_id
    d->config[0x03] = 0x00;
    d->config[0x08] = 0x05; // revision
    d->config[0x0A] = 0x04; // class_sub = pci2pci
    d->config[0x0B] = 0x06; // class_base = PCI_bridge
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x20; // latency_timer
    d->config[0x0E] = 0x01; // header_type

    d->config[0x18] = 0x01; // primary_bus
    d->config[0x19] = 0x02; // secondary_bus
    d->config[0x1A] = 0x02; // subordinate_bus
    d->config[0x1B] = 0x20; // secondary_latency_timer
    d->config[0x1C] = 0x11; // io_base
    d->config[0x1D] = 0x01; // io_limit
    d->config[0x20] = 0x00; // memory_base
    d->config[0x21] = 0x80;
    d->config[0x22] = 0x00; // memory_limit
    d->config[0x23] = 0x80;
    d->config[0x24] = 0x01; // prefetchable_memory_base
    d->config[0x25] = 0x80;
    d->config[0x26] = 0xF1; // prefectchable_memory_limit
    d->config[0x27] = 0x7F;
    // d->config[0x34] = 0xdc // capabilities_pointer
#endif
#if 0 // XXX: not needed for now
    /* Uninorth AGP bus */
    s = &pci_bridge[1];
    pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read, 
                                            pci_unin_config_write, s);
    pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
                                          pci_unin_write, s);
    cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
    cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);

    d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3,
                            NULL, NULL);
    d->config[0x00] = 0x6b; // vendor_id : Apple
    d->config[0x01] = 0x10;
    d->config[0x02] = 0x20; // device_id
    d->config[0x03] = 0x00;
    d->config[0x08] = 0x00; // revision
    d->config[0x0A] = 0x00; // class_sub = pci host
    d->config[0x0B] = 0x06; // class_base = PCI_bridge
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x0E] = 0x00; // header_type
    //    d->config[0x34] = 0x80; // capabilities_pointer
#endif
bellard's avatar
bellard committed
1150

bellard's avatar
bellard committed
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
#if 0 // XXX: not needed for now
    /* Uninorth internal bus */
    s = &pci_bridge[2];
    pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read, 
                                            pci_unin_config_write, s);
    pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
                                          pci_unin_write, s);
    cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
    cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);

    d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
                            3, 11 << 3, NULL, NULL);
    d->config[0x00] = 0x6b; // vendor_id : Apple
    d->config[0x01] = 0x10;
    d->config[0x02] = 0x1E; // device_id
    d->config[0x03] = 0x00;
    d->config[0x08] = 0x00; // revision
    d->config[0x0A] = 0x00; // class_sub = pci host
    d->config[0x0B] = 0x06; // class_base = PCI_bridge
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x0E] = 0x00; // header_type
    d->config[0x34] = 0x00; // capabilities_pointer
#endif

#if 0 // Grackle ?
bellard's avatar
bellard committed
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
    /* same values as PearPC - check this */
    d->config[0x00] = 0x11; // vendor_id
    d->config[0x01] = 0x10;
    d->config[0x02] = 0x26; // device_id
    d->config[0x03] = 0x00;
    d->config[0x08] = 0x02; // revision
    d->config[0x0a] = 0x04; // class_sub = pci2pci
    d->config[0x0b] = 0x06; // class_base = PCI_bridge
    d->config[0x0e] = 0x01; // header_type

    d->config[0x18] = 0x0;  // primary_bus
    d->config[0x19] = 0x1;  // secondary_bus
    d->config[0x1a] = 0x1;  // subordinate_bus
    d->config[0x1c] = 0x10; // io_base
    d->config[0x1d] = 0x20; // io_limit
    
    d->config[0x20] = 0x80; // memory_base
    d->config[0x21] = 0x80;
    d->config[0x22] = 0x90; // memory_limit
    d->config[0x23] = 0x80;
    
    d->config[0x24] = 0x00; // prefetchable_memory_base
    d->config[0x25] = 0x84;
    d->config[0x26] = 0x00; // prefetchable_memory_limit
    d->config[0x27] = 0x85;
bellard's avatar
bellard committed
1202
#endif
1203
    return s;
bellard's avatar
bellard committed
1204
1205
}

1206
1207
1208
1209
/***********************************************************/
/* generic PCI irq support */

/* 0 <= irq_num <= 3. level must be 0 or 1 */
bellard's avatar
bellard committed
1210
1211
void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
{
1212
1213
    PCIBus *bus = pci_dev->bus;
    bus->set_irq(pci_dev, irq_num, level);
bellard's avatar
bellard committed
1214
}
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224

/***********************************************************/
/* monitor info on PCI */

static void pci_info_device(PCIDevice *d)
{
    int i, class;
    PCIIORegion *r;

    printf("  Bus %2d, device %3d, function %d:\n",
1225
           d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
    class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
    printf("    ");
    switch(class) {
    case 0x0101:
        printf("IDE controller");
        break;
    case 0x0200:
        printf("Ethernet controller");
        break;
    case 0x0300:
        printf("VGA controller");
        break;
    default:
        printf("Class %04x", class);
        break;
    }
    printf(": PCI device %04x:%04x\n",
           le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
           le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));

    if (d->config[PCI_INTERRUPT_PIN] != 0) {
        printf("      IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
    }
1249
    for(i = 0;i < PCI_NUM_REGIONS; i++) {
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
        r = &d->io_regions[i];
        if (r->size != 0) {
            printf("      BAR%d: ", i);
            if (r->type & PCI_ADDRESS_SPACE_IO) {
                printf("I/O at 0x%04x [0x%04x].\n", 
                       r->addr, r->addr + r->size - 1);
            } else {
                printf("32 bit memory at 0x%08x [0x%08x].\n", 
                       r->addr, r->addr + r->size - 1);
            }
        }
    }
}

void pci_info(void)
{
1266
1267
1268
    PCIBus *bus = first_bus;
    PCIDevice *d;
    int devfn;
1269
    
1270
1271
1272
1273
1274
    if (bus) {
        for(devfn = 0; devfn < 256; devfn++) {
            d = bus->devices[devfn];
            if (d)
                pci_info_device(d);
1275
1276
1277
1278
1279
1280
1281
        }
    }
}

/***********************************************************/
/* XXX: the following should be moved to the PC BIOS */

1282
static __attribute__((unused)) uint32_t isa_inb(uint32_t addr)
1283
1284
1285
1286
1287
1288
1289
1290
1291
{
    return cpu_inb(cpu_single_env, addr);
}

static void isa_outb(uint32_t val, uint32_t addr)
{
    cpu_outb(cpu_single_env, addr, val);
}

1292
static __attribute__((unused)) uint32_t isa_inw(uint32_t addr)
1293
1294
1295
1296
{
    return cpu_inw(cpu_single_env, addr);
}

1297
static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr)
1298
1299
1300
1301
{
    cpu_outw(cpu_single_env, addr, val);
}

1302
static __attribute__((unused)) uint32_t isa_inl(uint32_t addr)
1303
1304
1305
1306
{
    return cpu_inl(cpu_single_env, addr);
}

1307
static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr)
1308
1309
1310
1311
1312
1313
{
    cpu_outl(cpu_single_env, addr, val);
}

static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
{
1314
1315
    PCIBus *s = d->bus;
    s->config_reg = 0x80000000 | (s->bus_num << 16) | 
1316
1317
1318
1319
1320
1321
        (d->devfn << 8) | addr;
    pci_data_write(s, 0, val, 4);
}

static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
{
1322
1323
    PCIBus *s = d->bus;
    s->config_reg = 0x80000000 | (s->bus_num << 16) | 
1324
1325
1326
1327
1328
1329
        (d->devfn << 8) | (addr & ~3);
    pci_data_write(s, addr & 3, val, 2);
}

static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
{
1330
1331
    PCIBus *s = d->bus;
    s->config_reg = 0x80000000 | (s->bus_num << 16) | 
1332
1333
1334
1335
        (d->devfn << 8) | (addr & ~3);
    pci_data_write(s, addr & 3, val, 1);
}

1336
static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
1337
{
1338
1339
    PCIBus *s = d->bus;
    s->config_reg = 0x80000000 | (s->bus_num << 16) | 
1340
1341
1342
1343
1344
1345
        (d->devfn << 8) | addr;
    return pci_data_read(s, 0, 4);
}

static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
{
1346
1347
    PCIBus *s = d->bus;
    s->config_reg = 0x80000000 | (s->bus_num << 16) | 
1348
1349
1350
1351
1352
1353
        (d->devfn << 8) | (addr & ~3);
    return pci_data_read(s, addr & 3, 2);
}

static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
{
1354
1355
    PCIBus *s = d->bus;
    s->config_reg = 0x80000000 | (s->bus_num << 16) | 
1356
1357
1358
        (d->devfn << 8) | (addr & ~3);
    return pci_data_read(s, addr & 3, 1);
}
bellard's avatar
bellard committed
1359
1360
1361

static uint32_t pci_bios_io_addr;
static uint32_t pci_bios_mem_addr;
1362
1363
/* host irqs corresponding to PCI irqs A-D */
static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
bellard's avatar
bellard committed
1364
1365
1366
1367

static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
{
    PCIIORegion *r;
1368
    uint16_t cmd;
1369
1370
1371
1372
1373
1374
1375
    uint32_t ofs;

    if ( region_num == PCI_ROM_SLOT ) {
        ofs = 0x30;
    }else{
        ofs = 0x10 + region_num * 4;
    }
bellard's avatar
bellard committed
1376

1377
    pci_config_writel(d, ofs, addr);
bellard's avatar
bellard committed
1378
1379
1380
    r = &d->io_regions[region_num];

    /* enable memory mappings */
1381
    cmd = pci_config_readw(d, PCI_COMMAND);
1382
1383
1384
    if ( region_num == PCI_ROM_SLOT )
        cmd |= 2;
    else if (r->type & PCI_ADDRESS_SPACE_IO)
1385
        cmd |= 1;
bellard's avatar
bellard committed
1386
    else
1387
1388
        cmd |= 2;
    pci_config_writew(d, PCI_COMMAND, cmd);
bellard's avatar
bellard committed
1389
1390
1391
1392
1393
1394
1395
}

static void pci_bios_init_device(PCIDevice *d)
{
    int class;
    PCIIORegion *r;
    uint32_t *paddr;
1396
    int i, pin, pic_irq, vendor_id, device_id;
bellard's avatar
bellard committed
1397

1398
    class = pci_config_readw(d, PCI_CLASS_DEVICE);
1399
1400
    vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
    device_id = pci_config_readw(d, PCI_DEVICE_ID);
bellard's avatar
bellard committed
1401
1402
    switch(class) {
    case 0x0101:
1403
1404
1405
        if (vendor_id == 0x8086 && device_id == 0x7010) {
            /* PIIX3 IDE */
            pci_config_writew(d, 0x40, 0x8000); // enable IDE0
bellard's avatar
bellard committed
1406
            pci_config_writew(d, 0x42, 0x8000); // enable IDE1
bellard's avatar
bellard committed
1407
            goto default_map;
1408
1409
1410
1411
1412
1413
1414
        } else {
            /* IDE: we map it as in ISA mode */
            pci_set_io_region_addr(d, 0, 0x1f0);
            pci_set_io_region_addr(d, 1, 0x3f4);
            pci_set_io_region_addr(d, 2, 0x170);
            pci_set_io_region_addr(d, 3, 0x374);
        }
bellard's avatar
bellard committed
1415
        break;
1416
    case 0x0300:
bellard's avatar
bellard committed
1417
1418
        if (vendor_id != 0x1234)
            goto default_map;
1419
1420
1421
        /* VGA: map frame buffer to default Bochs VBE address */
        pci_set_io_region_addr(d, 0, 0xE0000000);
        break;
bellard's avatar
bellard committed
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
    case 0x0800:
        /* PIC */
        vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
        device_id = pci_config_readw(d, PCI_DEVICE_ID);
        if (vendor_id == 0x1014) {
            /* IBM */
            if (device_id == 0x0046 || device_id == 0xFFFF) {
                /* MPIC & MPIC2 */
                pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
            }
        }
        break;
1434
    case 0xff00:
bellard's avatar
bellard committed
1435
1436
        if (vendor_id == 0x0106b &&
            (device_id == 0x0017 || device_id == 0x0022)) {
1437
1438
1439
1440
            /* macio bridge */
            pci_set_io_region_addr(d, 0, 0x80800000);
        }
        break;
bellard's avatar
bellard committed
1441
    default:
bellard's avatar
bellard committed
1442
    default_map:
bellard's avatar
bellard committed
1443
        /* default memory mappings */
1444
        for(i = 0; i < PCI_NUM_REGIONS; i++) {
bellard's avatar
bellard committed
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
            r = &d->io_regions[i];
            if (r->size) {
                if (r->type & PCI_ADDRESS_SPACE_IO)
                    paddr = &pci_bios_io_addr;
                else
                    paddr = &pci_bios_mem_addr;
                *paddr = (*paddr + r->size - 1) & ~(r->size - 1);
                pci_set_io_region_addr(d, i, *paddr);
                *paddr += r->size;
            }
        }
        break;
    }
1458
1459
1460
1461
1462
1463
1464
1465

    /* map the interrupt */
    pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
    if (pin != 0) {
        pin = pci_slot_get_pirq(d, pin - 1);
        pic_irq = pci_irqs[pin];
        pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
    }
bellard's avatar
bellard committed
1466
1467
1468
1469
1470
1471
1472
1473
1474
}

/*
 * This function initializes the PCI devices as a normal PCI BIOS
 * would do. It is provided just in case the BIOS has no support for
 * PCI.
 */
void pci_bios_init(void)
{
1475
1476
1477
    PCIBus *bus;
    PCIDevice *d;
    int devfn, i, irq;
1478
    uint8_t elcr[2];
bellard's avatar
bellard committed
1479
1480
1481
1482

    pci_bios_io_addr = 0xc000;
    pci_bios_mem_addr = 0xf0000000;

1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
    /* activate IRQ mappings */
    elcr[0] = 0x00;
    elcr[1] = 0x00;
    for(i = 0; i < 4; i++) {
        irq = pci_irqs[i];
        /* set to trigger level */
        elcr[irq >> 3] |= (1 << (irq & 7));
        /* activate irq remapping in PIIX */
        pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
    }
    isa_outb(elcr[0], 0x4d0);
    isa_outb(elcr[1], 0x4d1);

1496
1497
1498
1499
1500
1501
    bus = first_bus;
    if (bus) {
        for(devfn = 0; devfn < 256; devfn++) {
            d = bus->devices[devfn];
            if (d)
                pci_bios_init_device(d);
bellard's avatar
bellard committed
1502
1503
1504
        }
    }
}