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/*
   SPARC translation

   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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   Copyright (C) 2003 Fabrice Bellard
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   This library is free software; you can redistribute it and/or
   modify it under the terms of the GNU Lesser General Public
   License as published by the Free Software Foundation; either
   version 2 of the License, or (at your option) any later version.

   This library is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   Lesser General Public License for more details.

   You should have received a copy of the GNU Lesser General Public
   License along with this library; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/*
   TODO-list:

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   NPC/PC static optimisations (use JUMP_TB when possible)
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   FPU-Instructions
   Privileged instructions
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   Coprocessor-Instructions
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   Optimize synthetic instructions
   Optional alignment and privileged instruction check
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*/
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#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>

#include "cpu.h"
#include "exec-all.h"
#include "disas.h"

#define DEBUG_DISAS

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#define DYNAMIC_PC  1 /* dynamic pc value */
#define JUMP_PC     2 /* dynamic pc value which takes only two values
                         according to jump_pc[T2] */

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typedef struct DisasContext {
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    target_ulong pc;	/* current Program Counter: integer or DYNAMIC_PC */
    target_ulong npc;	/* next PC: integer or DYNAMIC_PC or JUMP_PC */
    target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
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    int is_br;
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    int mem_idx;
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    struct TranslationBlock *tb;
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} DisasContext;

static uint16_t *gen_opc_ptr;
static uint32_t *gen_opparam_ptr;
extern FILE *logfile;
extern int loglevel;

enum {
#define DEF(s,n,copy_size) INDEX_op_ ## s,
#include "opc.h"
#undef DEF
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    NB_OPS
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};

#include "gen-op.h"

#define GET_FIELD(X, FROM, TO) \
  ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))

#define IS_IMM (insn & (1<<13))

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static void disas_sparc_insn(DisasContext * dc);
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static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
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    {
     gen_op_movl_g0_T0,
     gen_op_movl_g1_T0,
     gen_op_movl_g2_T0,
     gen_op_movl_g3_T0,
     gen_op_movl_g4_T0,
     gen_op_movl_g5_T0,
     gen_op_movl_g6_T0,
     gen_op_movl_g7_T0,
     gen_op_movl_o0_T0,
     gen_op_movl_o1_T0,
     gen_op_movl_o2_T0,
     gen_op_movl_o3_T0,
     gen_op_movl_o4_T0,
     gen_op_movl_o5_T0,
     gen_op_movl_o6_T0,
     gen_op_movl_o7_T0,
     gen_op_movl_l0_T0,
     gen_op_movl_l1_T0,
     gen_op_movl_l2_T0,
     gen_op_movl_l3_T0,
     gen_op_movl_l4_T0,
     gen_op_movl_l5_T0,
     gen_op_movl_l6_T0,
     gen_op_movl_l7_T0,
     gen_op_movl_i0_T0,
     gen_op_movl_i1_T0,
     gen_op_movl_i2_T0,
     gen_op_movl_i3_T0,
     gen_op_movl_i4_T0,
     gen_op_movl_i5_T0,
     gen_op_movl_i6_T0,
     gen_op_movl_i7_T0,
     },
    {
     gen_op_movl_g0_T1,
     gen_op_movl_g1_T1,
     gen_op_movl_g2_T1,
     gen_op_movl_g3_T1,
     gen_op_movl_g4_T1,
     gen_op_movl_g5_T1,
     gen_op_movl_g6_T1,
     gen_op_movl_g7_T1,
     gen_op_movl_o0_T1,
     gen_op_movl_o1_T1,
     gen_op_movl_o2_T1,
     gen_op_movl_o3_T1,
     gen_op_movl_o4_T1,
     gen_op_movl_o5_T1,
     gen_op_movl_o6_T1,
     gen_op_movl_o7_T1,
     gen_op_movl_l0_T1,
     gen_op_movl_l1_T1,
     gen_op_movl_l2_T1,
     gen_op_movl_l3_T1,
     gen_op_movl_l4_T1,
     gen_op_movl_l5_T1,
     gen_op_movl_l6_T1,
     gen_op_movl_l7_T1,
     gen_op_movl_i0_T1,
     gen_op_movl_i1_T1,
     gen_op_movl_i2_T1,
     gen_op_movl_i3_T1,
     gen_op_movl_i4_T1,
     gen_op_movl_i5_T1,
     gen_op_movl_i6_T1,
     gen_op_movl_i7_T1,
     }
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};

static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
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    {
     gen_op_movl_T0_g0,
     gen_op_movl_T0_g1,
     gen_op_movl_T0_g2,
     gen_op_movl_T0_g3,
     gen_op_movl_T0_g4,
     gen_op_movl_T0_g5,
     gen_op_movl_T0_g6,
     gen_op_movl_T0_g7,
     gen_op_movl_T0_o0,
     gen_op_movl_T0_o1,
     gen_op_movl_T0_o2,
     gen_op_movl_T0_o3,
     gen_op_movl_T0_o4,
     gen_op_movl_T0_o5,
     gen_op_movl_T0_o6,
     gen_op_movl_T0_o7,
     gen_op_movl_T0_l0,
     gen_op_movl_T0_l1,
     gen_op_movl_T0_l2,
     gen_op_movl_T0_l3,
     gen_op_movl_T0_l4,
     gen_op_movl_T0_l5,
     gen_op_movl_T0_l6,
     gen_op_movl_T0_l7,
     gen_op_movl_T0_i0,
     gen_op_movl_T0_i1,
     gen_op_movl_T0_i2,
     gen_op_movl_T0_i3,
     gen_op_movl_T0_i4,
     gen_op_movl_T0_i5,
     gen_op_movl_T0_i6,
     gen_op_movl_T0_i7,
     },
    {
     gen_op_movl_T1_g0,
     gen_op_movl_T1_g1,
     gen_op_movl_T1_g2,
     gen_op_movl_T1_g3,
     gen_op_movl_T1_g4,
     gen_op_movl_T1_g5,
     gen_op_movl_T1_g6,
     gen_op_movl_T1_g7,
     gen_op_movl_T1_o0,
     gen_op_movl_T1_o1,
     gen_op_movl_T1_o2,
     gen_op_movl_T1_o3,
     gen_op_movl_T1_o4,
     gen_op_movl_T1_o5,
     gen_op_movl_T1_o6,
     gen_op_movl_T1_o7,
     gen_op_movl_T1_l0,
     gen_op_movl_T1_l1,
     gen_op_movl_T1_l2,
     gen_op_movl_T1_l3,
     gen_op_movl_T1_l4,
     gen_op_movl_T1_l5,
     gen_op_movl_T1_l6,
     gen_op_movl_T1_l7,
     gen_op_movl_T1_i0,
     gen_op_movl_T1_i1,
     gen_op_movl_T1_i2,
     gen_op_movl_T1_i3,
     gen_op_movl_T1_i4,
     gen_op_movl_T1_i5,
     gen_op_movl_T1_i6,
     gen_op_movl_T1_i7,
     },
    {
     gen_op_movl_T2_g0,
     gen_op_movl_T2_g1,
     gen_op_movl_T2_g2,
     gen_op_movl_T2_g3,
     gen_op_movl_T2_g4,
     gen_op_movl_T2_g5,
     gen_op_movl_T2_g6,
     gen_op_movl_T2_g7,
     gen_op_movl_T2_o0,
     gen_op_movl_T2_o1,
     gen_op_movl_T2_o2,
     gen_op_movl_T2_o3,
     gen_op_movl_T2_o4,
     gen_op_movl_T2_o5,
     gen_op_movl_T2_o6,
     gen_op_movl_T2_o7,
     gen_op_movl_T2_l0,
     gen_op_movl_T2_l1,
     gen_op_movl_T2_l2,
     gen_op_movl_T2_l3,
     gen_op_movl_T2_l4,
     gen_op_movl_T2_l5,
     gen_op_movl_T2_l6,
     gen_op_movl_T2_l7,
     gen_op_movl_T2_i0,
     gen_op_movl_T2_i1,
     gen_op_movl_T2_i2,
     gen_op_movl_T2_i3,
     gen_op_movl_T2_i4,
     gen_op_movl_T2_i5,
     gen_op_movl_T2_i6,
     gen_op_movl_T2_i7,
     }
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};

static GenOpFunc1 *gen_op_movl_TN_im[3] = {
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    gen_op_movl_T0_im,
    gen_op_movl_T1_im,
    gen_op_movl_T2_im
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};

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#define GEN32(func, NAME) \
static GenOpFunc *NAME ## _table [32] = {                                     \
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
};                                                                            \
static inline void func(int n)                                                \
{                                                                             \
    NAME ## _table[n]();                                                      \
}

/* floating point registers moves */
GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fprf);
GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fprf);

GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
GEN32(gen_op_load_fpr_DT2, gen_op_load_fpr_DT2_fprf);
GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
GEN32(gen_op_store_DT2_fpr, gen_op_store_DT2_fpr_fprf);

#if defined(CONFIG_USER_ONLY)
#define gen_op_ldst(name)        gen_op_##name##_raw()
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#define OP_LD_TABLE(width)
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#define supervisor(dc) 0
#else
#define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
#define OP_LD_TABLE(width)						      \
static GenOpFunc *gen_op_##width[] = {                                        \
    &gen_op_##width##_user,                                                   \
    &gen_op_##width##_kernel,                                                 \
};                                                                            \
                                                                              \
static void gen_op_##width##a(int insn, int is_ld, int size, int sign)        \
{                                                                             \
    int asi;                                                                  \
                                                                              \
    asi = GET_FIELD(insn, 19, 26);                                            \
    switch (asi) {                                                            \
	case 10: /* User data access */                                       \
	    gen_op_##width##_user();                                          \
	    break;                                                            \
	case 11: /* Supervisor data access */                                 \
	    gen_op_##width##_kernel();                                        \
	    break;                                                            \
        case 0x20 ... 0x2f: /* MMU passthrough */			      \
	    if (is_ld)                                                        \
		gen_op_ld_asi(asi, size, sign);				      \
	    else                                                              \
		gen_op_st_asi(asi, size, sign);				      \
	    break;                                                            \
	default:                                                              \
	    if (is_ld)                                                        \
		gen_op_ld_asi(asi, size, sign);			              \
	    else                                                              \
		gen_op_st_asi(asi, size, sign);				      \
            break;                                                            \
    }                                                                         \
}

#define supervisor(dc) (dc->mem_idx == 1)
#endif

OP_LD_TABLE(ld);
OP_LD_TABLE(st);
OP_LD_TABLE(ldub);
OP_LD_TABLE(lduh);
OP_LD_TABLE(ldsb);
OP_LD_TABLE(ldsh);
OP_LD_TABLE(stb);
OP_LD_TABLE(sth);
OP_LD_TABLE(std);
OP_LD_TABLE(ldstub);
OP_LD_TABLE(swap);
OP_LD_TABLE(ldd);
OP_LD_TABLE(stf);
OP_LD_TABLE(stdf);
OP_LD_TABLE(ldf);
OP_LD_TABLE(lddf);

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static inline void gen_movl_imm_TN(int reg, int imm)
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{
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    gen_op_movl_TN_im[reg] (imm);
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}

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static inline void gen_movl_imm_T1(int val)
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{
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    gen_movl_imm_TN(1, val);
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}

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static inline void gen_movl_imm_T0(int val)
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{
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    gen_movl_imm_TN(0, val);
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}

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static inline void gen_movl_reg_TN(int reg, int t)
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{
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    if (reg)
	gen_op_movl_reg_TN[t][reg] ();
    else
	gen_movl_imm_TN(t, 0);
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}

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static inline void gen_movl_reg_T0(int reg)
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{
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    gen_movl_reg_TN(reg, 0);
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}

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static inline void gen_movl_reg_T1(int reg)
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{
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    gen_movl_reg_TN(reg, 1);
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}

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static inline void gen_movl_reg_T2(int reg)
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{
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    gen_movl_reg_TN(reg, 2);
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}

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static inline void gen_movl_TN_reg(int reg, int t)
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{
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    if (reg)
	gen_op_movl_TN_reg[t][reg] ();
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}

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static inline void gen_movl_T0_reg(int reg)
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{
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    gen_movl_TN_reg(reg, 0);
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}

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static inline void gen_movl_T1_reg(int reg)
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{
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    gen_movl_TN_reg(reg, 1);
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}

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/* call this function before using T2 as it may have been set for a jump */
static inline void flush_T2(DisasContext * dc)
{
    if (dc->npc == JUMP_PC) {
        gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
        dc->npc = DYNAMIC_PC;
    }
}

static inline void save_npc(DisasContext * dc)
{
    if (dc->npc == JUMP_PC) {
        gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
        dc->npc = DYNAMIC_PC;
    } else if (dc->npc != DYNAMIC_PC) {
        gen_op_movl_npc_im(dc->npc);
    }
}

static inline void save_state(DisasContext * dc)
{
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    gen_op_jmp_im(dc->pc);
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    save_npc(dc);
}

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static inline void gen_mov_pc_npc(DisasContext * dc)
{
    if (dc->npc == JUMP_PC) {
        gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
        gen_op_mov_pc_npc();
        dc->pc = DYNAMIC_PC;
    } else if (dc->npc == DYNAMIC_PC) {
        gen_op_mov_pc_npc();
        dc->pc = DYNAMIC_PC;
    } else {
        dc->pc = dc->npc;
    }
}

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static void gen_cond(int cond)
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{
	switch (cond) {
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	case 0x1:
	    gen_op_eval_be();
	    break;
	case 0x2:
	    gen_op_eval_ble();
	    break;
	case 0x3:
	    gen_op_eval_bl();
	    break;
	case 0x4:
	    gen_op_eval_bleu();
	    break;
	case 0x5:
	    gen_op_eval_bcs();
	    break;
	case 0x6:
	    gen_op_eval_bneg();
	    break;
	case 0x7:
	    gen_op_eval_bvs();
	    break;
	case 0x9:
	    gen_op_eval_bne();
	    break;
	case 0xa:
	    gen_op_eval_bg();
	    break;
	case 0xb:
	    gen_op_eval_bge();
	    break;
	case 0xc:
	    gen_op_eval_bgu();
	    break;
	case 0xd:
	    gen_op_eval_bcc();
	    break;
	case 0xe:
	    gen_op_eval_bpos();
	    break;
        default:
	case 0xf:
	    gen_op_eval_bvc();
	    break;
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	}
}

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static void gen_fcond(int cond)
{
	switch (cond) {
	case 0x1:
	    gen_op_eval_fbne();
	    break;
	case 0x2:
	    gen_op_eval_fblg();
	    break;
	case 0x3:
	    gen_op_eval_fbul();
	    break;
	case 0x4:
	    gen_op_eval_fbl();
	    break;
	case 0x5:
	    gen_op_eval_fbug();
	    break;
	case 0x6:
	    gen_op_eval_fbg();
	    break;
	case 0x7:
	    gen_op_eval_fbu();
	    break;
	case 0x9:
	    gen_op_eval_fbe();
	    break;
	case 0xa:
	    gen_op_eval_fbue();
	    break;
	case 0xb:
	    gen_op_eval_fbge();
	    break;
	case 0xc:
	    gen_op_eval_fbuge();
	    break;
	case 0xd:
	    gen_op_eval_fble();
	    break;
	case 0xe:
	    gen_op_eval_fbule();
	    break;
        default:
	case 0xf:
	    gen_op_eval_fbo();
	    break;
	}
}
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/* XXX: potentially incorrect if dynamic npc */
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static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn)
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{
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    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
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    target_ulong target = dc->pc + offset;

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    if (cond == 0x0) {
	/* unconditional not taken */
	if (a) {
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	    dc->pc = dc->npc + 4; 
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	    dc->npc = dc->pc + 4;
	} else {
	    dc->pc = dc->npc;
	    dc->npc = dc->pc + 4;
	}
    } else if (cond == 0x8) {
	/* unconditional taken */
	if (a) {
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	    dc->pc = target;
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	    dc->npc = dc->pc + 4;
	} else {
	    dc->pc = dc->npc;
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	    dc->npc = target;
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	}
    } else {
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        flush_T2(dc);
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        gen_cond(cond);
	if (a) {
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	    gen_op_branch_a((long)dc->tb, target, dc->npc);
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            dc->is_br = 1;
	} else {
            dc->pc = dc->npc;
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            dc->jump_pc[0] = target;
            dc->jump_pc[1] = dc->npc + 4;
            dc->npc = JUMP_PC;
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	}
    }
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}

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/* XXX: potentially incorrect if dynamic npc */
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static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn)
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{
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
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    target_ulong target = dc->pc + offset;

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    if (cond == 0x0) {
	/* unconditional not taken */
	if (a) {
	    dc->pc = dc->npc + 4;
	    dc->npc = dc->pc + 4;
	} else {
	    dc->pc = dc->npc;
	    dc->npc = dc->pc + 4;
	}
    } else if (cond == 0x8) {
	/* unconditional taken */
	if (a) {
	    dc->pc = target;
	    dc->npc = dc->pc + 4;
	} else {
	    dc->pc = dc->npc;
	    dc->npc = target;
	}
    } else {
        flush_T2(dc);
        gen_fcond(cond);
	if (a) {
	    gen_op_branch_a((long)dc->tb, target, dc->npc);
            dc->is_br = 1;
	} else {
            dc->pc = dc->npc;
            dc->jump_pc[0] = target;
            dc->jump_pc[1] = dc->npc + 4;
            dc->npc = JUMP_PC;
	}
    }
}

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#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
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static int sign_extend(int x, int len)
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{
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    len = 32 - len;
    return (x << len) >> len;
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}

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/* before an instruction, dc->pc must be static */
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static void disas_sparc_insn(DisasContext * dc)
{
    unsigned int insn, opc, rs1, rs2, rd;
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    insn = ldl_code(dc->pc);
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    opc = GET_FIELD(insn, 0, 1);
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    rd = GET_FIELD(insn, 2, 6);
    switch (opc) {
    case 0:			/* branches/sethi */
	{
	    unsigned int xop = GET_FIELD(insn, 7, 9);
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	    int32_t target;
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	    target = GET_FIELD(insn, 10, 31);
	    switch (xop) {
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	    case 0x0:		/* UNIMPL */
	    case 0x1:		/* V9 BPcc */
	    case 0x3:		/* V9 BPr */
	    case 0x5:		/* V9 FBPcc */
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	    default:
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                goto illegal_insn;
	    case 0x2:		/* BN+x */
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		{
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		    target <<= 2;
		    target = sign_extend(target, 22);
		    do_branch(dc, target, insn);
		    goto jmp_insn;
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		}
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	    case 0x6:		/* FBN+x */
		{
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#if !defined(CONFIG_USER_ONLY)
		    gen_op_trap_ifnofpu();
#endif
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		    target <<= 2;
		    target = sign_extend(target, 22);
		    do_fbranch(dc, target, insn);
		    goto jmp_insn;
		}
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	    case 0x4:		/* SETHI */
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#define OPTIM
#if defined(OPTIM)
		if (rd) { // nop
#endif
		    gen_movl_imm_T0(target << 10);
		    gen_movl_T0_reg(rd);
#if defined(OPTIM)
		}
#endif
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		break;
	    }
	    break;
	}
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	break;
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    case 1:
	/*CALL*/ {
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	    target_long target = GET_FIELDs(insn, 2, 31) << 2;
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	    gen_op_movl_T0_im(dc->pc);
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	    gen_movl_T0_reg(15);
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	    target += dc->pc;
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            gen_mov_pc_npc(dc);
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	    dc->npc = target;
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	}
	goto jmp_insn;
    case 2:			/* FPU & Logical Operations */
	{
	    unsigned int xop = GET_FIELD(insn, 7, 12);
	    if (xop == 0x3a) {	/* generate trap */
                int cond;
                rs1 = GET_FIELD(insn, 13, 17);
                gen_movl_reg_T0(rs1);
		if (IS_IMM) {
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		    rs2 = GET_FIELD(insn, 25, 31);
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#if defined(OPTIM)
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		    if (rs2 != 0) {
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#endif
			gen_movl_imm_T1(rs2);
			gen_op_add_T1_T0();
#if defined(OPTIM)
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		    }
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#endif
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                } else {
                    rs2 = GET_FIELD(insn, 27, 31);
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#if defined(OPTIM)
		    if (rs2 != 0) {
#endif
			gen_movl_reg_T1(rs2);
			gen_op_add_T1_T0();
#if defined(OPTIM)
		    }
#endif
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                }
                save_state(dc);
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		/* V9 icc/xcc */
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                cond = GET_FIELD(insn, 3, 6);
                if (cond == 0x8) {
                    gen_op_trap_T0();
                    dc->is_br = 1;
                    goto jmp_insn;
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                } else if (cond != 0) {
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		    gen_cond(cond);
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                    gen_op_trapcc_T0();
                }
            } else if (xop == 0x28) {
                rs1 = GET_FIELD(insn, 13, 17);
                switch(rs1) {
                case 0: /* rdy */
                    gen_op_rdy();
                    gen_movl_T0_reg(rd);
                    break;
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                case 15: /* stbar / V9 membar */
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		    break; /* no effect? */
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                default:
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		case 0x2: /* V9 rdccr */
		case 0x3: /* V9 rdasi */
		case 0x4: /* V9 rdtick */
		case 0x5: /* V9 rdpc */
		case 0x6: /* V9 rdfprs */
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                    goto illegal_insn;
                }
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#if !defined(CONFIG_USER_ONLY)
            } else if (xop == 0x29) {
		if (!supervisor(dc))
		    goto priv_insn;
                gen_op_rdpsr();
                gen_movl_T0_reg(rd);
                break;
            } else if (xop == 0x2a) {
		if (!supervisor(dc))
		    goto priv_insn;
                gen_op_rdwim();
                gen_movl_T0_reg(rd);
                break;
            } else if (xop == 0x2b) {
		if (!supervisor(dc))
		    goto priv_insn;
                gen_op_rdtbr();
                gen_movl_T0_reg(rd);
                break;
#endif
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	    } else if (xop == 0x34) {	/* FPU Operations */
#if !defined(CONFIG_USER_ONLY)
		gen_op_trap_ifnofpu();
#endif
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                rs1 = GET_FIELD(insn, 13, 17);
	        rs2 = GET_FIELD(insn, 27, 31);
	        xop = GET_FIELD(insn, 18, 26);
		switch (xop) {
		    case 0x1: /* fmovs */
                	gen_op_load_fpr_FT0(rs2);
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x5: /* fnegs */
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fnegs();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x9: /* fabss */
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fabss();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x29: /* fsqrts */
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fsqrts();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x2a: /* fsqrtd */
                	gen_op_load_fpr_DT1(rs2);
			gen_op_fsqrtd();
			gen_op_store_DT0_fpr(rd);
			break;
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		    case 0x2b: /* fsqrtq */
		        goto nfpu_insn;
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		    case 0x41:
                	gen_op_load_fpr_FT0(rs1);
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fadds();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x42:
                	gen_op_load_fpr_DT0(rs1);
                	gen_op_load_fpr_DT1(rs2);
			gen_op_faddd();
			gen_op_store_DT0_fpr(rd);
			break;
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		    case 0x43: /* faddq */
		        goto nfpu_insn;
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		    case 0x45:
                	gen_op_load_fpr_FT0(rs1);
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fsubs();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x46:
                	gen_op_load_fpr_DT0(rs1);
                	gen_op_load_fpr_DT1(rs2);
			gen_op_fsubd();
			gen_op_store_DT0_fpr(rd);
			break;
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		    case 0x47: /* fsubq */
		        goto nfpu_insn;
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		    case 0x49:
                	gen_op_load_fpr_FT0(rs1);
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fmuls();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x4a:
                	gen_op_load_fpr_DT0(rs1);
                	gen_op_load_fpr_DT1(rs2);
			gen_op_fmuld();
			gen_op_store_DT0_fpr(rd);
			break;
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		    case 0x4b: /* fmulq */
		        goto nfpu_insn;
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		    case 0x4d:
                	gen_op_load_fpr_FT0(rs1);
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fdivs();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x4e:
                	gen_op_load_fpr_DT0(rs1);
                	gen_op_load_fpr_DT1(rs2);
			gen_op_fdivd();
			gen_op_store_DT0_fpr(rd);
			break;
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		    case 0x4f: /* fdivq */
		        goto nfpu_insn;
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		    case 0x69:
                	gen_op_load_fpr_FT0(rs1);
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fsmuld();
			gen_op_store_DT0_fpr(rd);
			break;
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		    case 0x6e: /* fdmulq */
		        goto nfpu_insn;
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		    case 0xc4:
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fitos();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0xc6:
                	gen_op_load_fpr_DT1(rs2);
			gen_op_fdtos();
			gen_op_store_FT0_fpr(rd);
			break;
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		    case 0xc7: /* fqtos */
		        goto nfpu_insn;
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		    case 0xc8:
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fitod();
			gen_op_store_DT0_fpr(rd);
			break;
		    case 0xc9:
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fstod();
			gen_op_store_DT0_fpr(rd);
			break;
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		    case 0xcb: /* fqtod */
		        goto nfpu_insn;
		    case 0xcc: /* fitoq */
		        goto nfpu_insn;
		    case 0xcd: /* fstoq */
		        goto nfpu_insn;
		    case 0xce: /* fdtoq */
		        goto nfpu_insn;
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		    case 0xd1:
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fstoi();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0xd2:
                	gen_op_load_fpr_DT1(rs2);
			gen_op_fdtoi();
			gen_op_store_FT0_fpr(rd);
			break;
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		    case 0xd3: /* fqtoi */
		        goto nfpu_insn;
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		    default:
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		    case 0x2: /* V9 fmovd */
		    case 0x6: /* V9 fnegd */
		    case 0xa: /* V9 fabsd */
		    case 0x81: /* V9 fstox */
		    case 0x82: /* V9 fdtox */
		    case 0x84: /* V9 fxtos */
		    case 0x88: /* V9 fxtod */

		    case 0x3: /* V9 fmovq */
		    case 0x7: /* V9 fnegq */
		    case 0xb: /* V9 fabsq */
		    case 0x83: /* V9 fqtox */
		    case 0x8c: /* V9 fxtoq */
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                	goto illegal_insn;
		}
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	    } else if (xop == 0x35) {	/* FPU Operations */
#if !defined(CONFIG_USER_ONLY)
		gen_op_trap_ifnofpu();
#endif
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                rs1 = GET_FIELD(insn, 13, 17);
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	        rs2 = GET_FIELD(insn, 27, 31);
	        xop = GET_FIELD(insn, 18, 26);
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		/* V9 fmovscc: x5, cond = x >> 1 */
		/* V9 fmovdcc: x6, cond = x >> 1 */

		/* V9 fmovqcc: x7, cond = x >> 1 */
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		switch (xop) {
		    case 0x51:
                	gen_op_load_fpr_FT0(rs1);
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fcmps();
			break;
		    case 0x52:
                	gen_op_load_fpr_DT0(rs1);
                	gen_op_load_fpr_DT1(rs2);
			gen_op_fcmpd();
			break;
		    case 0x53: /* fcmpq */
		        goto nfpu_insn;
		    case 0x55: /* fcmpes */
                	gen_op_load_fpr_FT0(rs1);
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fcmps(); /* XXX should trap if qNaN or sNaN  */
			break;
		    case 0x56: /* fcmped */
                	gen_op_load_fpr_DT0(rs1);
                	gen_op_load_fpr_DT1(rs2);
			gen_op_fcmpd(); /* XXX should trap if qNaN or sNaN  */
			break;
		    case 0x57: /* fcmpeq */
		        goto nfpu_insn;
		    default:
                	goto illegal_insn;
		}
#if defined(OPTIM)
	    } else if (xop == 0x2) {
		// clr/mov shortcut

                rs1 = GET_FIELD(insn, 13, 17);
		if (rs1 == 0) {
		    // or %g0, x, y -> mov T1, x; mov y, T1
		    if (IS_IMM) {	/* immediate */
			rs2 = GET_FIELDs(insn, 19, 31);
			gen_movl_imm_T1(rs2);
		    } else {		/* register */
			rs2 = GET_FIELD(insn, 27, 31);
			gen_movl_reg_T1(rs2);
		    }
		    gen_movl_T1_reg(rd);
		} else {
		    gen_movl_reg_T0(rs1);
		    if (IS_IMM) {	/* immediate */
			// or x, #0, y -> mov T1, x; mov y, T1
			rs2 = GET_FIELDs(insn, 19, 31);
			if (rs2 != 0) {
			    gen_movl_imm_T1(rs2);
			    gen_op_or_T1_T0();
			}
		    } else {		/* register */
			// or x, %g0, y -> mov T1, x; mov y, T1
			rs2 = GET_FIELD(insn, 27, 31);
			if (rs2 != 0) {
			    gen_movl_reg_T1(rs2);
			    gen_op_or_T1_T0();
			}
		    }
		    gen_movl_T0_reg(rd);
		}
#endif
	    } else if (xop < 0x38) {
                rs1 = GET_FIELD(insn, 13, 17);
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