pci.c 68.9 KB
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/*
 * QEMU PCI bus manager
 *
 * Copyright (c) 2004 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
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#include "hw/hw.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci/pci_host.h"
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#include "monitor/monitor.h"
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#include "net/net.h"
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#include "sysemu/sysemu.h"
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#include "hw/loader.h"
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#include "qemu/range.h"
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#include "qmp-commands.h"
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#include "hw/pci/msi.h"
#include "hw/pci/msix.h"
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#include "exec/address-spaces.h"
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//#define DEBUG_PCI
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#ifdef DEBUG_PCI
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# define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
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#else
# define PCI_DPRINTF(format, ...)       do { } while (0)
#endif
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static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
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static char *pcibus_get_dev_path(DeviceState *dev);
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static char *pcibus_get_fw_dev_path(DeviceState *dev);
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static int pcibus_reset(BusState *qbus);
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static Property pci_props[] = {
    DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
    DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
    DEFINE_PROP_UINT32("rombar",  PCIDevice, rom_bar, 1),
    DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
                    QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
    DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
                    QEMU_PCI_CAP_SERR_BITNR, true),
    DEFINE_PROP_END_OF_LIST()
};

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static void pci_bus_class_init(ObjectClass *klass, void *data)
{
    BusClass *k = BUS_CLASS(klass);

    k->print_dev = pcibus_dev_print;
    k->get_dev_path = pcibus_get_dev_path;
    k->get_fw_dev_path = pcibus_get_fw_dev_path;
    k->reset = pcibus_reset;
}

static const TypeInfo pci_bus_info = {
    .name = TYPE_PCI_BUS,
    .parent = TYPE_BUS,
    .instance_size = sizeof(PCIBus),
    .class_init = pci_bus_class_init,
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};
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static const TypeInfo pcie_bus_info = {
    .name = TYPE_PCIE_BUS,
    .parent = TYPE_PCI_BUS,
};

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static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
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static void pci_update_mappings(PCIDevice *d);
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static void pci_set_irq(void *opaque, int irq_num, int level);
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static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
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static void pci_del_option_rom(PCIDevice *pdev);
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static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
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static QLIST_HEAD(, PCIHostState) pci_host_bridges;
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static const VMStateDescription vmstate_pcibus = {
    .name = "PCIBUS",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_INT32_EQUAL(nirq, PCIBus),
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        VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static int pci_bar(PCIDevice *d, int reg)
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{
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    uint8_t type;

    if (reg != PCI_ROM_SLOT)
        return PCI_BASE_ADDRESS_0 + reg * 4;

    type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
    return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
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}

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static inline int pci_irq_state(PCIDevice *d, int irq_num)
{
	return (d->irq_state >> irq_num) & 0x1;
}

static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
{
	d->irq_state &= ~(0x1 << irq_num);
	d->irq_state |= level << irq_num;
}

static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
{
    PCIBus *bus;
    for (;;) {
        bus = pci_dev->bus;
        irq_num = bus->map_irq(pci_dev, irq_num);
        if (bus->set_irq)
            break;
        pci_dev = bus->parent_dev;
    }
    bus->irq_count[irq_num] += change;
    bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
}

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int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
{
    assert(irq_num >= 0);
    assert(irq_num < bus->nirq);
    return !!bus->irq_count[irq_num];
}

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/* Update interrupt status bit in config space on interrupt
 * state change. */
static void pci_update_irq_status(PCIDevice *dev)
{
    if (dev->irq_state) {
        dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
    } else {
        dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
    }
}

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void pci_device_deassert_intx(PCIDevice *dev)
{
    int i;
    for (i = 0; i < PCI_NUM_PINS; ++i) {
        qemu_set_irq(dev->irq[i], 0);
    }
}

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/*
 * This function is called on #RST and FLR.
 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
 */
void pci_device_reset(PCIDevice *dev)
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{
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    int r;
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    qdev_reset_all(&dev->qdev);
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    dev->irq_state = 0;
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    pci_update_irq_status(dev);
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    pci_device_deassert_intx(dev);
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    /* Clear all writable bits */
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    pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
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                                 pci_get_word(dev->wmask + PCI_COMMAND) |
                                 pci_get_word(dev->w1cmask + PCI_COMMAND));
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    pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
                                 pci_get_word(dev->wmask + PCI_STATUS) |
                                 pci_get_word(dev->w1cmask + PCI_STATUS));
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    dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
    dev->config[PCI_INTERRUPT_LINE] = 0x0;
    for (r = 0; r < PCI_NUM_REGIONS; ++r) {
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        PCIIORegion *region = &dev->io_regions[r];
        if (!region->size) {
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            continue;
        }
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        if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
            region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
            pci_set_quad(dev->config + pci_bar(dev, r), region->type);
        } else {
            pci_set_long(dev->config + pci_bar(dev, r), region->type);
        }
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    }
    pci_update_mappings(dev);
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    msi_reset(dev);
    msix_reset(dev);
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}

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/*
 * Trigger pci bus reset under a given bus.
 * To be called on RST# assert.
 */
void pci_bus_reset(PCIBus *bus)
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{
    int i;

    for (i = 0; i < bus->nirq; i++) {
        bus->irq_count[i] = 0;
    }
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    for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
        if (bus->devices[i]) {
            pci_device_reset(bus->devices[i]);
        }
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    }
}

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static int pcibus_reset(BusState *qbus)
{
    pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));

    /* topology traverse is done by pci_bus_reset().
       Tell qbus/qdev walker not to traverse the tree */
    return 1;
}

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static void pci_host_bus_register(PCIBus *bus, DeviceState *parent)
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{
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    PCIHostState *host_bridge = PCI_HOST_BRIDGE(parent);

    QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
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}

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PCIBus *pci_find_primary_bus(void)
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{
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    PCIBus *primary_bus = NULL;
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    PCIHostState *host;
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    QLIST_FOREACH(host, &pci_host_bridges, next) {
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        if (primary_bus) {
            /* We have multiple root buses, refuse to select a primary */
            return NULL;
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        }
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        primary_bus = host->bus;
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    }

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    return primary_bus;
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}

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PCIBus *pci_device_root_bus(const PCIDevice *d)
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{
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    PCIBus *bus = d->bus;
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    while ((d = bus->parent_dev) != NULL) {
        bus = d->bus;
    }

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    return bus;
}

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const char *pci_root_bus_path(PCIDevice *dev)
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{
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    PCIBus *rootbus = pci_device_root_bus(dev);
    PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
    PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
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    assert(!rootbus->parent_dev);
    assert(host_bridge->bus == rootbus);

    if (hc->root_bus_path) {
        return (*hc->root_bus_path)(host_bridge, rootbus);
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    }

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    return rootbus->qbus.name;
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}

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static void pci_bus_init(PCIBus *bus, DeviceState *parent,
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                         const char *name,
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                         MemoryRegion *address_space_mem,
                         MemoryRegion *address_space_io,
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                         uint8_t devfn_min)
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{
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    assert(PCI_FUNC(devfn_min) == 0);
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    bus->devfn_min = devfn_min;
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    bus->address_space_mem = address_space_mem;
    bus->address_space_io = address_space_io;
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    /* host bridge */
    QLIST_INIT(&bus->child);
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    pci_host_bus_register(bus, parent);
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    vmstate_register(NULL, -1, &vmstate_pcibus, bus);
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}

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bool pci_bus_is_express(PCIBus *bus)
{
    return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
}

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bool pci_bus_is_root(PCIBus *bus)
{
    return !bus->parent_dev;
}

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void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
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                         const char *name,
                         MemoryRegion *address_space_mem,
                         MemoryRegion *address_space_io,
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                         uint8_t devfn_min, const char *typename)
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{
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    qbus_create_inplace(bus, bus_size, typename, parent, name);
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    pci_bus_init(bus, parent, name, address_space_mem,
                 address_space_io, devfn_min);
}

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PCIBus *pci_bus_new(DeviceState *parent, const char *name,
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                    MemoryRegion *address_space_mem,
                    MemoryRegion *address_space_io,
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                    uint8_t devfn_min, const char *typename)
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{
    PCIBus *bus;

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    bus = PCI_BUS(qbus_create(typename, parent, name));
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    pci_bus_init(bus, parent, name, address_space_mem,
                 address_space_io, devfn_min);
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    return bus;
}

void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
                  void *irq_opaque, int nirq)
{
    bus->set_irq = set_irq;
    bus->map_irq = map_irq;
    bus->irq_opaque = irq_opaque;
    bus->nirq = nirq;
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    bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
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}

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void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
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{
    bus->qbus.allow_hotplug = 1;
    bus->hotplug = hotplug;
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    bus->hotplug_qdev = qdev;
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}

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PCIBus *pci_register_bus(DeviceState *parent, const char *name,
                         pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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                         void *irq_opaque,
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                         MemoryRegion *address_space_mem,
                         MemoryRegion *address_space_io,
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                         uint8_t devfn_min, int nirq, const char *typename)
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{
    PCIBus *bus;

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    bus = pci_bus_new(parent, name, address_space_mem,
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                      address_space_io, devfn_min, typename);
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    pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
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    return bus;
}
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int pci_bus_num(PCIBus *s)
{
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    if (pci_bus_is_root(s))
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        return 0;       /* pci host bridge */
    return s->parent_dev->config[PCI_SECONDARY_BUS];
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}

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static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
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{
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    PCIDevice *s = container_of(pv, PCIDevice, config);
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    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
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    uint8_t *config;
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    int i;

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    assert(size == pci_config_size(s));
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    config = g_malloc(size);
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    qemu_get_buffer(f, config, size);
    for (i = 0; i < size; ++i) {
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        if ((config[i] ^ s->config[i]) &
            s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
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            g_free(config);
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            return -EINVAL;
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        }
    }
    memcpy(s->config, config, size);
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    pci_update_mappings(s);
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    if (pc->is_bridge) {
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        PCIBridge *b = PCI_BRIDGE(s);
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        pci_bridge_update_mappings(b);
    }
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    memory_region_set_enabled(&s->bus_master_enable_region,
                              pci_get_word(s->config + PCI_COMMAND)
                              & PCI_COMMAND_MASTER);

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    g_free(config);
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    return 0;
}

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/* just put buffer */
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static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
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{
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    const uint8_t **v = pv;
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    assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
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    qemu_put_buffer(f, *v, size);
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}

static VMStateInfo vmstate_info_pci_config = {
    .name = "pci config",
    .get  = get_pci_config_device,
    .put  = put_pci_config_device,
};

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static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
{
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    PCIDevice *s = container_of(pv, PCIDevice, irq_state);
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    uint32_t irq_state[PCI_NUM_PINS];
    int i;
    for (i = 0; i < PCI_NUM_PINS; ++i) {
        irq_state[i] = qemu_get_be32(f);
        if (irq_state[i] != 0x1 && irq_state[i] != 0) {
            fprintf(stderr, "irq state %d: must be 0 or 1.\n",
                    irq_state[i]);
            return -EINVAL;
        }
    }

    for (i = 0; i < PCI_NUM_PINS; ++i) {
        pci_set_irq_state(s, i, irq_state[i]);
    }

    return 0;
}

static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
{
    int i;
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    PCIDevice *s = container_of(pv, PCIDevice, irq_state);
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    for (i = 0; i < PCI_NUM_PINS; ++i) {
        qemu_put_be32(f, pci_irq_state(s, i));
    }
}

static VMStateInfo vmstate_info_pci_irq_state = {
    .name = "pci irq state",
    .get  = get_pci_irq_state,
    .put  = put_pci_irq_state,
};

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const VMStateDescription vmstate_pci_device = {
    .name = "PCIDevice",
    .version_id = 2,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_INT32_LE(version_id, PCIDevice),
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        VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
                                   vmstate_info_pci_config,
                                   PCI_CONFIG_SPACE_SIZE),
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        VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
				   vmstate_info_pci_irq_state,
				   PCI_NUM_PINS * sizeof(int32_t)),
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        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_pcie_device = {
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    .name = "PCIEDevice",
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    .version_id = 2,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_INT32_LE(version_id, PCIDevice),
        VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
                                   vmstate_info_pci_config,
                                   PCIE_CONFIG_SPACE_SIZE),
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        VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
				   vmstate_info_pci_irq_state,
				   PCI_NUM_PINS * sizeof(int32_t)),
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        VMSTATE_END_OF_LIST()
    }
};

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static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
{
    return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
}

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void pci_device_save(PCIDevice *s, QEMUFile *f)
{
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    /* Clear interrupt status bit: it is implicit
     * in irq_state which we are saving.
     * This makes us compatible with old devices
     * which never set or clear this bit. */
    s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
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    vmstate_save_state(f, pci_get_vmstate(s), s);
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    /* Restore the interrupt status bit. */
    pci_update_irq_status(s);
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}

int pci_device_load(PCIDevice *s, QEMUFile *f)
{
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    int ret;
    ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
    /* Restore the interrupt status bit. */
    pci_update_irq_status(s);
    return ret;
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}

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static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
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{
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    pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
                 pci_default_sub_vendor_id);
    pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
                 pci_default_sub_device_id);
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}

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/*
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 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
 *       [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
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 */
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int pci_parse_devaddr(const char *addr, int *domp, int *busp,
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                      unsigned int *slotp, unsigned int *funcp)
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{
    const char *p;
    char *e;
    unsigned long val;
    unsigned long dom = 0, bus = 0;
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    unsigned int slot = 0;
    unsigned int func = 0;
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    p = addr;
    val = strtoul(p, &e, 16);
    if (e == p)
	return -1;
    if (*e == ':') {
	bus = val;
	p = e + 1;
	val = strtoul(p, &e, 16);
	if (e == p)
	    return -1;
	if (*e == ':') {
	    dom = bus;
	    bus = val;
	    p = e + 1;
	    val = strtoul(p, &e, 16);
	    if (e == p)
		return -1;
	}
    }

    slot = val;

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    if (funcp != NULL) {
        if (*e != '.')
            return -1;

        p = e + 1;
        val = strtoul(p, &e, 16);
        if (e == p)
            return -1;

        func = val;
    }

    /* if funcp == NULL func is 0 */
    if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
	return -1;

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    if (*e)
	return -1;

    *domp = dom;
    *busp = bus;
    *slotp = slot;
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    if (funcp != NULL)
        *funcp = func;
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    return 0;
}

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PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr)
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{
    int dom, bus;
    unsigned slot;

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    assert(!root->parent_dev);

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    if (!root) {
        fprintf(stderr, "No primary PCI bus\n");
        return NULL;
    }

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    if (!devaddr) {
        *devfnp = -1;
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        return pci_find_bus_nr(root, 0);
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    }

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    if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
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        return NULL;
    }

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    if (dom != 0) {
        fprintf(stderr, "No support for non-zero PCI domains\n");
        return NULL;
    }

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    *devfnp = PCI_DEVFN(slot, 0);
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    return pci_find_bus_nr(root, bus);
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}

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static void pci_init_cmask(PCIDevice *dev)
{
    pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
    pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
    dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
    dev->cmask[PCI_REVISION_ID] = 0xff;
    dev->cmask[PCI_CLASS_PROG] = 0xff;
    pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
    dev->cmask[PCI_HEADER_TYPE] = 0xff;
    dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
}

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static void pci_init_wmask(PCIDevice *dev)
{
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    int config_size = pci_config_size(dev);

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    dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
    dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
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    pci_set_word(dev->wmask + PCI_COMMAND,
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                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
                 PCI_COMMAND_INTX_DISABLE);
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    if (dev->cap_present & QEMU_PCI_CAP_SERR) {
        pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
    }
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    memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
           config_size - PCI_CONFIG_HEADER_SIZE);
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}

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static void pci_init_w1cmask(PCIDevice *dev)
{
    /*
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     * Note: It's okay to set w1cmask even for readonly bits as
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     * long as their value is hardwired to 0.
     */
    pci_set_word(dev->w1cmask + PCI_STATUS,
                 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
}

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static void pci_init_mask_bridge(PCIDevice *d)
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{
    /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
       PCI_SEC_LETENCY_TIMER */
    memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);

    /* base and limit */
    d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
    d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
    pci_set_word(d->wmask + PCI_MEMORY_BASE,
                 PCI_MEMORY_RANGE_MASK & 0xffff);
    pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
                 PCI_MEMORY_RANGE_MASK & 0xffff);
    pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
                 PCI_PREF_RANGE_MASK & 0xffff);
    pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
                 PCI_PREF_RANGE_MASK & 0xffff);

    /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
    memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);

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    /* Supported memory and i/o types */
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    d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
    d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
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    pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
                               PCI_PREF_RANGE_TYPE_64);
    pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
                               PCI_PREF_RANGE_TYPE_64);

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    /*
     * TODO: Bridges default to 10-bit VGA decoding but we currently only
     * implement 16-bit decoding (no alias support).
     */
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    pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
                 PCI_BRIDGE_CTL_PARITY |
                 PCI_BRIDGE_CTL_SERR |
                 PCI_BRIDGE_CTL_ISA |
                 PCI_BRIDGE_CTL_VGA |
                 PCI_BRIDGE_CTL_VGA_16BIT |
                 PCI_BRIDGE_CTL_MASTER_ABORT |
                 PCI_BRIDGE_CTL_BUS_RESET |
                 PCI_BRIDGE_CTL_FAST_BACK |
                 PCI_BRIDGE_CTL_DISCARD |
                 PCI_BRIDGE_CTL_SEC_DISCARD |
                 PCI_BRIDGE_CTL_DISCARD_SERR);
    /* Below does not do anything as we never set this bit, put here for
     * completeness. */
    pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
                 PCI_BRIDGE_CTL_DISCARD_STATUS);
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    d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
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    d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
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    pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
                               PCI_PREF_RANGE_TYPE_MASK);
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    pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
                               PCI_PREF_RANGE_TYPE_MASK);
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}

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static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
{
    uint8_t slot = PCI_SLOT(dev->devfn);
    uint8_t func;

    if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
        dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
    }

    /*
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     * multifunction bit is interpreted in two ways as follows.
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     *   - all functions must set the bit to 1.
     *     Example: Intel X53
     *   - function 0 must set the bit, but the rest function (> 0)
     *     is allowed to leave the bit to 0.
     *     Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
     *
     * So OS (at least Linux) checks the bit of only function 0,
     * and doesn't see the bit of function > 0.
     *
     * The below check allows both interpretation.
     */
    if (PCI_FUNC(dev->devfn)) {
        PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
        if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
            /* function 0 should set multifunction bit */
            error_report("PCI: single function device can't be populated "
                         "in function %x.%x", slot, PCI_FUNC(dev->devfn));
            return -1;
        }
        return 0;
    }

    if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
        return 0;
    }
    /* function 0 indicates single function, so function > 0 must be NULL */
    for (func = 1; func < PCI_FUNC_MAX; ++func) {
        if (bus->devices[PCI_DEVFN(slot, func)]) {
            error_report("PCI: %x.0 indicates single function, "
                         "but %x.%x is already populated.",
                         slot, slot, func);
            return -1;
        }
    }
    return 0;
}

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static void pci_config_alloc(PCIDevice *pci_dev)
{
    int config_size = pci_config_size(pci_dev);

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    pci_dev->config = g_malloc0(config_size);
    pci_dev->cmask = g_malloc0(config_size);
    pci_dev->wmask = g_malloc0(config_size);
    pci_dev->w1cmask = g_malloc0(config_size);
    pci_dev->used = g_malloc0(config_size);
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}

static void pci_config_free(PCIDevice *pci_dev)
{
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    g_free(pci_dev->config);
    g_free(pci_dev->cmask);
    g_free(pci_dev->wmask);
    g_free(pci_dev->w1cmask);
    g_free(pci_dev->used);
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}

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/* -1 for devfn means auto assign */
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static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
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                                         const char *name, int devfn)
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{
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    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
    PCIConfigReadFunc *config_read = pc->config_read;
    PCIConfigWriteFunc *config_write = pc->config_write;
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    AddressSpace *dma_as;
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    if (devfn < 0) {
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        for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
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            devfn += PCI_FUNC_MAX) {
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            if (!bus->devices[devfn])
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                goto found;
        }
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        error_report("PCI: no slot/function available for %s, all in use", name);
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        return NULL;
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    found: ;
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    } else if (bus->devices[devfn]) {
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        error_report("PCI: slot %d function %d not available for %s, in use by %s",
                     PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
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        return NULL;
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    }
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    pci_dev->bus = bus;
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    dma_as = pci_device_iommu_address_space(pci_dev);
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    memory_region_init_alias(&pci_dev->bus_master_enable_region,
                             OBJECT(pci_dev), "bus master",
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                             dma_as->root, 0, memory_region_size(dma_as->root));
    memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
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    address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region,
                       name);
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    pci_dev->devfn = devfn;
    pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
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    pci_dev->irq_state = 0;
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    pci_config_alloc(pci_dev);
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    pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
    pci_config_set_device_id(pci_dev->config, pc->device_id);
    pci_config_set_revision(pci_dev->config, pc->revision);
    pci_config_set_class(pci_dev->config, pc->class_id);
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    if (!pc->is_bridge) {
        if (pc->subsystem_vendor_id || pc->subsystem_id) {
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            pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
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                         pc->subsystem_vendor_id);
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            pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
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                         pc->subsystem_id);
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        } else {
            pci_set_default_subsystem_id(pci_dev);
        }
    } else {
        /* subsystem_vendor_id/subsystem_id are only for header type 0 */
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        assert(!pc->subsystem_vendor_id);
        assert(!pc->subsystem_id);
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    }
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    pci_init_cmask(pci_dev);
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    pci_init_wmask(pci_dev);
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    pci_init_w1cmask(pci_dev);
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    if (pc->is_bridge) {
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        pci_init_mask_bridge(pci_dev);
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    }
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    if (pci_init_multifunction(bus, pci_dev)) {
        pci_config_free(pci_dev);
        return NULL;
    }
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    if (!config_read)
        config_read = pci_default_read_config;
    if (!config_write)
        config_write = pci_default_write_config;
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    pci_dev->config_read = config_read;
    pci_dev->config_write = config_write;
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    bus->devices[devfn] = pci_dev;
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    pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
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    pci_dev->version_id = 2; /* Current pci device vmstate version */
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    return pci_dev;
}

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static void do_pci_unregister_device(PCIDevice *pci_dev)
{
    qemu_free_irqs(pci_dev->irq);
    pci_dev->bus->devices[pci_dev->devfn] = NULL;
    pci_config_free(pci_dev);
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    address_space_destroy(&pci_dev->bus_master_as);
    memory_region_destroy(&pci_dev->bus_master_enable_region);
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}

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static void pci_unregister_io_regions(PCIDevice *pci_dev)
{
    PCIIORegion *r;
    int i;

    for(i = 0; i < PCI_NUM_REGIONS; i++) {
        r = &pci_dev->io_regions[i];
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        if (!r->size || r->addr == PCI_BAR_UNMAPPED)
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            continue;
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        memory_region_del_subregion(r->address_space, r->memory);
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    }
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    pci_unregister_vga(pci_dev);
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}

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static int pci_unregister_device(DeviceState *dev)
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{
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    PCIDevice *pci_dev = PCI_DEVICE(dev);
    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
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    pci_unregister_io_regions(pci_dev);
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    pci_del_option_rom(pci_dev);
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    if (pc->exit) {
        pc->exit(pci_dev);
    }
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    do_pci_unregister_device(pci_dev);
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    return 0;
}

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void pci_register_bar(PCIDevice *pci_dev, int region_num,
                      uint8_t type, MemoryRegion *memory)
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{
    PCIIORegion *r;
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    uint32_t addr;
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    uint64_t wmask;
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    pcibus_t size = memory_region_size(memory);
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    assert(region_num >= 0);
    assert(region_num < PCI_NUM_REGIONS);
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    if (size & (size-1)) {
        fprintf(stderr, "ERROR: PCI region size must be pow2 "
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                    "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
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        exit(1);
    }

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    r = &pci_dev->io_regions[region_num];
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    r->addr = PCI_BAR_UNMAPPED;
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    r->size = size;
    r->type = type;
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    r->memory = NULL;
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    wmask = ~(size - 1);
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    addr = pci_bar(pci_dev, region_num);
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    if (region_num == PCI_ROM_SLOT) {
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        /* ROM enable bit is writable */
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        wmask |= PCI_ROM_ADDRESS_ENABLE;
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    }
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    pci_set_long(pci_dev->config + addr, type);
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    if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
        r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
        pci_set_quad(pci_dev->wmask + addr, wmask);
        pci_set_quad(pci_dev->cmask + addr, ~0ULL);
    } else {
        pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
        pci_set_long(pci_dev->cmask + addr, 0xffffffff);
    }
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    pci_dev->io_regions[region_num].memory = memory;
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    pci_dev->io_regions[region_num].address_space
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        = type & PCI_BASE_ADDRESS_SPACE_IO
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        ? pci_dev->bus->address_space_io
        : pci_dev->bus->address_space_mem;
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}

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static void pci_update_vga(PCIDevice *pci_dev)
{
    uint16_t cmd;

    if (!pci_dev->has_vga) {
        return;
    }

    cmd = pci_get_word(pci_dev->config + PCI_COMMAND);

    memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
                              cmd & PCI_COMMAND_MEMORY);
    memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
                              cmd & PCI_COMMAND_IO);
    memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
                              cmd & PCI_COMMAND_IO);
}

void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
                      MemoryRegion *io_lo, MemoryRegion *io_hi)
{
    assert(!pci_dev->has_vga);

    assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
    pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
    memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem,
                                        QEMU_PCI_VGA_MEM_BASE, mem, 1);

    assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
    pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
    memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
                                        QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);

    assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
    pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
    memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
                                        QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
    pci_dev->has_vga = true;

    pci_update_vga(pci_dev);
}

void pci_unregister_vga(PCIDevice *pci_dev)
{
    if (!pci_dev->has_vga) {
        return;
    }

    memory_region_del_subregion(pci_dev->bus->address_space_mem,
                                pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
    memory_region_del_subregion(pci_dev->bus->address_space_io,
                                pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
    memory_region_del_subregion(pci_dev->bus->address_space_io,
                                pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
    pci_dev->has_vga = false;
}

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pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
{
    return pci_dev->io_regions[region_num].addr;
}

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static pcibus_t pci_bar_address(PCIDevice *d,
				int reg, uint8_t type, pcibus_t size)
{
    pcibus_t new_addr, last_addr;
    int bar = pci_bar(d, reg);
    uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);

    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
        if (!(cmd & PCI_COMMAND_IO)) {
            return PCI_BAR_UNMAPPED;
        }
        new_addr = pci_get_long(d->config + bar) & ~(size - 1);
        last_addr = new_addr + size - 1;
1031
1032
1033
1034
        /* Check if 32 bit BAR wraps around explicitly.
         * TODO: make priorities correct and remove this work around.
         */
        if (last_addr <= new_addr || new_addr == 0 || last_addr >= UINT32_MAX) {
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
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1055
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1062
1063
1064
1065
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1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
            return PCI_BAR_UNMAPPED;
        }
        return new_addr;
    }

    if (!(cmd & PCI_COMMAND_MEMORY)) {
        return PCI_BAR_UNMAPPED;
    }
    if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
        new_addr = pci_get_quad(d->config + bar);
    } else {
        new_addr = pci_get_long(d->config + bar);
    }
    /* the ROM slot has a specific enable bit */
    if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
        return PCI_BAR_UNMAPPED;
    }
    new_addr &= ~(size - 1);
    last_addr = new_addr + size - 1;
    /* NOTE: we do not support wrapping */
    /* XXX: as we cannot support really dynamic
       mappings, we handle specific values as invalid
       mappings. */
    if (last_addr <= new_addr || new_addr == 0 ||
        last_addr == PCI_BAR_UNMAPPED) {
        return PCI_BAR_UNMAPPED;
    }

    /* Now pcibus_t is 64bit.
     * Check if 32 bit BAR wraps around explicitly.
     * Without this, PC ide doesn't work well.
     * TODO: remove this work around.
     */
    if  (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
        return PCI_BAR_UNMAPPED;
    }

    /*
     * OS is allowed to set BAR beyond its addressable
     * bits. For example, 32 bit OS can set 64bit bar
     * to >4G. Check it. TODO: we might need to support
     * it in the future for e.g. PAE.
     */
1078
    if (last_addr >= HWADDR_MAX) {
1079
1080
1081
1082
1083
1084
        return PCI_BAR_UNMAPPED;
    }

    return new_addr;
}

1085
1086
1087
static void pci_update_mappings(PCIDevice *d)
{
    PCIIORegion *r;
1088
    int i;
1089
    pcibus_t new_addr;
1090

1091
    for(i = 0; i < PCI_NUM_REGIONS; i++) {
1092
        r = &d->io_regions[i];
1093
1094

        /* this region isn't registered */
1095
        if (!r->size)