helper.c 41.4 KB
Newer Older
1 2
/*
 *  sparc helpers
3
 *
bellard's avatar
bellard committed
4
 *  Copyright (c) 2003-2005 Fabrice Bellard
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
20 21 22 23 24 25 26 27 28 29
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include <assert.h>

#include "cpu.h"
#include "exec-all.h"
30
#include "qemu-common.h"
31

bellard's avatar
bellard committed
32
//#define DEBUG_MMU
blueswir1's avatar
blueswir1 committed
33
//#define DEBUG_FEATURES
34

35 36 37 38 39 40 41 42 43 44 45 46
typedef struct sparc_def_t sparc_def_t;

struct sparc_def_t {
    const unsigned char *name;
    target_ulong iu_version;
    uint32_t fpu_version;
    uint32_t mmu_version;
    uint32_t mmu_bm;
    uint32_t mmu_ctpr_mask;
    uint32_t mmu_cxr_mask;
    uint32_t mmu_sfsr_mask;
    uint32_t mmu_trcr_mask;
blueswir1's avatar
blueswir1 committed
47
    uint32_t features;
48 49
};

blueswir1's avatar
blueswir1 committed
50
static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const unsigned char *cpu_model);
51

52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67
/* Sparc MMU emulation */

/* thread support */

spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;

void cpu_lock(void)
{
    spin_lock(&global_cpu_lock);
}

void cpu_unlock(void)
{
    spin_unlock(&global_cpu_lock);
}

68
#if defined(CONFIG_USER_ONLY)
bellard's avatar
bellard committed
69 70

int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
71
                               int mmu_idx, int is_softmmu)
bellard's avatar
bellard committed
72
{
bellard's avatar
bellard committed
73 74 75 76
    if (rw & 2)
        env->exception_index = TT_TFAULT;
    else
        env->exception_index = TT_DFAULT;
bellard's avatar
bellard committed
77 78 79 80
    return 1;
}

#else
81

bellard's avatar
bellard committed
82
#ifndef TARGET_SPARC64
bellard's avatar
bellard committed
83 84 85
/*
 * Sparc V8 Reference MMU (SRMMU)
 */
86 87 88 89 90 91 92 93 94 95 96
static const int access_table[8][8] = {
    { 0, 0, 0, 0, 2, 0, 3, 3 },
    { 0, 0, 0, 0, 2, 0, 0, 0 },
    { 2, 2, 0, 0, 0, 2, 3, 3 },
    { 2, 2, 0, 0, 0, 2, 0, 0 },
    { 2, 0, 2, 0, 2, 2, 3, 3 },
    { 2, 0, 2, 0, 2, 0, 2, 0 },
    { 2, 2, 2, 0, 2, 2, 3, 3 },
    { 2, 2, 2, 0, 2, 2, 2, 0 }
};

bellard's avatar
bellard committed
97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117
static const int perm_table[2][8] = {
    {
        PAGE_READ,
        PAGE_READ | PAGE_WRITE,
        PAGE_READ | PAGE_EXEC,
        PAGE_READ | PAGE_WRITE | PAGE_EXEC,
        PAGE_EXEC,
        PAGE_READ | PAGE_WRITE,
        PAGE_READ | PAGE_EXEC,
        PAGE_READ | PAGE_WRITE | PAGE_EXEC
    },
    {
        PAGE_READ,
        PAGE_READ | PAGE_WRITE,
        PAGE_READ | PAGE_EXEC,
        PAGE_READ | PAGE_WRITE | PAGE_EXEC,
        PAGE_EXEC,
        PAGE_READ,
        0,
        0,
    }
118 119
};

120 121 122
static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
                                int *prot, int *access_index,
                                target_ulong address, int rw, int mmu_idx)
123
{
bellard's avatar
bellard committed
124 125
    int access_perms = 0;
    target_phys_addr_t pde_ptr;
126 127
    uint32_t pde;
    target_ulong virt_addr;
128
    int error_code = 0, is_dirty, is_user;
bellard's avatar
bellard committed
129
    unsigned long page_offset;
130

131
    is_user = mmu_idx == MMU_USER_IDX;
132
    virt_addr = address & TARGET_PAGE_MASK;
blueswir1's avatar
blueswir1 committed
133

134
    if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
blueswir1's avatar
blueswir1 committed
135
        // Boot mode: instruction fetches are taken from PROM
136
        if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) {
blueswir1's avatar
blueswir1 committed
137
            *physical = env->prom_addr | (address & 0x7ffffULL);
blueswir1's avatar
blueswir1 committed
138 139 140
            *prot = PAGE_READ | PAGE_EXEC;
            return 0;
        }
blueswir1's avatar
blueswir1 committed
141
        *physical = address;
bellard's avatar
bellard committed
142
        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
bellard's avatar
bellard committed
143
        return 0;
144 145
    }

bellard's avatar
bellard committed
146
    *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
147
    *physical = 0xffffffffffff0000ULL;
bellard's avatar
bellard committed
148

149 150
    /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
    /* Context base + context number */
151
    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
bellard's avatar
bellard committed
152
    pde = ldl_phys(pde_ptr);
153 154 155

    /* Ctx pde */
    switch (pde & PTE_ENTRYTYPE_MASK) {
bellard's avatar
bellard committed
156
    default:
157
    case 0: /* Invalid */
blueswir1's avatar
blueswir1 committed
158
        return 1 << 2;
bellard's avatar
bellard committed
159
    case 2: /* L0 PTE, maybe should not happen? */
160
    case 3: /* Reserved */
bellard's avatar
bellard committed
161
        return 4 << 2;
bellard's avatar
bellard committed
162
    case 1: /* L0 PDE */
blueswir1's avatar
blueswir1 committed
163
        pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
bellard's avatar
bellard committed
164
        pde = ldl_phys(pde_ptr);
165

blueswir1's avatar
blueswir1 committed
166 167 168 169 170 171 172 173
        switch (pde & PTE_ENTRYTYPE_MASK) {
        default:
        case 0: /* Invalid */
            return (1 << 8) | (1 << 2);
        case 3: /* Reserved */
            return (1 << 8) | (4 << 2);
        case 1: /* L1 PDE */
            pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
bellard's avatar
bellard committed
174
            pde = ldl_phys(pde_ptr);
175

blueswir1's avatar
blueswir1 committed
176 177 178 179 180 181 182 183
            switch (pde & PTE_ENTRYTYPE_MASK) {
            default:
            case 0: /* Invalid */
                return (2 << 8) | (1 << 2);
            case 3: /* Reserved */
                return (2 << 8) | (4 << 2);
            case 1: /* L2 PDE */
                pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
bellard's avatar
bellard committed
184
                pde = ldl_phys(pde_ptr);
185

blueswir1's avatar
blueswir1 committed
186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206
                switch (pde & PTE_ENTRYTYPE_MASK) {
                default:
                case 0: /* Invalid */
                    return (3 << 8) | (1 << 2);
                case 1: /* PDE, should not happen */
                case 3: /* Reserved */
                    return (3 << 8) | (4 << 2);
                case 2: /* L3 PTE */
                    virt_addr = address & TARGET_PAGE_MASK;
                    page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
                }
                break;
            case 2: /* L2 PTE */
                virt_addr = address & ~0x3ffff;
                page_offset = address & 0x3ffff;
            }
            break;
        case 2: /* L1 PTE */
            virt_addr = address & ~0xffffff;
            page_offset = address & 0xffffff;
        }
207 208 209
    }

    /* update page modified and dirty bits */
bellard's avatar
bellard committed
210
    is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
211
    if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
blueswir1's avatar
blueswir1 committed
212 213 214
        pde |= PG_ACCESSED_MASK;
        if (is_dirty)
            pde |= PG_MODIFIED_MASK;
bellard's avatar
bellard committed
215
        stl_phys_notdirty(pde_ptr, pde);
216 217 218
    }
    /* check access */
    access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
bellard's avatar
bellard committed
219
    error_code = access_table[*access_index][access_perms];
bellard's avatar
bellard committed
220
    if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
blueswir1's avatar
blueswir1 committed
221
        return error_code;
222 223

    /* the page can be put in the TLB */
bellard's avatar
bellard committed
224 225
    *prot = perm_table[is_user][access_perms];
    if (!(pde & PG_MODIFIED_MASK)) {
226 227
        /* only set write access if already dirty... otherwise wait
           for dirty access */
bellard's avatar
bellard committed
228
        *prot &= ~PAGE_WRITE;
229 230 231 232
    }

    /* Even if large ptes, we map only one 4KB page in the cache to
       avoid filling it too fast */
233
    *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
bellard's avatar
bellard committed
234
    return error_code;
bellard's avatar
bellard committed
235 236 237
}

/* Perform address translation */
238
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
239
                              int mmu_idx, int is_softmmu)
bellard's avatar
bellard committed
240
{
241
    target_phys_addr_t paddr;
242
    target_ulong vaddr;
bellard's avatar
bellard committed
243
    int error_code = 0, prot, ret = 0, access_index;
244

245
    error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx);
bellard's avatar
bellard committed
246
    if (error_code == 0) {
blueswir1's avatar
blueswir1 committed
247 248
        vaddr = address & TARGET_PAGE_MASK;
        paddr &= TARGET_PAGE_MASK;
bellard's avatar
bellard committed
249
#ifdef DEBUG_MMU
blueswir1's avatar
blueswir1 committed
250
        printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
251
               TARGET_FMT_lx "\n", address, paddr, vaddr);
bellard's avatar
bellard committed
252
#endif
253
        ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
blueswir1's avatar
blueswir1 committed
254
        return ret;
bellard's avatar
bellard committed
255
    }
256 257

    if (env->mmuregs[3]) /* Fault status register */
blueswir1's avatar
blueswir1 committed
258
        env->mmuregs[3] = 1; /* overflow (not read before another fault) */
bellard's avatar
bellard committed
259
    env->mmuregs[3] |= (access_index << 5) | error_code | 2;
260 261
    env->mmuregs[4] = address; /* Fault address register */

bellard's avatar
bellard committed
262
    if ((env->mmuregs[0] & MMU_NF) || env->psret == 0)  {
bellard's avatar
bellard committed
263 264 265 266
        // No fault mode: if a mapping is available, just override
        // permissions. If no mapping is available, redirect accesses to
        // neverland. Fake/overridden mappings will be flushed when
        // switching to normal mode.
blueswir1's avatar
blueswir1 committed
267
        vaddr = address & TARGET_PAGE_MASK;
bellard's avatar
bellard committed
268
        prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
269
        ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
blueswir1's avatar
blueswir1 committed
270
        return ret;
bellard's avatar
bellard committed
271 272 273 274 275 276
    } else {
        if (rw & 2)
            env->exception_index = TT_TFAULT;
        else
            env->exception_index = TT_DFAULT;
        return 1;
bellard's avatar
bellard committed
277
    }
278
}
279 280 281 282 283 284 285

target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
{
    target_phys_addr_t pde_ptr;
    uint32_t pde;

    /* Context base + context number */
286 287
    pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
        (env->mmuregs[2] << 2);
288 289 290 291 292 293 294
    pde = ldl_phys(pde_ptr);

    switch (pde & PTE_ENTRYTYPE_MASK) {
    default:
    case 0: /* Invalid */
    case 2: /* PTE, maybe should not happen? */
    case 3: /* Reserved */
blueswir1's avatar
blueswir1 committed
295
        return 0;
296
    case 1: /* L1 PDE */
blueswir1's avatar
blueswir1 committed
297 298 299
        if (mmulev == 3)
            return pde;
        pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
300 301
        pde = ldl_phys(pde_ptr);

blueswir1's avatar
blueswir1 committed
302 303 304 305 306 307 308 309 310 311 312
        switch (pde & PTE_ENTRYTYPE_MASK) {
        default:
        case 0: /* Invalid */
        case 3: /* Reserved */
            return 0;
        case 2: /* L1 PTE */
            return pde;
        case 1: /* L2 PDE */
            if (mmulev == 2)
                return pde;
            pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
313 314
            pde = ldl_phys(pde_ptr);

blueswir1's avatar
blueswir1 committed
315 316 317 318 319 320 321 322 323 324 325
            switch (pde & PTE_ENTRYTYPE_MASK) {
            default:
            case 0: /* Invalid */
            case 3: /* Reserved */
                return 0;
            case 2: /* L2 PTE */
                return pde;
            case 1: /* L3 PDE */
                if (mmulev == 1)
                    return pde;
                pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
326 327
                pde = ldl_phys(pde_ptr);

blueswir1's avatar
blueswir1 committed
328 329 330 331 332 333 334 335 336 337 338
                switch (pde & PTE_ENTRYTYPE_MASK) {
                default:
                case 0: /* Invalid */
                case 1: /* PDE, should not happen */
                case 3: /* Reserved */
                    return 0;
                case 2: /* L3 PTE */
                    return pde;
                }
            }
        }
339 340 341 342 343 344 345
    }
    return 0;
}

#ifdef DEBUG_MMU
void dump_mmu(CPUState *env)
{
346 347 348
    target_ulong va, va1, va2;
    unsigned int n, m, o;
    target_phys_addr_t pde_ptr, pa;
349 350 351 352 353
    uint32_t pde;

    printf("MMU dump:\n");
    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
    pde = ldl_phys(pde_ptr);
354 355
    printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
           (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
356
    for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
blueswir1's avatar
blueswir1 committed
357 358 359 360
        pde = mmu_probe(env, va, 2);
        if (pde) {
            pa = cpu_get_phys_page_debug(env, va);
            printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
361
                   " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
blueswir1's avatar
blueswir1 committed
362 363 364 365 366
            for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
                pde = mmu_probe(env, va1, 1);
                if (pde) {
                    pa = cpu_get_phys_page_debug(env, va1);
                    printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
367
                           " PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
blueswir1's avatar
blueswir1 committed
368 369 370 371 372
                    for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
                        pde = mmu_probe(env, va2, 0);
                        if (pde) {
                            pa = cpu_get_phys_page_debug(env, va2);
                            printf("  VA: " TARGET_FMT_lx ", PA: "
373 374
                                   TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
                                   va2, pa, pde);
blueswir1's avatar
blueswir1 committed
375 376 377 378 379
                        }
                    }
                }
            }
        }
380 381 382 383 384 385
    }
    printf("MMU dump ends\n");
}
#endif /* DEBUG_MMU */

#else /* !TARGET_SPARC64 */
bellard's avatar
bellard committed
386 387 388
/*
 * UltraSparc IIi I/DMMUs
 */
bellard's avatar
bellard committed
389
static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,
blueswir1's avatar
blueswir1 committed
390 391
                          int *access_index, target_ulong address, int rw,
                          int is_user)
bellard's avatar
bellard committed
392 393 394 395 396
{
    target_ulong mask;
    unsigned int i;

    if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
blueswir1's avatar
blueswir1 committed
397 398
        *physical = address;
        *prot = PAGE_READ | PAGE_WRITE;
bellard's avatar
bellard committed
399 400 401 402
        return 0;
    }

    for (i = 0; i < 64; i++) {
blueswir1's avatar
blueswir1 committed
403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429
        switch ((env->dtlb_tte[i] >> 61) & 3) {
        default:
        case 0x0: // 8k
            mask = 0xffffffffffffe000ULL;
            break;
        case 0x1: // 64k
            mask = 0xffffffffffff0000ULL;
            break;
        case 0x2: // 512k
            mask = 0xfffffffffff80000ULL;
            break;
        case 0x3: // 4M
            mask = 0xffffffffffc00000ULL;
            break;
        }
        // ctx match, vaddr match?
        if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
            (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
            // valid, access ok?
            if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
                ((env->dtlb_tte[i] & 0x4) && is_user) ||
                (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
                if (env->dmmuregs[3]) /* Fault status register */
                    env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
                env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
                env->dmmuregs[4] = address; /* Fault address register */
                env->exception_index = TT_DFAULT;
bellard's avatar
bellard committed
430
#ifdef DEBUG_MMU
blueswir1's avatar
blueswir1 committed
431
                printf("DFAULT at 0x%" PRIx64 "\n", address);
bellard's avatar
bellard committed
432
#endif
blueswir1's avatar
blueswir1 committed
433 434 435 436 437 438 439 440
                return 1;
            }
            *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
            *prot = PAGE_READ;
            if (env->dtlb_tte[i] & 0x2)
                *prot |= PAGE_WRITE;
            return 0;
        }
bellard's avatar
bellard committed
441
    }
bellard's avatar
bellard committed
442
#ifdef DEBUG_MMU
bellard's avatar
bellard committed
443
    printf("DMISS at 0x%" PRIx64 "\n", address);
bellard's avatar
bellard committed
444 445
#endif
    env->exception_index = TT_DMISS;
bellard's avatar
bellard committed
446 447 448 449
    return 1;
}

static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,
blueswir1's avatar
blueswir1 committed
450 451
                          int *access_index, target_ulong address, int rw,
                          int is_user)
bellard's avatar
bellard committed
452 453 454 455 456
{
    target_ulong mask;
    unsigned int i;

    if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
blueswir1's avatar
blueswir1 committed
457 458
        *physical = address;
        *prot = PAGE_EXEC;
bellard's avatar
bellard committed
459 460
        return 0;
    }
bellard's avatar
bellard committed
461

bellard's avatar
bellard committed
462
    for (i = 0; i < 64; i++) {
blueswir1's avatar
blueswir1 committed
463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487
        switch ((env->itlb_tte[i] >> 61) & 3) {
        default:
        case 0x0: // 8k
            mask = 0xffffffffffffe000ULL;
            break;
        case 0x1: // 64k
            mask = 0xffffffffffff0000ULL;
            break;
        case 0x2: // 512k
            mask = 0xfffffffffff80000ULL;
            break;
        case 0x3: // 4M
            mask = 0xffffffffffc00000ULL;
                break;
        }
        // ctx match, vaddr match?
        if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
            (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
            // valid, access ok?
            if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
                ((env->itlb_tte[i] & 0x4) && is_user)) {
                if (env->immuregs[3]) /* Fault status register */
                    env->immuregs[3] = 2; /* overflow (not read before another fault) */
                env->immuregs[3] |= (is_user << 3) | 1;
                env->exception_index = TT_TFAULT;
bellard's avatar
bellard committed
488
#ifdef DEBUG_MMU
blueswir1's avatar
blueswir1 committed
489
                printf("TFAULT at 0x%" PRIx64 "\n", address);
bellard's avatar
bellard committed
490
#endif
blueswir1's avatar
blueswir1 committed
491 492 493 494 495 496
                return 1;
            }
            *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
            *prot = PAGE_EXEC;
            return 0;
        }
bellard's avatar
bellard committed
497
    }
bellard's avatar
bellard committed
498
#ifdef DEBUG_MMU
bellard's avatar
bellard committed
499
    printf("TMISS at 0x%" PRIx64 "\n", address);
bellard's avatar
bellard committed
500 501
#endif
    env->exception_index = TT_TMISS;
bellard's avatar
bellard committed
502 503 504
    return 1;
}

505 506 507
static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
                                int *prot, int *access_index,
                                target_ulong address, int rw, int mmu_idx)
bellard's avatar
bellard committed
508
{
509 510
    int is_user = mmu_idx == MMU_USER_IDX;

bellard's avatar
bellard committed
511
    if (rw == 2)
blueswir1's avatar
blueswir1 committed
512
        return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
bellard's avatar
bellard committed
513
    else
blueswir1's avatar
blueswir1 committed
514
        return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
bellard's avatar
bellard committed
515 516 517 518
}

/* Perform address translation */
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
519
                              int mmu_idx, int is_softmmu)
bellard's avatar
bellard committed
520
{
bellard's avatar
bellard committed
521
    target_ulong virt_addr, vaddr;
bellard's avatar
bellard committed
522 523 524
    target_phys_addr_t paddr;
    int error_code = 0, prot, ret = 0, access_index;

525
    error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx);
bellard's avatar
bellard committed
526
    if (error_code == 0) {
blueswir1's avatar
blueswir1 committed
527 528
        virt_addr = address & TARGET_PAGE_MASK;
        vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
bellard's avatar
bellard committed
529
#ifdef DEBUG_MMU
blueswir1's avatar
blueswir1 committed
530
        printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
bellard's avatar
bellard committed
531
#endif
532
        ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
blueswir1's avatar
blueswir1 committed
533
        return ret;
bellard's avatar
bellard committed
534 535 536 537 538
    }
    // XXX
    return 1;
}

bellard's avatar
bellard committed
539 540 541 542 543 544
#ifdef DEBUG_MMU
void dump_mmu(CPUState *env)
{
    unsigned int i;
    const char *mask;

bellard's avatar
bellard committed
545
    printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]);
bellard's avatar
bellard committed
546
    if ((env->lsu & DMMU_E) == 0) {
blueswir1's avatar
blueswir1 committed
547
        printf("DMMU disabled\n");
bellard's avatar
bellard committed
548
    } else {
blueswir1's avatar
blueswir1 committed
549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576
        printf("DMMU dump:\n");
        for (i = 0; i < 64; i++) {
            switch ((env->dtlb_tte[i] >> 61) & 3) {
            default:
            case 0x0:
                mask = "  8k";
                break;
            case 0x1:
                mask = " 64k";
                break;
            case 0x2:
                mask = "512k";
                break;
            case 0x3:
                mask = "  4M";
                break;
            }
            if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
                printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
                       env->dtlb_tag[i] & ~0x1fffULL,
                       env->dtlb_tte[i] & 0x1ffffffe000ULL,
                       mask,
                       env->dtlb_tte[i] & 0x4? "priv": "user",
                       env->dtlb_tte[i] & 0x2? "RW": "RO",
                       env->dtlb_tte[i] & 0x40? "locked": "unlocked",
                       env->dtlb_tag[i] & 0x1fffULL);
            }
        }
bellard's avatar
bellard committed
577 578
    }
    if ((env->lsu & IMMU_E) == 0) {
blueswir1's avatar
blueswir1 committed
579
        printf("IMMU disabled\n");
bellard's avatar
bellard committed
580
    } else {
blueswir1's avatar
blueswir1 committed
581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607
        printf("IMMU dump:\n");
        for (i = 0; i < 64; i++) {
            switch ((env->itlb_tte[i] >> 61) & 3) {
            default:
            case 0x0:
                mask = "  8k";
                break;
            case 0x1:
                mask = " 64k";
                break;
            case 0x2:
                mask = "512k";
                break;
            case 0x3:
                mask = "  4M";
                break;
            }
            if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
                printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
                       env->itlb_tag[i] & ~0x1fffULL,
                       env->itlb_tte[i] & 0x1ffffffe000ULL,
                       mask,
                       env->itlb_tte[i] & 0x4? "priv": "user",
                       env->itlb_tte[i] & 0x40? "locked": "unlocked",
                       env->itlb_tag[i] & 0x1fffULL);
            }
        }
bellard's avatar
bellard committed
608 609
    }
}
610 611 612 613 614
#endif /* DEBUG_MMU */

#endif /* TARGET_SPARC64 */
#endif /* !CONFIG_USER_ONLY */

615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638

#if defined(CONFIG_USER_ONLY)
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
    return addr;
}

#else
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
    target_phys_addr_t phys_addr;
    int prot, access_index;

    if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
                             MMU_KERNEL_IDX) != 0)
        if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
                                 0, MMU_KERNEL_IDX) != 0)
            return -1;
    if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
        return -1;
    return phys_addr;
}
#endif

639 640 641 642 643 644 645 646 647 648 649
void memcpy32(target_ulong *dst, const target_ulong *src)
{
    dst[0] = src[0];
    dst[1] = src[1];
    dst[2] = src[2];
    dst[3] = src[3];
    dst[4] = src[4];
    dst[5] = src[5];
    dst[6] = src[6];
    dst[7] = src[7];
}
pbrook's avatar
pbrook committed
650

651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688
void helper_flush(target_ulong addr)
{
    addr &= ~7;
    tb_invalidate_page_range(addr, addr + 8);
}

void cpu_reset(CPUSPARCState *env)
{
    tlb_flush(env, 1);
    env->cwp = 0;
    env->wim = 1;
    env->regwptr = env->regbase + (env->cwp * 16);
#if defined(CONFIG_USER_ONLY)
    env->user_mode_only = 1;
#ifdef TARGET_SPARC64
    env->cleanwin = NWINDOWS - 2;
    env->cansave = NWINDOWS - 2;
    env->pstate = PS_RMO | PS_PEF | PS_IE;
    env->asi = 0x82; // Primary no-fault
#endif
#else
    env->psret = 0;
    env->psrs = 1;
    env->psrps = 1;
#ifdef TARGET_SPARC64
    env->pstate = PS_PRIV;
    env->hpstate = HS_PRIV;
    env->pc = 0x1fff0000000ULL;
    env->tsptr = &env->ts[env->tl];
#else
    env->pc = 0;
    env->mmuregs[0] &= ~(MMU_E | MMU_NF);
    env->mmuregs[0] |= env->mmu_bm;
#endif
    env->npc = env->pc + 4;
#endif
}

blueswir1's avatar
blueswir1 committed
689
static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
690
{
blueswir1's avatar
blueswir1 committed
691
    sparc_def_t def1, *def = &def1;
692

blueswir1's avatar
blueswir1 committed
693 694
    if (cpu_sparc_find_by_name(def, cpu_model) < 0)
        return -1;
695

blueswir1's avatar
blueswir1 committed
696
    env->features = def->features;
697 698 699 700 701 702 703 704 705 706 707 708
    env->cpu_model_str = cpu_model;
    env->version = def->iu_version;
    env->fsr = def->fpu_version;
#if !defined(TARGET_SPARC64)
    env->mmu_bm = def->mmu_bm;
    env->mmu_ctpr_mask = def->mmu_ctpr_mask;
    env->mmu_cxr_mask = def->mmu_cxr_mask;
    env->mmu_sfsr_mask = def->mmu_sfsr_mask;
    env->mmu_trcr_mask = def->mmu_trcr_mask;
    env->mmuregs[0] |= def->mmu_version;
    cpu_sparc_set_id(env, 0);
#endif
blueswir1's avatar
blueswir1 committed
709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724
    return 0;
}

static void cpu_sparc_close(CPUSPARCState *env)
{
    free(env);
}

CPUSPARCState *cpu_sparc_init(const char *cpu_model)
{
    CPUSPARCState *env;

    env = qemu_mallocz(sizeof(CPUSPARCState));
    if (!env)
        return NULL;
    cpu_exec_init(env);
725 726 727

    gen_intermediate_code_init(env);

blueswir1's avatar
blueswir1 committed
728 729 730 731
    if (cpu_sparc_register(env, cpu_model) < 0) {
        cpu_sparc_close(env);
        return NULL;
    }
732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751
    cpu_reset(env);

    return env;
}

void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
{
#if !defined(TARGET_SPARC64)
    env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
#endif
}

static const sparc_def_t sparc_defs[] = {
#ifdef TARGET_SPARC64
    {
        .name = "Fujitsu Sparc64",
        .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
                       | (MAXTL << 8) | (NWINDOWS - 1)),
        .fpu_version = 0x00000000,
        .mmu_version = 0,
blueswir1's avatar
blueswir1 committed
752
        .features = CPU_DEFAULT_FEATURES,
753 754 755 756 757 758 759
    },
    {
        .name = "Fujitsu Sparc64 III",
        .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
                       | (MAXTL << 8) | (NWINDOWS - 1)),
        .fpu_version = 0x00000000,
        .mmu_version = 0,
blueswir1's avatar
blueswir1 committed
760
        .features = CPU_DEFAULT_FEATURES,
761 762 763 764 765 766 767
    },
    {
        .name = "Fujitsu Sparc64 IV",
        .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
                       | (MAXTL << 8) | (NWINDOWS - 1)),
        .fpu_version = 0x00000000,
        .mmu_version = 0,
blueswir1's avatar
blueswir1 committed
768
        .features = CPU_DEFAULT_FEATURES,
769 770 771 772 773 774 775
    },
    {
        .name = "Fujitsu Sparc64 V",
        .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
                       | (MAXTL << 8) | (NWINDOWS - 1)),
        .fpu_version = 0x00000000,
        .mmu_version = 0,
blueswir1's avatar
blueswir1 committed
776
        .features = CPU_DEFAULT_FEATURES,
777 778 779 780 781 782 783
    },
    {
        .name = "TI UltraSparc I",
        .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
                       | (MAXTL << 8) | (NWINDOWS - 1)),
        .fpu_version = 0x00000000,
        .mmu_version = 0,
blueswir1's avatar
blueswir1 committed
784
        .features = CPU_DEFAULT_FEATURES,
785 786 787 788 789 790 791
    },
    {
        .name = "TI UltraSparc II",
        .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
                       | (MAXTL << 8) | (NWINDOWS - 1)),
        .fpu_version = 0x00000000,
        .mmu_version = 0,
blueswir1's avatar
blueswir1 committed
792
        .features = CPU_DEFAULT_FEATURES,
793 794 795 796 797 798 799
    },
    {
        .name = "TI UltraSparc IIi",
        .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
                       | (MAXTL << 8) | (NWINDOWS - 1)),
        .fpu_version = 0x00000000,
        .mmu_version = 0,
blueswir1's avatar
blueswir1 committed
800
        .features = CPU_DEFAULT_FEATURES,
801 802 803 804 805 806 807
    },
    {
        .name = "TI UltraSparc IIe",
        .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
                       | (MAXTL << 8) | (NWINDOWS - 1)),
        .fpu_version = 0x00000000,
        .mmu_version = 0,
blueswir1's avatar
blueswir1 committed
808
        .features = CPU_DEFAULT_FEATURES,
809 810 811 812 813 814 815
    },
    {
        .name = "Sun UltraSparc III",
        .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
                       | (MAXTL << 8) | (NWINDOWS - 1)),
        .fpu_version = 0x00000000,
        .mmu_version = 0,
blueswir1's avatar
blueswir1 committed
816
        .features = CPU_DEFAULT_FEATURES,
817 818 819 820 821 822 823
    },
    {
        .name = "Sun UltraSparc III Cu",
        .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
                       | (MAXTL << 8) | (NWINDOWS - 1)),
        .fpu_version = 0x00000000,
        .mmu_version = 0,
blueswir1's avatar
blueswir1 committed
824
        .features = CPU_DEFAULT_FEATURES,
825 826 827 828 829 830 831
    },
    {
        .name = "Sun UltraSparc IIIi",
        .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
                       | (MAXTL << 8) | (NWINDOWS - 1)),
        .fpu_version = 0x00000000,
        .mmu_version = 0,
blueswir1's avatar
blueswir1 committed
832
        .features = CPU_DEFAULT_FEATURES,
833 834 835 836 837 838 839
    },
    {
        .name = "Sun UltraSparc IV",
        .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
                       | (MAXTL << 8) | (NWINDOWS - 1)),
        .fpu_version = 0x00000000,
        .mmu_version = 0,
blueswir1's avatar
blueswir1 committed
840
        .features = CPU_DEFAULT_FEATURES,
841 842 843 844 845 846 847
    },
    {
        .name = "Sun UltraSparc IV+",
        .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
                       | (MAXTL << 8) | (NWINDOWS - 1)),
        .fpu_version = 0x00000000,
        .mmu_version = 0,
blueswir1's avatar
blueswir1 committed
848
        .features = CPU_DEFAULT_FEATURES,
849 850 851 852 853 854 855
    },
    {
        .name = "Sun UltraSparc IIIi+",
        .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)
                       | (MAXTL << 8) | (NWINDOWS - 1)),
        .fpu_version = 0x00000000,
        .mmu_version = 0,
blueswir1's avatar
blueswir1 committed
856
        .features = CPU_DEFAULT_FEATURES,
857 858 859 860 861 862 863
    },
    {
        .name = "NEC UltraSparc I",
        .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
                       | (MAXTL << 8) | (NWINDOWS - 1)),
        .fpu_version = 0x00000000,
        .mmu_version = 0,
blueswir1's avatar
blueswir1 committed
864
        .features = CPU_DEFAULT_FEATURES,
865 866 867 868 869 870 871 872 873 874 875 876
    },
#else
    {
        .name = "Fujitsu MB86900",
        .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
        .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
        .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
        .mmu_bm = 0x00004000,
        .mmu_ctpr_mask = 0x007ffff0,
        .mmu_cxr_mask = 0x0000003f,
        .mmu_sfsr_mask = 0xffffffff,
        .mmu_trcr_mask = 0xffffffff,
blueswir1's avatar
blueswir1 committed
877
        .features = CPU_FEATURE_FLOAT,
878 879 880 881 882 883 884 885 886 887 888
    },
    {
        .name = "Fujitsu MB86904",
        .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
        .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
        .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
        .mmu_bm = 0x00004000,
        .mmu_ctpr_mask = 0x00ffffc0,
        .mmu_cxr_mask = 0x000000ff,
        .mmu_sfsr_mask = 0x00016fff,
        .mmu_trcr_mask = 0x00ffffff,
blueswir1's avatar
blueswir1 committed
889
        .features = CPU_DEFAULT_FEATURES,
890 891 892 893 894 895 896 897 898 899 900
    },
    {
        .name = "Fujitsu MB86907",
        .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
        .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
        .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
        .mmu_bm = 0x00004000,
        .mmu_ctpr_mask = 0xffffffc0,
        .mmu_cxr_mask = 0x000000ff,
        .mmu_sfsr_mask = 0x00016fff,
        .mmu_trcr_mask = 0xffffffff,
blueswir1's avatar
blueswir1 committed
901
        .features = CPU_DEFAULT_FEATURES,
902 903 904 905 906 907 908 909 910 911 912
    },
    {
        .name = "LSI L64811",
        .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
        .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
        .mmu_version = 0x10 << 24,
        .mmu_bm = 0x00004000,
        .mmu_ctpr_mask = 0x007ffff0,
        .mmu_cxr_mask = 0x0000003f,
        .mmu_sfsr_mask = 0xffffffff,
        .mmu_trcr_mask = 0xffffffff,
blueswir1's avatar
blueswir1 committed
913
        .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT,
914 915 916 917 918 919 920 921 922 923 924
    },
    {
        .name = "Cypress CY7C601",
        .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
        .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
        .mmu_version = 0x10 << 24,
        .mmu_bm = 0x00004000,
        .mmu_ctpr_mask = 0x007ffff0,
        .mmu_cxr_mask = 0x0000003f,
        .mmu_sfsr_mask = 0xffffffff,
        .mmu_trcr_mask = 0xffffffff,
blueswir1's avatar
blueswir1 committed
925
        .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT,
926 927 928 929 930 931 932 933 934 935 936
    },
    {
        .name = "Cypress CY7C611",
        .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
        .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
        .mmu_version = 0x10 << 24,
        .mmu_bm = 0x00004000,
        .mmu_ctpr_mask = 0x007ffff0,
        .mmu_cxr_mask = 0x0000003f,
        .mmu_sfsr_mask = 0xffffffff,
        .mmu_trcr_mask = 0xffffffff,
blueswir1's avatar
blueswir1 committed
937
        .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT,
938 939 940 941 942 943 944 945 946 947 948
    },
    {
        .name = "TI SuperSparc II",
        .iu_version = 0x40000000,
        .fpu_version = 0 << 17,
        .mmu_version = 0x04000000,
        .mmu_bm = 0x00002000,
        .mmu_ctpr_mask = 0xffffffc0,
        .mmu_cxr_mask = 0x0000ffff,
        .mmu_sfsr_mask = 0xffffffff,
        .mmu_trcr_mask = 0xffffffff,
blueswir1's avatar
blueswir1 committed
949
        .features = CPU_DEFAULT_FEATURES,
950 951 952 953 954 955 956 957 958 959 960
    },
    {
        .name = "TI MicroSparc I",
        .iu_version = 0x41000000,
        .fpu_version = 4 << 17,
        .mmu_version = 0x41000000,
        .mmu_bm = 0x00004000,
        .mmu_ctpr_mask = 0x007ffff0,
        .mmu_cxr_mask = 0x0000003f,
        .mmu_sfsr_mask = 0x00016fff,
        .mmu_trcr_mask = 0x0000003f,
blueswir1's avatar
blueswir1 committed
961
        .features = CPU_DEFAULT_FEATURES,
962 963 964 965 966 967 968 969 970 971 972
    },
    {
        .name = "TI MicroSparc II",
        .iu_version = 0x42000000,
        .fpu_version = 4 << 17,
        .mmu_version = 0x02000000,
        .mmu_bm = 0x00004000,
        .mmu_ctpr_mask = 0x00ffffc0,
        .mmu_cxr_mask = 0x000000ff,
        .mmu_sfsr_mask = 0x00016fff,
        .mmu_trcr_mask = 0x00ffffff,
blueswir1's avatar
blueswir1 committed
973
        .features = CPU_DEFAULT_FEATURES,
974 975 976 977 978 979 980 981 982 983 984
    },
    {
        .name = "TI MicroSparc IIep",
        .iu_version = 0x42000000,
        .fpu_version = 4 << 17,
        .mmu_version = 0x04000000,
        .mmu_bm = 0x00004000,
        .mmu_ctpr_mask = 0x00ffffc0,
        .mmu_cxr_mask = 0x000000ff,
        .mmu_sfsr_mask = 0x00016bff,
        .mmu_trcr_mask = 0x00ffffff,
blueswir1's avatar
blueswir1 committed
985
        .features = CPU_DEFAULT_FEATURES,
986 987 988 989 990 991 992 993 994 995 996
    },
    {
        .name = "TI SuperSparc 51",
        .iu_version = 0x43000000,
        .fpu_version = 0 << 17,
        .mmu_version = 0x04000000,
        .mmu_bm = 0x00002000,
        .mmu_ctpr_mask = 0xffffffc0,
        .mmu_cxr_mask = 0x0000ffff,
        .mmu_sfsr_mask = 0xffffffff,
        .mmu_trcr_mask = 0xffffffff,
blueswir1's avatar
blueswir1 committed
997
        .features = CPU_DEFAULT_FEATURES,
998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008
    },
    {
        .name = "TI SuperSparc 61",
        .iu_version = 0x44000000,
        .fpu_version = 0 << 17,
        .mmu_version = 0x04000000,
        .mmu_bm = 0x00002000,
        .mmu_ctpr_mask = 0xffffffc0,
        .mmu_cxr_mask = 0x0000ffff,
        .mmu_sfsr_mask = 0xffffffff,
        .mmu_trcr_mask = 0xffffffff,
blueswir1's avatar
blueswir1 committed
1009
        .features = CPU_DEFAULT_FEATURES,
1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020
    },
    {
        .name = "Ross RT625",
        .iu_version = 0x1e000000,
        .fpu_version = 1 << 17,
        .mmu_version = 0x1e000000,
        .mmu_bm = 0x00004000,
        .mmu_ctpr_mask = 0x007ffff0,
        .mmu_cxr_mask = 0x0000003f,
        .mmu_sfsr_mask = 0xffffffff,
        .mmu_trcr_mask = 0xffffffff,
blueswir1's avatar
blueswir1 committed
1021
        .features = CPU_DEFAULT_FEATURES,
1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032
    },
    {
        .name = "Ross RT620",
        .iu_version = 0x1f000000,
        .fpu_version = 1 << 17,
        .mmu_version = 0x1f000000,
        .mmu_bm = 0x00004000,
        .mmu_ctpr_mask = 0x007ffff0,
        .mmu_cxr_mask = 0x0000003f,
        .mmu_sfsr_mask = 0xffffffff,
        .mmu_trcr_mask = 0xffffffff,
blueswir1's avatar
blueswir1 committed
1033
        .features = CPU_DEFAULT_FEATURES,
1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044
    },
    {
        .name = "BIT B5010",
        .iu_version = 0x20000000,
        .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
        .mmu_version = 0x20000000,
        .mmu_bm = 0x00004000,
        .mmu_ctpr_mask = 0x007ffff0,
        .mmu_cxr_mask = 0x0000003f,
        .mmu_sfsr_mask = 0xffffffff,
        .mmu_trcr_mask = 0xffffffff,
blueswir1's avatar
blueswir1 committed
1045
        .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT,
1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056
    },
    {
        .name = "Matsushita MN10501",
        .iu_version = 0x50000000,
        .fpu_version = 0 << 17,
        .mmu_version = 0x50000000,
        .mmu_bm = 0x00004000,
        .mmu_ctpr_mask = 0x007ffff0,
        .mmu_cxr_mask = 0x0000003f,
        .mmu_sfsr_mask = 0xffffffff,
        .mmu_trcr_mask = 0xffffffff,
blueswir1's avatar
blueswir1 committed
1057
        .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT,
1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068
    },
    {
        .name = "Weitek W8601",
        .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
        .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
        .mmu_version = 0x10 << 24,
        .mmu_bm = 0x00004000,
        .mmu_ctpr_mask = 0x007ffff0,
        .mmu_cxr_mask = 0x0000003f,
        .mmu_sfsr_mask = 0xffffffff,
        .mmu_trcr_mask = 0xffffffff,
blueswir1's avatar
blueswir1 committed
1069
        .features = CPU_DEFAULT_FEATURES,
1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080
    },
    {
        .name = "LEON2",
        .iu_version = 0xf2000000,
        .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
        .mmu_version = 0xf2000000,
        .mmu_bm = 0x00004000,
        .mmu_ctpr_mask = 0x007ffff0,
        .mmu_cxr_mask = 0x0000003f,
        .mmu_sfsr_mask = 0xffffffff,
        .mmu_trcr_mask = 0xffffffff,
blueswir1's avatar
blueswir1 committed
1081
        .features = CPU_DEFAULT_FEATURES,
1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092
    },
    {
        .name = "LEON3",
        .iu_version = 0xf3000000,
        .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
        .mmu_version = 0xf3000000,
        .mmu_bm = 0x00004000,
        .mmu_ctpr_mask = 0x007ffff0,
        .mmu_cxr_mask = 0x0000003f,
        .mmu_sfsr_mask = 0xffffffff,
        .mmu_trcr_mask = 0xffffffff,
blueswir1's avatar
blueswir1 committed
1093
        .features = CPU_DEFAULT_FEATURES,
1094 1095 1096 1097
    },
#endif
};

blueswir1's avatar
blueswir1 committed
1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113
static const char * const feature_name[] = {
    "float",
    "float128",
    "swap",
    "mul",
    "div",
    "flush",
    "fsqrt",
    "fmul",
    "vis1",
    "vis2",
};

static void print_features(FILE *f,
                           int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
                           uint32_t features, const char *prefix)
1114 1115 1116
{
    unsigned int i;

blueswir1's avatar
blueswir1 committed
1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147
    for (i = 0; i < ARRAY_SIZE(feature_name); i++)
        if (feature_name[i] && (features & (1 << i))) {
            if (prefix)
                (*cpu_fprintf)(f, "%s", prefix);
            (*cpu_fprintf)(f, "%s ", feature_name[i]);
        }
}

static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
{
    unsigned int i;

    for (i = 0; i < ARRAY_SIZE(feature_name); i++)
        if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
            *features |= 1 << i;
            return;
        }
    fprintf(stderr, "CPU feature %s not found\n", flagname);
}

static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const unsigned char *cpu_model)
{
    unsigned int i;
    const sparc_def_t *def = NULL;
    char *s = strdup(cpu_model);
    char *featurestr, *name = strtok(s, ",");
    uint32_t plus_features = 0;
    uint32_t minus_features = 0;
    long long iu_version;
    uint32_t fpu_version, mmu_version;

1148 1149
    for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
        if (strcasecmp(name, sparc_defs[i].name) == 0) {
blueswir1's avatar
blueswir1 committed
1150
            def = &sparc_defs[i];
1151 1152
        }
    }
blueswir1's avatar
blueswir1 committed
1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223
    if (!def)
        goto error;
    memcpy(cpu_def, def, sizeof(*def));

    featurestr = strtok(NULL, ",");
    while (featurestr) {
        char *val;

        if (featurestr[0] == '+') {
            add_flagname_to_bitmaps(featurestr + 1, &plus_features);
        } else if (featurestr[0] == '-') {
            add_flagname_to_bitmaps(featurestr + 1, &minus_features);
        } else if ((val = strchr(featurestr, '='))) {
            *val = 0; val++;