translate_init.c 10.2 KB
Newer Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
/*
 *  MIPS emulation for qemu: CPU initialisation routines.
 *
 *  Copyright (c) 2004-2005 Jocelyn Mayer
 *  Copyright (c) 2007 Herve Poussineau
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

22
23
24
25
26
27
28
29
30
/* CPU / CPU family specific config register values. */

/* Have config1, is MIPS32R1, uses TLB, no virtual icache,
   uncached coherency */
#define MIPS_CONFIG0                                              \
  ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) |      \
   (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) |    \
   (0x2 << CP0C0_K0))

31
/* Have config2, 64 sets Icache, 16 bytes Icache line,
32
33
34
35
36
   2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
   no coprocessor2 attached, no MDMX support attached,
   no performance counters, watch registers present,
   no code compression, EJTAG present, no FPU */
#define MIPS_CONFIG1                                              \
37
((1 << CP0C1_M) |                                                 \
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
 (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) |      \
 (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) |      \
 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |            \
 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) |            \
 (0 << CP0C1_FP))

/* Have config3, no tertiary/secondary caches implemented */
#define MIPS_CONFIG2                                              \
((1 << CP0C2_M))

/* No config4, no DSP ASE, no large physaddr,
   no external interrupt controller, no vectored interupts,
   no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
#define MIPS_CONFIG3                                              \
((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \
 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |        \
 (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))

/* Define a implementation number of 1.
   Define a major version 1, minor version 0. */
58
#define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV))
59
60


61
62
63
64
65
struct mips_def_t {
    const unsigned char *name;
    int32_t CP0_PRid;
    int32_t CP0_Config0;
    int32_t CP0_Config1;
66
67
    int32_t CP0_Config2;
    int32_t CP0_Config3;
68
69
    int32_t CP0_Config6;
    int32_t CP0_Config7;
ths's avatar
ths committed
70
71
    int32_t SYNCI_Step;
    int32_t CCRes;
72
    int32_t Status_rw_bitmask;
73
    int32_t CP1_fcr0;
74
75
76
77
78
79
};

/*****************************************************************************/
/* MIPS CPU definitions */
static mips_def_t mips_defs[] =
{
ths's avatar
ths committed
80
#ifndef TARGET_MIPS64
81
82
83
84
    {
        .name = "4Kc",
        .CP0_PRid = 0x00018000,
        .CP0_Config0 = MIPS_CONFIG0,
85
        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
86
87
        .CP0_Config2 = MIPS_CONFIG2,
        .CP0_Config3 = MIPS_CONFIG3,
ths's avatar
ths committed
88
89
        .SYNCI_Step = 32,
        .CCRes = 2,
90
        .Status_rw_bitmask = 0x3278FF17,
91
92
    },
    {
93
        .name = "4KEcR1",
94
        .CP0_PRid = 0x00018400,
95
        .CP0_Config0 = MIPS_CONFIG0,
96
        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
97
98
        .CP0_Config2 = MIPS_CONFIG2,
        .CP0_Config3 = MIPS_CONFIG3,
ths's avatar
ths committed
99
100
        .SYNCI_Step = 32,
        .CCRes = 2,
101
        .Status_rw_bitmask = 0x3278FF17,
102
103
104
105
106
    },
    {
        .name = "4KEc",
        .CP0_PRid = 0x00019000,
        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
107
        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
108
109
        .CP0_Config2 = MIPS_CONFIG2,
        .CP0_Config3 = MIPS_CONFIG3,
ths's avatar
ths committed
110
111
        .SYNCI_Step = 32,
        .CCRes = 2,
112
        .Status_rw_bitmask = 0x3278FF17,
113
114
115
116
    },
    {
        .name = "24Kc",
        .CP0_PRid = 0x00019300,
117
        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
118
        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
119
120
        .CP0_Config2 = MIPS_CONFIG2,
        .CP0_Config3 = MIPS_CONFIG3,
ths's avatar
ths committed
121
122
        .SYNCI_Step = 32,
        .CCRes = 2,
123
        .Status_rw_bitmask = 0x3278FF17,
124
125
126
127
128
    },
    {
        .name = "24Kf",
        .CP0_PRid = 0x00019300,
        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
129
        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU),
130
131
        .CP0_Config2 = MIPS_CONFIG2,
        .CP0_Config3 = MIPS_CONFIG3,
ths's avatar
ths committed
132
133
        .SYNCI_Step = 32,
        .CCRes = 2,
134
135
136
        .Status_rw_bitmask = 0x3678FF17,
        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
                    (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
137
138
139
140
141
142
    },
#else
    {
        .name = "R4000",
        .CP0_PRid = 0x00000400,
        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
143
        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU),
144
145
        .CP0_Config2 = MIPS_CONFIG2,
        .CP0_Config3 = MIPS_CONFIG3,
ths's avatar
ths committed
146
147
        .SYNCI_Step = 16,
        .CCRes = 2,
148
        .Status_rw_bitmask = 0x3678FFFF,
149
	/* The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */
150
151
152
153
154
155
156
157
158
159
160
161
162
163
        .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
    },
    {
        .name = "5Kc",
        .CP0_PRid = 0x00018100,
        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
        .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
		    (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
		    (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
		    (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
        .CP0_Config2 = MIPS_CONFIG2,
        .CP0_Config3 = MIPS_CONFIG3,
        .SYNCI_Step = 32,
        .CCRes = 2,
ths's avatar
ths committed
164
        .Status_rw_bitmask = 0x32F8FFFF,
165
166
167
168
169
170
171
172
173
174
175
176
177
    },
    {
        .name = "5Kf",
        .CP0_PRid = 0x00018100,
        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
		    (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
		    (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
		    (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
        .CP0_Config2 = MIPS_CONFIG2,
        .CP0_Config3 = MIPS_CONFIG3,
        .SYNCI_Step = 32,
        .CCRes = 2,
ths's avatar
ths committed
178
        .Status_rw_bitmask = 0x36F8FFFF,
179
	/* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
        .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
                    (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
    },
    {
        .name = "20Kc",
        .CP0_PRid = 0x00018200,
        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (1 << CP0C0_VI),
        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
		    (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
		    (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
		    (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
        .CP0_Config2 = MIPS_CONFIG2,
        .CP0_Config3 = MIPS_CONFIG3,
        .SYNCI_Step = 32,
        .CCRes = 2,
        .Status_rw_bitmask = 0x36FBFFFF,
196
	/* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
197
        .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
198
                    (1 << FCR0_D) | (1 << FCR0_S) |
199
                    (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
    },
#endif
};

int mips_find_by_name (const unsigned char *name, mips_def_t **def)
{
    int i, ret;

    ret = -1;
    *def = NULL;
    for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
        if (strcasecmp(name, mips_defs[i].name) == 0) {
            *def = &mips_defs[i];
            ret = 0;
            break;
        }
    }

    return ret;
}

void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
{
    int i;

    for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
        (*cpu_fprintf)(f, "MIPS '%s'\n",
                       mips_defs[i].name);
    }
}

231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
#ifndef CONFIG_USER_ONLY
static void no_mmu_init (CPUMIPSState *env, mips_def_t *def)
{
    env->nb_tlb = 1;
    env->map_address = &no_mmu_map_address;
}

static void fixed_mmu_init (CPUMIPSState *env, mips_def_t *def)
{
    env->nb_tlb = 1;
    env->map_address = &fixed_mmu_map_address;
}

static void r4k_mmu_init (CPUMIPSState *env, mips_def_t *def)
{
    env->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
    env->map_address = &r4k_map_address;
    env->do_tlbwi = r4k_do_tlbwi;
    env->do_tlbwr = r4k_do_tlbwr;
    env->do_tlbp = r4k_do_tlbp;
    env->do_tlbr = r4k_do_tlbr;
}
#endif /* CONFIG_USER_ONLY */

255
256
int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
{
ths's avatar
ths committed
257
258
    if (!def)
        def = env->cpu_model;
259
260
    if (!def)
        cpu_abort(env, "Unable to find MIPS CPU definition\n");
ths's avatar
ths committed
261
    env->cpu_model = def;
262
263
    env->CP0_PRid = def->CP0_PRid;
    env->CP0_Config0 = def->CP0_Config0;
ths's avatar
ths committed
264
265
#ifdef TARGET_WORDS_BIGENDIAN
    env->CP0_Config0 |= (1 << CP0C0_BE);
266
#endif
267
    env->CP0_Config1 = def->CP0_Config1;
268
269
    env->CP0_Config2 = def->CP0_Config2;
    env->CP0_Config3 = def->CP0_Config3;
270
271
    env->CP0_Config6 = def->CP0_Config6;
    env->CP0_Config7 = def->CP0_Config7;
ths's avatar
ths committed
272
273
    env->SYNCI_Step = def->SYNCI_Step;
    env->CCRes = def->CCRes;
274
    env->Status_rw_bitmask = def->Status_rw_bitmask;
275
    env->fcr0 = def->CP1_fcr0;
ths's avatar
ths committed
276
277
278
279
280
281
#ifdef CONFIG_USER_ONLY
    if (env->CP0_Config1 & (1 << CP0C1_FP))
        env->hflags |= MIPS_HFLAG_FPU;
    if (env->fcr0 & (1 << FCR0_F64))
        env->hflags |= MIPS_HFLAG_F64;
#else
282
283
284
285
    /* There are more full-featured MMU variants in older MIPS CPUs,
       R3000, R6000 and R8000 come to mind. If we ever support them,
       this check will need to look up a different place than those
       newfangled config registers. */
286
287
288
289
290
291
292
293
294
295
296
297
298
    switch ((env->CP0_Config0 >> CP0C0_MT) & 3) {
        case 0:
            no_mmu_init(env, def);
            break;
        case 1:
            r4k_mmu_init(env, def);
            break;
        case 3:
            fixed_mmu_init(env, def);
            break;
        default:
            cpu_abort(env, "MMU type not supported\n");
    }
299
300
    env->CP0_Random = env->nb_tlb - 1;
    env->tlb_in_use = env->nb_tlb;
301
#endif /* CONFIG_USER_ONLY */
302
303
    return 0;
}