helper.c 51.2 KB
Newer Older
1 2
/*
 *  sparc helpers
3
 *
bellard's avatar
bellard committed
4
 *  Copyright (c) 2003-2005 Fabrice Bellard
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
20 21 22 23 24 25 26 27 28 29
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include <assert.h>

#include "cpu.h"
#include "exec-all.h"
30
#include "qemu-common.h"
blueswir1's avatar
blueswir1 committed
31
#include "helper.h"
32

bellard's avatar
bellard committed
33
//#define DEBUG_MMU
blueswir1's avatar
blueswir1 committed
34
//#define DEBUG_FEATURES
35
//#define DEBUG_PCALL
36

37 38 39
typedef struct sparc_def_t sparc_def_t;

struct sparc_def_t {
blueswir1's avatar
blueswir1 committed
40
    const char *name;
41 42 43 44 45 46 47 48
    target_ulong iu_version;
    uint32_t fpu_version;
    uint32_t mmu_version;
    uint32_t mmu_bm;
    uint32_t mmu_ctpr_mask;
    uint32_t mmu_cxr_mask;
    uint32_t mmu_sfsr_mask;
    uint32_t mmu_trcr_mask;
blueswir1's avatar
blueswir1 committed
49
    uint32_t features;
50
    uint32_t nwindows;
51 52
};

blueswir1's avatar
blueswir1 committed
53
static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
54

55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
/* Sparc MMU emulation */

/* thread support */

spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;

void cpu_lock(void)
{
    spin_lock(&global_cpu_lock);
}

void cpu_unlock(void)
{
    spin_unlock(&global_cpu_lock);
}

71
#if defined(CONFIG_USER_ONLY)
bellard's avatar
bellard committed
72

blueswir1's avatar
blueswir1 committed
73
int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
74
                               int mmu_idx, int is_softmmu)
bellard's avatar
bellard committed
75
{
bellard's avatar
bellard committed
76
    if (rw & 2)
blueswir1's avatar
blueswir1 committed
77
        env1->exception_index = TT_TFAULT;
bellard's avatar
bellard committed
78
    else
blueswir1's avatar
blueswir1 committed
79
        env1->exception_index = TT_DFAULT;
bellard's avatar
bellard committed
80 81 82 83
    return 1;
}

#else
84

bellard's avatar
bellard committed
85
#ifndef TARGET_SPARC64
bellard's avatar
bellard committed
86 87 88
/*
 * Sparc V8 Reference MMU (SRMMU)
 */
89 90 91 92 93 94 95 96 97 98 99
static const int access_table[8][8] = {
    { 0, 0, 0, 0, 2, 0, 3, 3 },
    { 0, 0, 0, 0, 2, 0, 0, 0 },
    { 2, 2, 0, 0, 0, 2, 3, 3 },
    { 2, 2, 0, 0, 0, 2, 0, 0 },
    { 2, 0, 2, 0, 2, 2, 3, 3 },
    { 2, 0, 2, 0, 2, 0, 2, 0 },
    { 2, 2, 2, 0, 2, 2, 3, 3 },
    { 2, 2, 2, 0, 2, 2, 2, 0 }
};

bellard's avatar
bellard committed
100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
static const int perm_table[2][8] = {
    {
        PAGE_READ,
        PAGE_READ | PAGE_WRITE,
        PAGE_READ | PAGE_EXEC,
        PAGE_READ | PAGE_WRITE | PAGE_EXEC,
        PAGE_EXEC,
        PAGE_READ | PAGE_WRITE,
        PAGE_READ | PAGE_EXEC,
        PAGE_READ | PAGE_WRITE | PAGE_EXEC
    },
    {
        PAGE_READ,
        PAGE_READ | PAGE_WRITE,
        PAGE_READ | PAGE_EXEC,
        PAGE_READ | PAGE_WRITE | PAGE_EXEC,
        PAGE_EXEC,
        PAGE_READ,
        0,
        0,
    }
121 122
};

123 124 125
static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
                                int *prot, int *access_index,
                                target_ulong address, int rw, int mmu_idx)
126
{
bellard's avatar
bellard committed
127 128
    int access_perms = 0;
    target_phys_addr_t pde_ptr;
129 130
    uint32_t pde;
    target_ulong virt_addr;
131
    int error_code = 0, is_dirty, is_user;
bellard's avatar
bellard committed
132
    unsigned long page_offset;
133

134
    is_user = mmu_idx == MMU_USER_IDX;
135
    virt_addr = address & TARGET_PAGE_MASK;
blueswir1's avatar
blueswir1 committed
136

137
    if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
blueswir1's avatar
blueswir1 committed
138
        // Boot mode: instruction fetches are taken from PROM
139
        if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) {
blueswir1's avatar
blueswir1 committed
140
            *physical = env->prom_addr | (address & 0x7ffffULL);
blueswir1's avatar
blueswir1 committed
141 142 143
            *prot = PAGE_READ | PAGE_EXEC;
            return 0;
        }
blueswir1's avatar
blueswir1 committed
144
        *physical = address;
bellard's avatar
bellard committed
145
        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
bellard's avatar
bellard committed
146
        return 0;
147 148
    }

bellard's avatar
bellard committed
149
    *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
150
    *physical = 0xffffffffffff0000ULL;
bellard's avatar
bellard committed
151

152 153
    /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
    /* Context base + context number */
154
    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
bellard's avatar
bellard committed
155
    pde = ldl_phys(pde_ptr);
156 157 158

    /* Ctx pde */
    switch (pde & PTE_ENTRYTYPE_MASK) {
bellard's avatar
bellard committed
159
    default:
160
    case 0: /* Invalid */
blueswir1's avatar
blueswir1 committed
161
        return 1 << 2;
bellard's avatar
bellard committed
162
    case 2: /* L0 PTE, maybe should not happen? */
163
    case 3: /* Reserved */
bellard's avatar
bellard committed
164
        return 4 << 2;
bellard's avatar
bellard committed
165
    case 1: /* L0 PDE */
blueswir1's avatar
blueswir1 committed
166
        pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
bellard's avatar
bellard committed
167
        pde = ldl_phys(pde_ptr);
168

blueswir1's avatar
blueswir1 committed
169 170 171 172 173 174 175 176
        switch (pde & PTE_ENTRYTYPE_MASK) {
        default:
        case 0: /* Invalid */
            return (1 << 8) | (1 << 2);
        case 3: /* Reserved */
            return (1 << 8) | (4 << 2);
        case 1: /* L1 PDE */
            pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
bellard's avatar
bellard committed
177
            pde = ldl_phys(pde_ptr);
178

blueswir1's avatar
blueswir1 committed
179 180 181 182 183 184 185 186
            switch (pde & PTE_ENTRYTYPE_MASK) {
            default:
            case 0: /* Invalid */
                return (2 << 8) | (1 << 2);
            case 3: /* Reserved */
                return (2 << 8) | (4 << 2);
            case 1: /* L2 PDE */
                pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
bellard's avatar
bellard committed
187
                pde = ldl_phys(pde_ptr);
188

blueswir1's avatar
blueswir1 committed
189 190 191 192 193 194 195 196 197
                switch (pde & PTE_ENTRYTYPE_MASK) {
                default:
                case 0: /* Invalid */
                    return (3 << 8) | (1 << 2);
                case 1: /* PDE, should not happen */
                case 3: /* Reserved */
                    return (3 << 8) | (4 << 2);
                case 2: /* L3 PTE */
                    virt_addr = address & TARGET_PAGE_MASK;
blueswir1's avatar
blueswir1 committed
198 199
                    page_offset = (address & TARGET_PAGE_MASK) &
                        (TARGET_PAGE_SIZE - 1);
blueswir1's avatar
blueswir1 committed
200 201 202 203 204 205 206 207 208 209 210
                }
                break;
            case 2: /* L2 PTE */
                virt_addr = address & ~0x3ffff;
                page_offset = address & 0x3ffff;
            }
            break;
        case 2: /* L1 PTE */
            virt_addr = address & ~0xffffff;
            page_offset = address & 0xffffff;
        }
211 212 213
    }

    /* update page modified and dirty bits */
bellard's avatar
bellard committed
214
    is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
215
    if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
blueswir1's avatar
blueswir1 committed
216 217 218
        pde |= PG_ACCESSED_MASK;
        if (is_dirty)
            pde |= PG_MODIFIED_MASK;
bellard's avatar
bellard committed
219
        stl_phys_notdirty(pde_ptr, pde);
220 221 222
    }
    /* check access */
    access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
bellard's avatar
bellard committed
223
    error_code = access_table[*access_index][access_perms];
bellard's avatar
bellard committed
224
    if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
blueswir1's avatar
blueswir1 committed
225
        return error_code;
226 227

    /* the page can be put in the TLB */
bellard's avatar
bellard committed
228 229
    *prot = perm_table[is_user][access_perms];
    if (!(pde & PG_MODIFIED_MASK)) {
230 231
        /* only set write access if already dirty... otherwise wait
           for dirty access */
bellard's avatar
bellard committed
232
        *prot &= ~PAGE_WRITE;
233 234 235 236
    }

    /* Even if large ptes, we map only one 4KB page in the cache to
       avoid filling it too fast */
237
    *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
bellard's avatar
bellard committed
238
    return error_code;
bellard's avatar
bellard committed
239 240 241
}

/* Perform address translation */
242
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
243
                              int mmu_idx, int is_softmmu)
bellard's avatar
bellard committed
244
{
245
    target_phys_addr_t paddr;
246
    target_ulong vaddr;
bellard's avatar
bellard committed
247
    int error_code = 0, prot, ret = 0, access_index;
248

blueswir1's avatar
blueswir1 committed
249 250
    error_code = get_physical_address(env, &paddr, &prot, &access_index,
                                      address, rw, mmu_idx);
bellard's avatar
bellard committed
251
    if (error_code == 0) {
blueswir1's avatar
blueswir1 committed
252 253
        vaddr = address & TARGET_PAGE_MASK;
        paddr &= TARGET_PAGE_MASK;
bellard's avatar
bellard committed
254
#ifdef DEBUG_MMU
blueswir1's avatar
blueswir1 committed
255
        printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
256
               TARGET_FMT_lx "\n", address, paddr, vaddr);
bellard's avatar
bellard committed
257
#endif
258
        ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
blueswir1's avatar
blueswir1 committed
259
        return ret;
bellard's avatar
bellard committed
260
    }
261 262

    if (env->mmuregs[3]) /* Fault status register */
blueswir1's avatar
blueswir1 committed
263
        env->mmuregs[3] = 1; /* overflow (not read before another fault) */
bellard's avatar
bellard committed
264
    env->mmuregs[3] |= (access_index << 5) | error_code | 2;
265 266
    env->mmuregs[4] = address; /* Fault address register */

bellard's avatar
bellard committed
267
    if ((env->mmuregs[0] & MMU_NF) || env->psret == 0)  {
bellard's avatar
bellard committed
268 269 270 271
        // No fault mode: if a mapping is available, just override
        // permissions. If no mapping is available, redirect accesses to
        // neverland. Fake/overridden mappings will be flushed when
        // switching to normal mode.
blueswir1's avatar
blueswir1 committed
272
        vaddr = address & TARGET_PAGE_MASK;
bellard's avatar
bellard committed
273
        prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
274
        ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
blueswir1's avatar
blueswir1 committed
275
        return ret;
bellard's avatar
bellard committed
276 277 278 279 280 281
    } else {
        if (rw & 2)
            env->exception_index = TT_TFAULT;
        else
            env->exception_index = TT_DFAULT;
        return 1;
bellard's avatar
bellard committed
282
    }
283
}
284 285 286 287 288 289 290

target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
{
    target_phys_addr_t pde_ptr;
    uint32_t pde;

    /* Context base + context number */
291 292
    pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
        (env->mmuregs[2] << 2);
293 294 295 296 297 298 299
    pde = ldl_phys(pde_ptr);

    switch (pde & PTE_ENTRYTYPE_MASK) {
    default:
    case 0: /* Invalid */
    case 2: /* PTE, maybe should not happen? */
    case 3: /* Reserved */
blueswir1's avatar
blueswir1 committed
300
        return 0;
301
    case 1: /* L1 PDE */
blueswir1's avatar
blueswir1 committed
302 303 304
        if (mmulev == 3)
            return pde;
        pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
305 306
        pde = ldl_phys(pde_ptr);

blueswir1's avatar
blueswir1 committed
307 308 309 310 311 312 313 314 315 316 317
        switch (pde & PTE_ENTRYTYPE_MASK) {
        default:
        case 0: /* Invalid */
        case 3: /* Reserved */
            return 0;
        case 2: /* L1 PTE */
            return pde;
        case 1: /* L2 PDE */
            if (mmulev == 2)
                return pde;
            pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
318 319
            pde = ldl_phys(pde_ptr);

blueswir1's avatar
blueswir1 committed
320 321 322 323 324 325 326 327 328 329 330
            switch (pde & PTE_ENTRYTYPE_MASK) {
            default:
            case 0: /* Invalid */
            case 3: /* Reserved */
                return 0;
            case 2: /* L2 PTE */
                return pde;
            case 1: /* L3 PDE */
                if (mmulev == 1)
                    return pde;
                pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
331 332
                pde = ldl_phys(pde_ptr);

blueswir1's avatar
blueswir1 committed
333 334 335 336 337 338 339 340 341 342 343
                switch (pde & PTE_ENTRYTYPE_MASK) {
                default:
                case 0: /* Invalid */
                case 1: /* PDE, should not happen */
                case 3: /* Reserved */
                    return 0;
                case 2: /* L3 PTE */
                    return pde;
                }
            }
        }
344 345 346 347 348 349 350
    }
    return 0;
}

#ifdef DEBUG_MMU
void dump_mmu(CPUState *env)
{
351 352 353
    target_ulong va, va1, va2;
    unsigned int n, m, o;
    target_phys_addr_t pde_ptr, pa;
354 355 356 357 358
    uint32_t pde;

    printf("MMU dump:\n");
    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
    pde = ldl_phys(pde_ptr);
359 360
    printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
           (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
361
    for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
blueswir1's avatar
blueswir1 committed
362 363 364 365
        pde = mmu_probe(env, va, 2);
        if (pde) {
            pa = cpu_get_phys_page_debug(env, va);
            printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
366
                   " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
blueswir1's avatar
blueswir1 committed
367 368 369 370 371
            for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
                pde = mmu_probe(env, va1, 1);
                if (pde) {
                    pa = cpu_get_phys_page_debug(env, va1);
                    printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
372
                           " PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
blueswir1's avatar
blueswir1 committed
373 374 375 376 377
                    for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
                        pde = mmu_probe(env, va2, 0);
                        if (pde) {
                            pa = cpu_get_phys_page_debug(env, va2);
                            printf("  VA: " TARGET_FMT_lx ", PA: "
378 379
                                   TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
                                   va2, pa, pde);
blueswir1's avatar
blueswir1 committed
380 381 382 383 384
                        }
                    }
                }
            }
        }
385 386 387 388 389 390
    }
    printf("MMU dump ends\n");
}
#endif /* DEBUG_MMU */

#else /* !TARGET_SPARC64 */
bellard's avatar
bellard committed
391 392 393
/*
 * UltraSparc IIi I/DMMUs
 */
blueswir1's avatar
blueswir1 committed
394 395
static int get_physical_address_data(CPUState *env,
                                     target_phys_addr_t *physical, int *prot,
blueswir1's avatar
blueswir1 committed
396
                                     target_ulong address, int rw, int is_user)
bellard's avatar
bellard committed
397 398 399 400 401
{
    target_ulong mask;
    unsigned int i;

    if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
blueswir1's avatar
blueswir1 committed
402 403
        *physical = address;
        *prot = PAGE_READ | PAGE_WRITE;
bellard's avatar
bellard committed
404 405 406 407
        return 0;
    }

    for (i = 0; i < 64; i++) {
blueswir1's avatar
blueswir1 committed
408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430
        switch ((env->dtlb_tte[i] >> 61) & 3) {
        default:
        case 0x0: // 8k
            mask = 0xffffffffffffe000ULL;
            break;
        case 0x1: // 64k
            mask = 0xffffffffffff0000ULL;
            break;
        case 0x2: // 512k
            mask = 0xfffffffffff80000ULL;
            break;
        case 0x3: // 4M
            mask = 0xffffffffffc00000ULL;
            break;
        }
        // ctx match, vaddr match?
        if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
            (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
            // valid, access ok?
            if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
                ((env->dtlb_tte[i] & 0x4) && is_user) ||
                (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
                if (env->dmmuregs[3]) /* Fault status register */
blueswir1's avatar
blueswir1 committed
431 432
                    env->dmmuregs[3] = 2; /* overflow (not read before
                                             another fault) */
blueswir1's avatar
blueswir1 committed
433 434 435
                env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
                env->dmmuregs[4] = address; /* Fault address register */
                env->exception_index = TT_DFAULT;
bellard's avatar
bellard committed
436
#ifdef DEBUG_MMU
blueswir1's avatar
blueswir1 committed
437
                printf("DFAULT at 0x%" PRIx64 "\n", address);
bellard's avatar
bellard committed
438
#endif
blueswir1's avatar
blueswir1 committed
439 440
                return 1;
            }
blueswir1's avatar
blueswir1 committed
441 442
            *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) +
                (address & ~mask & 0x1fffffff000ULL);
blueswir1's avatar
blueswir1 committed
443 444 445 446 447
            *prot = PAGE_READ;
            if (env->dtlb_tte[i] & 0x2)
                *prot |= PAGE_WRITE;
            return 0;
        }
bellard's avatar
bellard committed
448
    }
bellard's avatar
bellard committed
449
#ifdef DEBUG_MMU
bellard's avatar
bellard committed
450
    printf("DMISS at 0x%" PRIx64 "\n", address);
bellard's avatar
bellard committed
451 452
#endif
    env->exception_index = TT_DMISS;
bellard's avatar
bellard committed
453 454 455
    return 1;
}

blueswir1's avatar
blueswir1 committed
456 457
static int get_physical_address_code(CPUState *env,
                                     target_phys_addr_t *physical, int *prot,
blueswir1's avatar
blueswir1 committed
458
                                     target_ulong address, int is_user)
bellard's avatar
bellard committed
459 460 461 462 463
{
    target_ulong mask;
    unsigned int i;

    if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
blueswir1's avatar
blueswir1 committed
464 465
        *physical = address;
        *prot = PAGE_EXEC;
bellard's avatar
bellard committed
466 467
        return 0;
    }
bellard's avatar
bellard committed
468

bellard's avatar
bellard committed
469
    for (i = 0; i < 64; i++) {
blueswir1's avatar
blueswir1 committed
470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491
        switch ((env->itlb_tte[i] >> 61) & 3) {
        default:
        case 0x0: // 8k
            mask = 0xffffffffffffe000ULL;
            break;
        case 0x1: // 64k
            mask = 0xffffffffffff0000ULL;
            break;
        case 0x2: // 512k
            mask = 0xfffffffffff80000ULL;
            break;
        case 0x3: // 4M
            mask = 0xffffffffffc00000ULL;
                break;
        }
        // ctx match, vaddr match?
        if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
            (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
            // valid, access ok?
            if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
                ((env->itlb_tte[i] & 0x4) && is_user)) {
                if (env->immuregs[3]) /* Fault status register */
blueswir1's avatar
blueswir1 committed
492 493
                    env->immuregs[3] = 2; /* overflow (not read before
                                             another fault) */
blueswir1's avatar
blueswir1 committed
494 495
                env->immuregs[3] |= (is_user << 3) | 1;
                env->exception_index = TT_TFAULT;
bellard's avatar
bellard committed
496
#ifdef DEBUG_MMU
blueswir1's avatar
blueswir1 committed
497
                printf("TFAULT at 0x%" PRIx64 "\n", address);
bellard's avatar
bellard committed
498
#endif
blueswir1's avatar
blueswir1 committed
499 500
                return 1;
            }
blueswir1's avatar
blueswir1 committed
501 502
            *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) +
                (address & ~mask & 0x1fffffff000ULL);
blueswir1's avatar
blueswir1 committed
503 504 505
            *prot = PAGE_EXEC;
            return 0;
        }
bellard's avatar
bellard committed
506
    }
bellard's avatar
bellard committed
507
#ifdef DEBUG_MMU
bellard's avatar
bellard committed
508
    printf("TMISS at 0x%" PRIx64 "\n", address);
bellard's avatar
bellard committed
509 510
#endif
    env->exception_index = TT_TMISS;
bellard's avatar
bellard committed
511 512 513
    return 1;
}

514 515 516
static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
                                int *prot, int *access_index,
                                target_ulong address, int rw, int mmu_idx)
bellard's avatar
bellard committed
517
{
518 519
    int is_user = mmu_idx == MMU_USER_IDX;

bellard's avatar
bellard committed
520
    if (rw == 2)
blueswir1's avatar
blueswir1 committed
521 522
        return get_physical_address_code(env, physical, prot, address,
                                         is_user);
bellard's avatar
bellard committed
523
    else
blueswir1's avatar
blueswir1 committed
524 525
        return get_physical_address_data(env, physical, prot, address, rw,
                                         is_user);
bellard's avatar
bellard committed
526 527 528 529
}

/* Perform address translation */
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
530
                              int mmu_idx, int is_softmmu)
bellard's avatar
bellard committed
531
{
bellard's avatar
bellard committed
532
    target_ulong virt_addr, vaddr;
bellard's avatar
bellard committed
533 534 535
    target_phys_addr_t paddr;
    int error_code = 0, prot, ret = 0, access_index;

blueswir1's avatar
blueswir1 committed
536 537
    error_code = get_physical_address(env, &paddr, &prot, &access_index,
                                      address, rw, mmu_idx);
bellard's avatar
bellard committed
538
    if (error_code == 0) {
blueswir1's avatar
blueswir1 committed
539
        virt_addr = address & TARGET_PAGE_MASK;
blueswir1's avatar
blueswir1 committed
540 541
        vaddr = virt_addr + ((address & TARGET_PAGE_MASK) &
                             (TARGET_PAGE_SIZE - 1));
bellard's avatar
bellard committed
542
#ifdef DEBUG_MMU
blueswir1's avatar
blueswir1 committed
543 544
        printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64
               "\n", address, paddr, vaddr);
bellard's avatar
bellard committed
545
#endif
546
        ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
blueswir1's avatar
blueswir1 committed
547
        return ret;
bellard's avatar
bellard committed
548 549 550 551 552
    }
    // XXX
    return 1;
}

bellard's avatar
bellard committed
553 554 555 556 557 558
#ifdef DEBUG_MMU
void dump_mmu(CPUState *env)
{
    unsigned int i;
    const char *mask;

blueswir1's avatar
blueswir1 committed
559 560
    printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n",
           env->dmmuregs[1], env->dmmuregs[2]);
bellard's avatar
bellard committed
561
    if ((env->lsu & DMMU_E) == 0) {
blueswir1's avatar
blueswir1 committed
562
        printf("DMMU disabled\n");
bellard's avatar
bellard committed
563
    } else {
blueswir1's avatar
blueswir1 committed
564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581
        printf("DMMU dump:\n");
        for (i = 0; i < 64; i++) {
            switch ((env->dtlb_tte[i] >> 61) & 3) {
            default:
            case 0x0:
                mask = "  8k";
                break;
            case 0x1:
                mask = " 64k";
                break;
            case 0x2:
                mask = "512k";
                break;
            case 0x3:
                mask = "  4M";
                break;
            }
            if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
blueswir1's avatar
blueswir1 committed
582 583
                printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
                       ", %s, %s, %s, %s, ctx %" PRId64 "\n",
blueswir1's avatar
blueswir1 committed
584 585 586 587 588 589 590 591 592
                       env->dtlb_tag[i] & ~0x1fffULL,
                       env->dtlb_tte[i] & 0x1ffffffe000ULL,
                       mask,
                       env->dtlb_tte[i] & 0x4? "priv": "user",
                       env->dtlb_tte[i] & 0x2? "RW": "RO",
                       env->dtlb_tte[i] & 0x40? "locked": "unlocked",
                       env->dtlb_tag[i] & 0x1fffULL);
            }
        }
bellard's avatar
bellard committed
593 594
    }
    if ((env->lsu & IMMU_E) == 0) {
blueswir1's avatar
blueswir1 committed
595
        printf("IMMU disabled\n");
bellard's avatar
bellard committed
596
    } else {
blueswir1's avatar
blueswir1 committed
597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614
        printf("IMMU dump:\n");
        for (i = 0; i < 64; i++) {
            switch ((env->itlb_tte[i] >> 61) & 3) {
            default:
            case 0x0:
                mask = "  8k";
                break;
            case 0x1:
                mask = " 64k";
                break;
            case 0x2:
                mask = "512k";
                break;
            case 0x3:
                mask = "  4M";
                break;
            }
            if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
blueswir1's avatar
blueswir1 committed
615 616
                printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
                       ", %s, %s, %s, ctx %" PRId64 "\n",
blueswir1's avatar
blueswir1 committed
617 618 619 620 621 622 623 624
                       env->itlb_tag[i] & ~0x1fffULL,
                       env->itlb_tte[i] & 0x1ffffffe000ULL,
                       mask,
                       env->itlb_tte[i] & 0x4? "priv": "user",
                       env->itlb_tte[i] & 0x40? "locked": "unlocked",
                       env->itlb_tag[i] & 0x1fffULL);
            }
        }
bellard's avatar
bellard committed
625 626
    }
}
627 628 629 630 631
#endif /* DEBUG_MMU */

#endif /* TARGET_SPARC64 */
#endif /* !CONFIG_USER_ONLY */

632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655

#if defined(CONFIG_USER_ONLY)
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
    return addr;
}

#else
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
    target_phys_addr_t phys_addr;
    int prot, access_index;

    if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
                             MMU_KERNEL_IDX) != 0)
        if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
                                 0, MMU_KERNEL_IDX) != 0)
            return -1;
    if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
        return -1;
    return phys_addr;
}
#endif

656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753
#ifdef TARGET_SPARC64
#ifdef DEBUG_PCALL
static const char * const excp_names[0x50] = {
    [TT_TFAULT] = "Instruction Access Fault",
    [TT_TMISS] = "Instruction Access MMU Miss",
    [TT_CODE_ACCESS] = "Instruction Access Error",
    [TT_ILL_INSN] = "Illegal Instruction",
    [TT_PRIV_INSN] = "Privileged Instruction",
    [TT_NFPU_INSN] = "FPU Disabled",
    [TT_FP_EXCP] = "FPU Exception",
    [TT_TOVF] = "Tag Overflow",
    [TT_CLRWIN] = "Clean Windows",
    [TT_DIV_ZERO] = "Division By Zero",
    [TT_DFAULT] = "Data Access Fault",
    [TT_DMISS] = "Data Access MMU Miss",
    [TT_DATA_ACCESS] = "Data Access Error",
    [TT_DPROT] = "Data Protection Error",
    [TT_UNALIGNED] = "Unaligned Memory Access",
    [TT_PRIV_ACT] = "Privileged Action",
    [TT_EXTINT | 0x1] = "External Interrupt 1",
    [TT_EXTINT | 0x2] = "External Interrupt 2",
    [TT_EXTINT | 0x3] = "External Interrupt 3",
    [TT_EXTINT | 0x4] = "External Interrupt 4",
    [TT_EXTINT | 0x5] = "External Interrupt 5",
    [TT_EXTINT | 0x6] = "External Interrupt 6",
    [TT_EXTINT | 0x7] = "External Interrupt 7",
    [TT_EXTINT | 0x8] = "External Interrupt 8",
    [TT_EXTINT | 0x9] = "External Interrupt 9",
    [TT_EXTINT | 0xa] = "External Interrupt 10",
    [TT_EXTINT | 0xb] = "External Interrupt 11",
    [TT_EXTINT | 0xc] = "External Interrupt 12",
    [TT_EXTINT | 0xd] = "External Interrupt 13",
    [TT_EXTINT | 0xe] = "External Interrupt 14",
    [TT_EXTINT | 0xf] = "External Interrupt 15",
};
#endif

void do_interrupt(CPUState *env)
{
    int intno = env->exception_index;

#ifdef DEBUG_PCALL
    if (loglevel & CPU_LOG_INT) {
        static int count;
        const char *name;

        if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80))
            name = "Unknown";
        else if (intno >= 0x100)
            name = "Trap Instruction";
        else if (intno >= 0xc0)
            name = "Window Fill";
        else if (intno >= 0x80)
            name = "Window Spill";
        else {
            name = excp_names[intno];
            if (!name)
                name = "Unknown";
        }

        fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
                " SP=%016" PRIx64 "\n",
                count, name, intno,
                env->pc,
                env->npc, env->regwptr[6]);
        cpu_dump_state(env, logfile, fprintf, 0);
#if 0
        {
            int i;
            uint8_t *ptr;

            fprintf(logfile, "       code=");
            ptr = (uint8_t *)env->pc;
            for(i = 0; i < 16; i++) {
                fprintf(logfile, " %02x", ldub(ptr + i));
            }
            fprintf(logfile, "\n");
        }
#endif
        count++;
    }
#endif
#if !defined(CONFIG_USER_ONLY)
    if (env->tl == MAXTL) {
        cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state",
                  env->exception_index);
        return;
    }
#endif
    env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
        ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
        GET_CWP64(env);
    env->tsptr->tpc = env->pc;
    env->tsptr->tnpc = env->npc;
    env->tsptr->tt = intno;
    change_pstate(PS_PEF | PS_PRIV | PS_AG);

    if (intno == TT_CLRWIN)
754
        cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
755
    else if ((intno & 0x1c0) == TT_SPILL)
756
        cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
757
    else if ((intno & 0x1c0) == TT_FILL)
758
        cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856
    env->tbr &= ~0x7fffULL;
    env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
    if (env->tl < MAXTL - 1) {
        env->tl++;
    } else {
        env->pstate |= PS_RED;
        if (env->tl != MAXTL)
            env->tl++;
    }
    env->tsptr = &env->ts[env->tl];
    env->pc = env->tbr;
    env->npc = env->pc + 4;
    env->exception_index = 0;
}
#else
#ifdef DEBUG_PCALL
static const char * const excp_names[0x80] = {
    [TT_TFAULT] = "Instruction Access Fault",
    [TT_ILL_INSN] = "Illegal Instruction",
    [TT_PRIV_INSN] = "Privileged Instruction",
    [TT_NFPU_INSN] = "FPU Disabled",
    [TT_WIN_OVF] = "Window Overflow",
    [TT_WIN_UNF] = "Window Underflow",
    [TT_UNALIGNED] = "Unaligned Memory Access",
    [TT_FP_EXCP] = "FPU Exception",
    [TT_DFAULT] = "Data Access Fault",
    [TT_TOVF] = "Tag Overflow",
    [TT_EXTINT | 0x1] = "External Interrupt 1",
    [TT_EXTINT | 0x2] = "External Interrupt 2",
    [TT_EXTINT | 0x3] = "External Interrupt 3",
    [TT_EXTINT | 0x4] = "External Interrupt 4",
    [TT_EXTINT | 0x5] = "External Interrupt 5",
    [TT_EXTINT | 0x6] = "External Interrupt 6",
    [TT_EXTINT | 0x7] = "External Interrupt 7",
    [TT_EXTINT | 0x8] = "External Interrupt 8",
    [TT_EXTINT | 0x9] = "External Interrupt 9",
    [TT_EXTINT | 0xa] = "External Interrupt 10",
    [TT_EXTINT | 0xb] = "External Interrupt 11",
    [TT_EXTINT | 0xc] = "External Interrupt 12",
    [TT_EXTINT | 0xd] = "External Interrupt 13",
    [TT_EXTINT | 0xe] = "External Interrupt 14",
    [TT_EXTINT | 0xf] = "External Interrupt 15",
    [TT_TOVF] = "Tag Overflow",
    [TT_CODE_ACCESS] = "Instruction Access Error",
    [TT_DATA_ACCESS] = "Data Access Error",
    [TT_DIV_ZERO] = "Division By Zero",
    [TT_NCP_INSN] = "Coprocessor Disabled",
};
#endif

void do_interrupt(CPUState *env)
{
    int cwp, intno = env->exception_index;

#ifdef DEBUG_PCALL
    if (loglevel & CPU_LOG_INT) {
        static int count;
        const char *name;

        if (intno < 0 || intno >= 0x100)
            name = "Unknown";
        else if (intno >= 0x80)
            name = "Trap Instruction";
        else {
            name = excp_names[intno];
            if (!name)
                name = "Unknown";
        }

        fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
                count, name, intno,
                env->pc,
                env->npc, env->regwptr[6]);
        cpu_dump_state(env, logfile, fprintf, 0);
#if 0
        {
            int i;
            uint8_t *ptr;

            fprintf(logfile, "       code=");
            ptr = (uint8_t *)env->pc;
            for(i = 0; i < 16; i++) {
                fprintf(logfile, " %02x", ldub(ptr + i));
            }
            fprintf(logfile, "\n");
        }
#endif
        count++;
    }
#endif
#if !defined(CONFIG_USER_ONLY)
    if (env->psret == 0) {
        cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
                  env->exception_index);
        return;
    }
#endif
    env->psret = 0;
857
    cwp = cpu_cwp_dec(env, env->cwp - 1);
858 859 860 861 862 863 864 865 866 867 868 869
    cpu_set_cwp(env, cwp);
    env->regwptr[9] = env->pc;
    env->regwptr[10] = env->npc;
    env->psrps = env->psrs;
    env->psrs = 1;
    env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
    env->pc = env->tbr;
    env->npc = env->pc + 4;
    env->exception_index = 0;
}
#endif

870 871 872 873 874 875 876 877 878 879 880
void memcpy32(target_ulong *dst, const target_ulong *src)
{
    dst[0] = src[0];
    dst[1] = src[1];
    dst[2] = src[2];
    dst[3] = src[3];
    dst[4] = src[4];
    dst[5] = src[5];
    dst[6] = src[6];
    dst[7] = src[7];
}
pbrook's avatar
pbrook committed
881

882 883 884 885 886 887 888 889 890
void cpu_reset(CPUSPARCState *env)
{
    tlb_flush(env, 1);
    env->cwp = 0;
    env->wim = 1;
    env->regwptr = env->regbase + (env->cwp * 16);
#if defined(CONFIG_USER_ONLY)
    env->user_mode_only = 1;
#ifdef TARGET_SPARC64
891 892
    env->cleanwin = env->nwindows - 2;
    env->cansave = env->nwindows - 2;
893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913
    env->pstate = PS_RMO | PS_PEF | PS_IE;
    env->asi = 0x82; // Primary no-fault
#endif
#else
    env->psret = 0;
    env->psrs = 1;
    env->psrps = 1;
#ifdef TARGET_SPARC64
    env->pstate = PS_PRIV;
    env->hpstate = HS_PRIV;
    env->pc = 0x1fff0000000ULL;
    env->tsptr = &env->ts[env->tl];
#else
    env->pc = 0;
    env->mmuregs[0] &= ~(MMU_E | MMU_NF);
    env->mmuregs[0] |= env->mmu_bm;
#endif
    env->npc = env->pc + 4;
#endif
}

blueswir1's avatar
blueswir1 committed
914
static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
915
{
blueswir1's avatar
blueswir1 committed
916
    sparc_def_t def1, *def = &def1;
917

blueswir1's avatar
blueswir1 committed
918 919
    if (cpu_sparc_find_by_name(def, cpu_model) < 0)
        return -1;
920

blueswir1's avatar
blueswir1 committed
921
    env->features = def->features;
922 923 924
    env->cpu_model_str = cpu_model;
    env->version = def->iu_version;
    env->fsr = def->fpu_version;
925
    env->nwindows = def->nwindows;
926 927 928 929 930 931 932 933
#if !defined(TARGET_SPARC64)
    env->mmu_bm = def->mmu_bm;
    env->mmu_ctpr_mask = def->mmu_ctpr_mask;
    env->mmu_cxr_mask = def->mmu_cxr_mask;
    env->mmu_sfsr_mask = def->mmu_sfsr_mask;
    env->mmu_trcr_mask = def->mmu_trcr_mask;
    env->mmuregs[0] |= def->mmu_version;
    cpu_sparc_set_id(env, 0);
934 935
#else
    env->version |= def->nwindows - 1;
936
#endif
blueswir1's avatar
blueswir1 committed
937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952
    return 0;
}

static void cpu_sparc_close(CPUSPARCState *env)
{
    free(env);
}

CPUSPARCState *cpu_sparc_init(const char *cpu_model)
{
    CPUSPARCState *env;

    env = qemu_mallocz(sizeof(CPUSPARCState));
    if (!env)
        return NULL;
    cpu_exec_init(env);
953 954 955

    gen_intermediate_code_init(env);

blueswir1's avatar
blueswir1 committed
956 957 958 959
    if (cpu_sparc_register(env, cpu_model) < 0) {
        cpu_sparc_close(env);
        return NULL;
    }
960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976
    cpu_reset(env);

    return env;
}

void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
{
#if !defined(TARGET_SPARC64)
    env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
#endif
}

static const sparc_def_t sparc_defs[] = {
#ifdef TARGET_SPARC64
    {
        .name = "Fujitsu Sparc64",
        .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
977
                       | (MAXTL << 8)),
978 979
        .fpu_version = 0x00000000,
        .mmu_version = 0,
980
        .nwindows = 4,
blueswir1's avatar
blueswir1 committed
981
        .features = CPU_DEFAULT_FEATURES,
982 983 984 985
    },
    {
        .name = "Fujitsu Sparc64 III",
        .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
986
                       | (MAXTL << 8)),
987 988
        .fpu_version = 0x00000000,
        .mmu_version = 0,
989
        .nwindows = 5,
blueswir1's avatar
blueswir1 committed
990
        .features = CPU_DEFAULT_FEATURES,
991 992 993 994
    },
    {
        .name = "Fujitsu Sparc64 IV",
        .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
995
                       | (MAXTL << 8)),
996 997
        .fpu_version = 0x00000000,
        .mmu_version = 0,
998
        .nwindows = 8,
blueswir1's avatar
blueswir1 committed
999
        .features = CPU_DEFAULT_FEATURES,
1000 1001 1002 1003
    },
    {
        .name = "Fujitsu Sparc64 V",
        .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
1004
                       | (MAXTL << 8)),
1005 1006
        .fpu_version = 0x00000000,
        .mmu_version = 0,
1007
        .nwindows = 8,
blueswir1's avatar
blueswir1 committed
1008
        .features = CPU_DEFAULT_FEATURES,
1009 1010 1011 1012
    },
    {
        .name = "TI UltraSparc I",
        .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
1013
                       | (MAXTL << 8)),
1014 1015
        .fpu_version = 0x00000000,
        .mmu_version = 0,
1016
        .nwindows = 8,
blueswir1's avatar
blueswir1 committed
1017
        .features = CPU_DEFAULT_FEATURES,
1018 1019 1020 1021
    },
    {
        .name = "TI UltraSparc II",
        .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
1022
                       | (MAXTL << 8)),
1023 1024
        .fpu_version = 0x00000000,
        .mmu_version = 0,
1025
        .nwindows = 8,
blueswir1's avatar
blueswir1 committed
1026
        .features = CPU_DEFAULT_FEATURES,
1027 1028 1029 1030
    },
    {
        .name = "TI UltraSparc IIi",
        .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
1031
                       | (MAXTL << 8)),
1032 1033
        .fpu_version = 0x00000000,
        .mmu_version = 0,
1034
        .nwindows = 8,
blueswir1's avatar
blueswir1 committed
1035
        .features = CPU_DEFAULT_FEATURES,
1036 1037 1038 1039
    },
    {
        .name = "TI UltraSparc IIe",
        .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
1040
                       | (MAXTL << 8)),
1041 1042
        .fpu_version = 0x00000000,
        .mmu_version = 0,
1043
        .nwindows = 8,
blueswir1's avatar
blueswir1 committed
1044
        .features = CPU_DEFAULT_FEATURES,
1045 1046 1047 1048
    },
    {
        .name = "Sun UltraSparc III",
        .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
1049
                       | (MAXTL << 8)),
1050 1051
        .fpu_version = 0x00000000,
        .mmu_version = 0,
1052
        .nwindows = 8,
blueswir1's avatar
blueswir1 committed
1053
        .features = CPU_DEFAULT_FEATURES,
1054 1055 1056 1057
    },
    {
        .name = "Sun UltraSparc III Cu",
        .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
1058
                       | (MAXTL << 8)),
1059 1060
        .fpu_version = 0x00000000,
        .mmu_version = 0,
1061
        .nwindows = 8,
blueswir1's avatar
blueswir1 committed
1062
        .features = CPU_DEFAULT_FEATURES,
1063 1064 1065 1066
    },
    {
        .name = "Sun UltraSparc IIIi",
        .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
1067
                       | (MAXTL << 8)),
1068 1069
        .fpu_version = 0x00000000,
        .mmu_version = 0,
1070
        .nwindows = 8,
blueswir1's avatar
blueswir1 committed
1071
        .features = CPU_DEFAULT_FEATURES,
1072 1073 1074 1075
    },
    {
        .name = "Sun UltraSparc IV",
        .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
1076
                       | (MAXTL << 8)),
1077 1078
        .fpu_version = 0x00000000,
        .mmu_version = 0,
1079
        .nwindows = 8,
blueswir1's avatar
blueswir1 committed
1080
        .features = CPU_DEFAULT_FEATURES,
1081 1082 1083 1084
    },
    {
        .name = "Sun UltraSparc IV+",
        .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
1085
                       | (MAXTL << 8)),
1086 1087
        .fpu_version = 0x00000000,
        .mmu_version = 0,
1088
        .nwindows = 8,
blueswir1's avatar
blueswir1 committed
1089
        .features = CPU_DEFAULT_FEATURES,
1090 1091 1092 1093
    },
    {
        .name = "Sun UltraSparc IIIi+",
        .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)