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/*
   SPARC translation

   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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   Copyright (C) 2003-2005 Fabrice Bellard
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   This library is free software; you can redistribute it and/or
   modify it under the terms of the GNU Lesser General Public
   License as published by the Free Software Foundation; either
   version 2 of the License, or (at your option) any later version.

   This library is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   Lesser General Public License for more details.

   You should have received a copy of the GNU Lesser General Public
   License along with this library; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/*
   TODO-list:

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   Rest of V9 instructions, VIS instructions
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   NPC/PC static optimisations (use JUMP_TB when possible)
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   Optimize synthetic instructions
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   Optional alignment check
   128-bit float
   Tagged add/sub
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*/
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#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>

#include "cpu.h"
#include "exec-all.h"
#include "disas.h"

#define DEBUG_DISAS

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#define DYNAMIC_PC  1 /* dynamic pc value */
#define JUMP_PC     2 /* dynamic pc value which takes only two values
                         according to jump_pc[T2] */

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typedef struct DisasContext {
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    target_ulong pc;	/* current Program Counter: integer or DYNAMIC_PC */
    target_ulong npc;	/* next PC: integer or DYNAMIC_PC or JUMP_PC */
    target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
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    int is_br;
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    int mem_idx;
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    struct TranslationBlock *tb;
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} DisasContext;

static uint16_t *gen_opc_ptr;
static uint32_t *gen_opparam_ptr;
extern FILE *logfile;
extern int loglevel;

enum {
#define DEF(s,n,copy_size) INDEX_op_ ## s,
#include "opc.h"
#undef DEF
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    NB_OPS
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};

#include "gen-op.h"

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// This function uses non-native bit order
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#define GET_FIELD(X, FROM, TO) \
  ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))

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// This function uses the order in the manuals, i.e. bit 0 is 2^0
#define GET_FIELD_SP(X, FROM, TO) \
    GET_FIELD(X, 31 - (TO), 31 - (FROM))

#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), 32 - ((b) - (a) + 1))

#ifdef TARGET_SPARC64
#define DFPREG(r) (((r & 1) << 6) | (r & 0x1e))
#else
#define DFPREG(r) (r)
#endif

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#ifdef USE_DIRECT_JUMP
#define TBPARAM(x)
#else
#define TBPARAM(x) (long)(x)
#endif

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static int sign_extend(int x, int len)
{
    len = 32 - len;
    return (x << len) >> len;
}

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#define IS_IMM (insn & (1<<13))

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static void disas_sparc_insn(DisasContext * dc);
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static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
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    {
     gen_op_movl_g0_T0,
     gen_op_movl_g1_T0,
     gen_op_movl_g2_T0,
     gen_op_movl_g3_T0,
     gen_op_movl_g4_T0,
     gen_op_movl_g5_T0,
     gen_op_movl_g6_T0,
     gen_op_movl_g7_T0,
     gen_op_movl_o0_T0,
     gen_op_movl_o1_T0,
     gen_op_movl_o2_T0,
     gen_op_movl_o3_T0,
     gen_op_movl_o4_T0,
     gen_op_movl_o5_T0,
     gen_op_movl_o6_T0,
     gen_op_movl_o7_T0,
     gen_op_movl_l0_T0,
     gen_op_movl_l1_T0,
     gen_op_movl_l2_T0,
     gen_op_movl_l3_T0,
     gen_op_movl_l4_T0,
     gen_op_movl_l5_T0,
     gen_op_movl_l6_T0,
     gen_op_movl_l7_T0,
     gen_op_movl_i0_T0,
     gen_op_movl_i1_T0,
     gen_op_movl_i2_T0,
     gen_op_movl_i3_T0,
     gen_op_movl_i4_T0,
     gen_op_movl_i5_T0,
     gen_op_movl_i6_T0,
     gen_op_movl_i7_T0,
     },
    {
     gen_op_movl_g0_T1,
     gen_op_movl_g1_T1,
     gen_op_movl_g2_T1,
     gen_op_movl_g3_T1,
     gen_op_movl_g4_T1,
     gen_op_movl_g5_T1,
     gen_op_movl_g6_T1,
     gen_op_movl_g7_T1,
     gen_op_movl_o0_T1,
     gen_op_movl_o1_T1,
     gen_op_movl_o2_T1,
     gen_op_movl_o3_T1,
     gen_op_movl_o4_T1,
     gen_op_movl_o5_T1,
     gen_op_movl_o6_T1,
     gen_op_movl_o7_T1,
     gen_op_movl_l0_T1,
     gen_op_movl_l1_T1,
     gen_op_movl_l2_T1,
     gen_op_movl_l3_T1,
     gen_op_movl_l4_T1,
     gen_op_movl_l5_T1,
     gen_op_movl_l6_T1,
     gen_op_movl_l7_T1,
     gen_op_movl_i0_T1,
     gen_op_movl_i1_T1,
     gen_op_movl_i2_T1,
     gen_op_movl_i3_T1,
     gen_op_movl_i4_T1,
     gen_op_movl_i5_T1,
     gen_op_movl_i6_T1,
     gen_op_movl_i7_T1,
     }
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};

static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
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    {
     gen_op_movl_T0_g0,
     gen_op_movl_T0_g1,
     gen_op_movl_T0_g2,
     gen_op_movl_T0_g3,
     gen_op_movl_T0_g4,
     gen_op_movl_T0_g5,
     gen_op_movl_T0_g6,
     gen_op_movl_T0_g7,
     gen_op_movl_T0_o0,
     gen_op_movl_T0_o1,
     gen_op_movl_T0_o2,
     gen_op_movl_T0_o3,
     gen_op_movl_T0_o4,
     gen_op_movl_T0_o5,
     gen_op_movl_T0_o6,
     gen_op_movl_T0_o7,
     gen_op_movl_T0_l0,
     gen_op_movl_T0_l1,
     gen_op_movl_T0_l2,
     gen_op_movl_T0_l3,
     gen_op_movl_T0_l4,
     gen_op_movl_T0_l5,
     gen_op_movl_T0_l6,
     gen_op_movl_T0_l7,
     gen_op_movl_T0_i0,
     gen_op_movl_T0_i1,
     gen_op_movl_T0_i2,
     gen_op_movl_T0_i3,
     gen_op_movl_T0_i4,
     gen_op_movl_T0_i5,
     gen_op_movl_T0_i6,
     gen_op_movl_T0_i7,
     },
    {
     gen_op_movl_T1_g0,
     gen_op_movl_T1_g1,
     gen_op_movl_T1_g2,
     gen_op_movl_T1_g3,
     gen_op_movl_T1_g4,
     gen_op_movl_T1_g5,
     gen_op_movl_T1_g6,
     gen_op_movl_T1_g7,
     gen_op_movl_T1_o0,
     gen_op_movl_T1_o1,
     gen_op_movl_T1_o2,
     gen_op_movl_T1_o3,
     gen_op_movl_T1_o4,
     gen_op_movl_T1_o5,
     gen_op_movl_T1_o6,
     gen_op_movl_T1_o7,
     gen_op_movl_T1_l0,
     gen_op_movl_T1_l1,
     gen_op_movl_T1_l2,
     gen_op_movl_T1_l3,
     gen_op_movl_T1_l4,
     gen_op_movl_T1_l5,
     gen_op_movl_T1_l6,
     gen_op_movl_T1_l7,
     gen_op_movl_T1_i0,
     gen_op_movl_T1_i1,
     gen_op_movl_T1_i2,
     gen_op_movl_T1_i3,
     gen_op_movl_T1_i4,
     gen_op_movl_T1_i5,
     gen_op_movl_T1_i6,
     gen_op_movl_T1_i7,
     },
    {
     gen_op_movl_T2_g0,
     gen_op_movl_T2_g1,
     gen_op_movl_T2_g2,
     gen_op_movl_T2_g3,
     gen_op_movl_T2_g4,
     gen_op_movl_T2_g5,
     gen_op_movl_T2_g6,
     gen_op_movl_T2_g7,
     gen_op_movl_T2_o0,
     gen_op_movl_T2_o1,
     gen_op_movl_T2_o2,
     gen_op_movl_T2_o3,
     gen_op_movl_T2_o4,
     gen_op_movl_T2_o5,
     gen_op_movl_T2_o6,
     gen_op_movl_T2_o7,
     gen_op_movl_T2_l0,
     gen_op_movl_T2_l1,
     gen_op_movl_T2_l2,
     gen_op_movl_T2_l3,
     gen_op_movl_T2_l4,
     gen_op_movl_T2_l5,
     gen_op_movl_T2_l6,
     gen_op_movl_T2_l7,
     gen_op_movl_T2_i0,
     gen_op_movl_T2_i1,
     gen_op_movl_T2_i2,
     gen_op_movl_T2_i3,
     gen_op_movl_T2_i4,
     gen_op_movl_T2_i5,
     gen_op_movl_T2_i6,
     gen_op_movl_T2_i7,
     }
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};

static GenOpFunc1 *gen_op_movl_TN_im[3] = {
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    gen_op_movl_T0_im,
    gen_op_movl_T1_im,
    gen_op_movl_T2_im
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};

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// Sign extending version
static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
    gen_op_movl_T0_sim,
    gen_op_movl_T1_sim,
    gen_op_movl_T2_sim
};

#ifdef TARGET_SPARC64
#define GEN32(func, NAME) \
static GenOpFunc *NAME ## _table [64] = {                                     \
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0,                   \
NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0,                   \
NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0,                   \
NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0,                   \
};                                                                            \
static inline void func(int n)                                                \
{                                                                             \
    NAME ## _table[n]();                                                      \
}
#else
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#define GEN32(func, NAME) \
static GenOpFunc *NAME ## _table [32] = {                                     \
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
};                                                                            \
static inline void func(int n)                                                \
{                                                                             \
    NAME ## _table[n]();                                                      \
}
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#endif
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/* floating point registers moves */
GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);

GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);

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#ifdef TARGET_SPARC64
// 'a' versions allowed to user depending on asi
#if defined(CONFIG_USER_ONLY)
#define supervisor(dc) 0
#define gen_op_ldst(name)        gen_op_##name##_raw()
#define OP_LD_TABLE(width)						\
    static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
    {									\
	int asi, offset;						\
									\
	if (IS_IMM) {							\
	    offset = GET_FIELD(insn, 25, 31);				\
	    if (is_ld)							\
		gen_op_ld_asi_reg(offset, size, sign);			\
	    else							\
		gen_op_st_asi_reg(offset, size, sign);			\
	    return;							\
	}								\
	asi = GET_FIELD(insn, 19, 26);					\
	switch (asi) {							\
	case 0x80: /* Primary address space */				\
	    gen_op_##width##_raw();					\
	    break;							\
	default:							\
            break;							\
	}								\
    }

#else
#define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
#define OP_LD_TABLE(width)						\
    static GenOpFunc *gen_op_##width[] = {				\
	&gen_op_##width##_user,						\
	&gen_op_##width##_kernel,					\
    };									\
									\
    static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
    {									\
	int asi, offset;						\
									\
	if (IS_IMM) {							\
	    offset = GET_FIELD(insn, 25, 31);				\
	    if (is_ld)							\
		gen_op_ld_asi_reg(offset, size, sign);			\
	    else							\
		gen_op_st_asi_reg(offset, size, sign);			\
	    return;							\
	}								\
	asi = GET_FIELD(insn, 19, 26);					\
	if (is_ld)							\
	    gen_op_ld_asi(asi, size, sign);				\
	else								\
	    gen_op_st_asi(asi, size, sign);				\
    }

#define supervisor(dc) (dc->mem_idx == 1)
#endif
#else
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#if defined(CONFIG_USER_ONLY)
#define gen_op_ldst(name)        gen_op_##name##_raw()
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#define OP_LD_TABLE(width)
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#define supervisor(dc) 0
#else
#define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
#define OP_LD_TABLE(width)						      \
static GenOpFunc *gen_op_##width[] = {                                        \
    &gen_op_##width##_user,                                                   \
    &gen_op_##width##_kernel,                                                 \
};                                                                            \
                                                                              \
static void gen_op_##width##a(int insn, int is_ld, int size, int sign)        \
{                                                                             \
    int asi;                                                                  \
                                                                              \
    asi = GET_FIELD(insn, 19, 26);                                            \
    switch (asi) {                                                            \
	case 10: /* User data access */                                       \
	    gen_op_##width##_user();                                          \
	    break;                                                            \
	case 11: /* Supervisor data access */                                 \
	    gen_op_##width##_kernel();                                        \
	    break;                                                            \
        case 0x20 ... 0x2f: /* MMU passthrough */			      \
	    if (is_ld)                                                        \
		gen_op_ld_asi(asi, size, sign);				      \
	    else                                                              \
		gen_op_st_asi(asi, size, sign);				      \
	    break;                                                            \
	default:                                                              \
	    if (is_ld)                                                        \
		gen_op_ld_asi(asi, size, sign);			              \
	    else                                                              \
		gen_op_st_asi(asi, size, sign);				      \
            break;                                                            \
    }                                                                         \
}

#define supervisor(dc) (dc->mem_idx == 1)
#endif
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#endif
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OP_LD_TABLE(ld);
OP_LD_TABLE(st);
OP_LD_TABLE(ldub);
OP_LD_TABLE(lduh);
OP_LD_TABLE(ldsb);
OP_LD_TABLE(ldsh);
OP_LD_TABLE(stb);
OP_LD_TABLE(sth);
OP_LD_TABLE(std);
OP_LD_TABLE(ldstub);
OP_LD_TABLE(swap);
OP_LD_TABLE(ldd);
OP_LD_TABLE(stf);
OP_LD_TABLE(stdf);
OP_LD_TABLE(ldf);
OP_LD_TABLE(lddf);

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#ifdef TARGET_SPARC64
OP_LD_TABLE(ldsw);
OP_LD_TABLE(ldx);
OP_LD_TABLE(stx);
OP_LD_TABLE(cas);
OP_LD_TABLE(casx);
#endif

static inline void gen_movl_imm_TN(int reg, uint32_t imm)
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{
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    gen_op_movl_TN_im[reg](imm);
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}

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static inline void gen_movl_imm_T1(uint32_t val)
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{
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    gen_movl_imm_TN(1, val);
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}

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static inline void gen_movl_imm_T0(uint32_t val)
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{
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    gen_movl_imm_TN(0, val);
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}

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static inline void gen_movl_simm_TN(int reg, int32_t imm)
{
    gen_op_movl_TN_sim[reg](imm);
}

static inline void gen_movl_simm_T1(int32_t val)
{
    gen_movl_simm_TN(1, val);
}

static inline void gen_movl_simm_T0(int32_t val)
{
    gen_movl_simm_TN(0, val);
}

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static inline void gen_movl_reg_TN(int reg, int t)
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{
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    if (reg)
	gen_op_movl_reg_TN[t][reg] ();
    else
	gen_movl_imm_TN(t, 0);
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}

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static inline void gen_movl_reg_T0(int reg)
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{
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    gen_movl_reg_TN(reg, 0);
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}

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static inline void gen_movl_reg_T1(int reg)
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{
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    gen_movl_reg_TN(reg, 1);
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}

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static inline void gen_movl_reg_T2(int reg)
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{
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    gen_movl_reg_TN(reg, 2);
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}

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static inline void gen_movl_TN_reg(int reg, int t)
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{
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    if (reg)
	gen_op_movl_TN_reg[t][reg] ();
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}

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static inline void gen_movl_T0_reg(int reg)
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{
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    gen_movl_TN_reg(reg, 0);
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}

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static inline void gen_movl_T1_reg(int reg)
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{
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    gen_movl_TN_reg(reg, 1);
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}

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static inline void gen_jmp_im(target_ulong pc)
{
#ifdef TARGET_SPARC64
    if (pc == (uint32_t)pc) {
        gen_op_jmp_im(pc);
    } else {
        gen_op_jmp_im64(pc >> 32, pc);
    }
#else
    gen_op_jmp_im(pc);
#endif
}

static inline void gen_movl_npc_im(target_ulong npc)
{
#ifdef TARGET_SPARC64
    if (npc == (uint32_t)npc) {
        gen_op_movl_npc_im(npc);
    } else {
        gen_op_movq_npc_im64(npc >> 32, npc);
    }
#else
    gen_op_movl_npc_im(npc);
#endif
}

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static inline void gen_goto_tb(DisasContext *s, int tb_num, 
                               target_ulong pc, target_ulong npc)
{
    TranslationBlock *tb;

    tb = s->tb;
    if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
        (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
        /* jump to same page: we can use a direct jump */
        if (tb_num == 0)
            gen_op_goto_tb0(TBPARAM(tb));
        else
            gen_op_goto_tb1(TBPARAM(tb));
        gen_jmp_im(pc);
        gen_movl_npc_im(npc);
        gen_op_movl_T0_im((long)tb + tb_num);
        gen_op_exit_tb();
    } else {
        /* jump to another page: currently not optimized */
        gen_jmp_im(pc);
        gen_movl_npc_im(npc);
        gen_op_movl_T0_0();
        gen_op_exit_tb();
    }
}

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static inline void gen_branch2(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
{
    int l1;

    l1 = gen_new_label();

    gen_op_jz_T2_label(l1);

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    gen_goto_tb(dc, 0, pc1, pc1 + 4);
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    gen_set_label(l1);
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    gen_goto_tb(dc, 1, pc2, pc2 + 4);
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}

static inline void gen_branch_a(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
{
    int l1;

    l1 = gen_new_label();

    gen_op_jz_T2_label(l1);

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    gen_goto_tb(dc, 0, pc2, pc1);
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    gen_set_label(l1);
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    gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
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}

static inline void gen_branch(DisasContext *dc, long tb, target_ulong pc, target_ulong npc)
{
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    gen_goto_tb(dc, 0, pc, npc);
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}

static inline void gen_generic_branch(DisasContext *dc, target_ulong npc1, target_ulong npc2)
{
    int l1, l2;

    l1 = gen_new_label();
    l2 = gen_new_label();
    gen_op_jz_T2_label(l1);

    gen_movl_npc_im(npc1);
    gen_op_jmp_label(l2);

    gen_set_label(l1);
    gen_movl_npc_im(npc2);
    gen_set_label(l2);
}

/* call this function before using T2 as it may have been set for a jump */
static inline void flush_T2(DisasContext * dc)
{
    if (dc->npc == JUMP_PC) {
        gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
        dc->npc = DYNAMIC_PC;
    }
}

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static inline void save_npc(DisasContext * dc)
{
    if (dc->npc == JUMP_PC) {
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        gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
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        dc->npc = DYNAMIC_PC;
    } else if (dc->npc != DYNAMIC_PC) {
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        gen_movl_npc_im(dc->npc);
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    }
}

static inline void save_state(DisasContext * dc)
{
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    gen_jmp_im(dc->pc);
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    save_npc(dc);
}

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static inline void gen_mov_pc_npc(DisasContext * dc)
{
    if (dc->npc == JUMP_PC) {
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        gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
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        gen_op_mov_pc_npc();
        dc->pc = DYNAMIC_PC;
    } else if (dc->npc == DYNAMIC_PC) {
        gen_op_mov_pc_npc();
        dc->pc = DYNAMIC_PC;
    } else {
        dc->pc = dc->npc;
    }
}

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static GenOpFunc * const gen_cond[2][16] = {
    {
	gen_op_eval_ba,
	gen_op_eval_be,
	gen_op_eval_ble,
	gen_op_eval_bl,
	gen_op_eval_bleu,
	gen_op_eval_bcs,
	gen_op_eval_bneg,
	gen_op_eval_bvs,
	gen_op_eval_bn,
	gen_op_eval_bne,
	gen_op_eval_bg,
	gen_op_eval_bge,
	gen_op_eval_bgu,
	gen_op_eval_bcc,
	gen_op_eval_bpos,
	gen_op_eval_bvc,
    },
    {
#ifdef TARGET_SPARC64
	gen_op_eval_ba,
	gen_op_eval_xbe,
	gen_op_eval_xble,
	gen_op_eval_xbl,
	gen_op_eval_xbleu,
	gen_op_eval_xbcs,
	gen_op_eval_xbneg,
	gen_op_eval_xbvs,
	gen_op_eval_bn,
	gen_op_eval_xbne,
	gen_op_eval_xbg,
	gen_op_eval_xbge,
	gen_op_eval_xbgu,
	gen_op_eval_xbcc,
	gen_op_eval_xbpos,
	gen_op_eval_xbvc,
#endif
    },
};

static GenOpFunc * const gen_fcond[4][16] = {
    {
	gen_op_eval_ba,
	gen_op_eval_fbne,
	gen_op_eval_fblg,
	gen_op_eval_fbul,
	gen_op_eval_fbl,
	gen_op_eval_fbug,
	gen_op_eval_fbg,
	gen_op_eval_fbu,
	gen_op_eval_bn,
	gen_op_eval_fbe,
	gen_op_eval_fbue,
	gen_op_eval_fbge,
	gen_op_eval_fbuge,
	gen_op_eval_fble,
	gen_op_eval_fbule,
	gen_op_eval_fbo,
    },
#ifdef TARGET_SPARC64
    {
	gen_op_eval_ba,
	gen_op_eval_fbne_fcc1,
	gen_op_eval_fblg_fcc1,
	gen_op_eval_fbul_fcc1,
	gen_op_eval_fbl_fcc1,
	gen_op_eval_fbug_fcc1,
	gen_op_eval_fbg_fcc1,
	gen_op_eval_fbu_fcc1,
	gen_op_eval_bn,
	gen_op_eval_fbe_fcc1,
	gen_op_eval_fbue_fcc1,
	gen_op_eval_fbge_fcc1,
	gen_op_eval_fbuge_fcc1,
	gen_op_eval_fble_fcc1,
	gen_op_eval_fbule_fcc1,
	gen_op_eval_fbo_fcc1,
    },
    {
	gen_op_eval_ba,
	gen_op_eval_fbne_fcc2,
	gen_op_eval_fblg_fcc2,
	gen_op_eval_fbul_fcc2,
	gen_op_eval_fbl_fcc2,
	gen_op_eval_fbug_fcc2,
	gen_op_eval_fbg_fcc2,
	gen_op_eval_fbu_fcc2,
	gen_op_eval_bn,
	gen_op_eval_fbe_fcc2,
	gen_op_eval_fbue_fcc2,
	gen_op_eval_fbge_fcc2,
	gen_op_eval_fbuge_fcc2,
	gen_op_eval_fble_fcc2,
	gen_op_eval_fbule_fcc2,
	gen_op_eval_fbo_fcc2,
    },
    {
	gen_op_eval_ba,
	gen_op_eval_fbne_fcc3,
	gen_op_eval_fblg_fcc3,
	gen_op_eval_fbul_fcc3,
	gen_op_eval_fbl_fcc3,
	gen_op_eval_fbug_fcc3,
	gen_op_eval_fbg_fcc3,
	gen_op_eval_fbu_fcc3,
	gen_op_eval_bn,
	gen_op_eval_fbe_fcc3,
	gen_op_eval_fbue_fcc3,
	gen_op_eval_fbge_fcc3,
	gen_op_eval_fbuge_fcc3,
	gen_op_eval_fble_fcc3,
	gen_op_eval_fbule_fcc3,
	gen_op_eval_fbo_fcc3,
    },
#else
    {}, {}, {},
#endif
};
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#ifdef TARGET_SPARC64
static void gen_cond_reg(int cond)
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{
	switch (cond) {
	case 0x1:
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	    gen_op_eval_brz();
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	    break;
	case 0x2:
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	    gen_op_eval_brlez();
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	    break;
	case 0x3:
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	    gen_op_eval_brlz();
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	    break;
	case 0x5:
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	    gen_op_eval_brnz();
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	    break;
	case 0x6:
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	    gen_op_eval_brgz();
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	    break;
        default:
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	case 0x7:
	    gen_op_eval_brgez();
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	    break;
	}
}
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#endif
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/* XXX: potentially incorrect if dynamic npc */
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static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
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{
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    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
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    target_ulong target = dc->pc + offset;
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    if (cond == 0x0) {
	/* unconditional not taken */
	if (a) {
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	    dc->pc = dc->npc + 4; 
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	    dc->npc = dc->pc + 4;
	} else {
	    dc->pc = dc->npc;
	    dc->npc = dc->pc + 4;
	}
    } else if (cond == 0x8) {
	/* unconditional taken */
	if (a) {
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	    dc->pc = target;
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	    dc->npc = dc->pc + 4;
	} else {
	    dc->pc = dc->npc;
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	    dc->npc = target;
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	}
    } else {
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        flush_T2(dc);
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        gen_cond[cc][cond]();
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	if (a) {
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	    gen_branch_a(dc, (long)dc->tb, target, dc->npc);
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            dc->is_br = 1;
	} else {
            dc->pc = dc->npc;
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            dc->jump_pc[0] = target;
            dc->jump_pc[1] = dc->npc + 4;
            dc->npc = JUMP_PC;
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	}
    }
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}

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/* XXX: potentially incorrect if dynamic npc */
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static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
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{
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
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    target_ulong target = dc->pc + offset;

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    if (cond == 0x0) {
	/* unconditional not taken */
	if (a) {
	    dc->pc = dc->npc + 4;
	    dc->npc = dc->pc + 4;
	} else {
	    dc->pc = dc->npc;
	    dc->npc = dc->pc + 4;
	}
    } else if (cond == 0x8) {
	/* unconditional taken */
	if (a) {
	    dc->pc = target;
	    dc->npc = dc->pc + 4;
	} else {
	    dc->pc = dc->npc;
	    dc->npc = target;
	}
    } else {
        flush_T2(dc);
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        gen_fcond[cc][cond]();
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	if (a) {
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	    gen_branch_a(dc, (long)dc->tb, target, dc->npc);
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            dc->is_br = 1;
	} else {
            dc->pc = dc->npc;
            dc->jump_pc[0] = target;
            dc->jump_pc[1] = dc->npc + 4;
            dc->npc = JUMP_PC;
	}
    }
}

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#ifdef TARGET_SPARC64
/* XXX: potentially incorrect if dynamic npc */
static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
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{
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    unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
    target_ulong target = dc->pc + offset;

    flush_T2(dc);
    gen_cond_reg(cond);
    if (a) {
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	gen_branch_a(dc, (long)dc->tb, target, dc->npc);
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	dc->is_br = 1;
    } else {
	dc->pc = dc->npc;
	dc->jump_pc[0] = target;
	dc->jump_pc[1] = dc->npc + 4;
	dc->npc = JUMP_PC;
    }
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}

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static GenOpFunc * const gen_fcmps[4] = {
    gen_op_fcmps,
    gen_op_fcmps_fcc1,
    gen_op_fcmps_fcc2,
    gen_op_fcmps_fcc3,
};

static GenOpFunc * const gen_fcmpd[4] = {
    gen_op_fcmpd,
    gen_op_fcmpd_fcc1,
    gen_op_fcmpd_fcc2,
    gen_op_fcmpd_fcc3,
};
#endif

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/* before an instruction, dc->pc must be static */
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static void disas_sparc_insn(DisasContext * dc)
{
    unsigned int insn, opc, rs1, rs2, rd;
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    insn = ldl_code(dc->pc);
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    opc = GET_FIELD(insn, 0, 1);
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    rd = GET_FIELD(insn, 2, 6);
    switch (opc) {
    case 0:			/* branches/sethi */
	{
	    unsigned int xop = GET_FIELD(insn, 7, 9);
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	    int32_t target;
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	    switch (xop) {
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#ifdef TARGET_SPARC64
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	    case 0x1:		/* V9 BPcc */
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		{
		    int cc;

		    target = GET_FIELD_SP(insn, 0, 18);
		    target = sign_extend(target, 18);
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		    target <<= 2;
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		    cc = GET_FIELD_SP(insn, 20, 21);
		    if (cc == 0)
			do_branch(dc, target, insn, 0);
		    else if (cc == 2)
			do_branch(dc, target, insn, 1);
		    else
			goto illegal_insn;
		    goto jmp_insn;
		}
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	    case 0x3:		/* V9 BPr */
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		{
		    target = GET_FIELD_SP(insn, 0, 13) | 
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                        (GET_FIELD_SP(insn, 20, 21) << 14);
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		    target = sign_extend(target, 16);
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		    target <<= 2;
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		    rs1 = GET_FIELD(insn, 13, 17);
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		    gen_movl_reg_T0(rs1);
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		    do_branch_reg(dc, target, insn);
		    goto jmp_insn;
		}
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	    case 0x5:		/* V9 FBPcc */
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		{
		    int cc = GET_FIELD_SP(insn, 20, 21);
#if !defined(CONFIG_USER_ONLY)
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		    save_state(dc);
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		    gen_op_trap_ifnofpu();
#endif
		    target = GET_FIELD_SP(insn, 0, 18);
		    target = sign_extend(target, 19);
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		    target <<= 2;
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		    do_fbranch(dc, target, insn, cc);
		    goto jmp_insn;
		}
#endif
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	    case 0x2:		/* BN+x */
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		{
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		    target = GET_FIELD(insn, 10, 31);
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		    target = sign_extend(target, 22);
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		    target <<= 2;
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		    do_branch(dc, target, insn, 0);
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		    goto jmp_insn;
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		}
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	    case 0x6:		/* FBN+x */
		{
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#if !defined(CONFIG_USER_ONLY)
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		    save_state(dc);
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		    gen_op_trap_ifnofpu();
#endif
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		    target = GET_FIELD(insn, 10, 31);
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		    target = sign_extend(target, 22);
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		    target <<= 2;
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		    do_fbranch(dc, target, insn, 0);
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		    goto jmp_insn;
		}
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	    case 0x4:		/* SETHI */
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#define OPTIM
#if defined(OPTIM)
		if (rd) { // nop
#endif
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		    uint32_t value = GET_FIELD(insn, 10, 31);
		    gen_movl_imm_T0(value << 10);
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		    gen_movl_T0_reg(rd);
#if defined(OPTIM)
		}
#endif
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		break;
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	    case 0x0:		/* UNIMPL */
	    default:
                goto illegal_insn;
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	    }
	    break;
	}
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	break;
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    case 1:
	/*CALL*/ {
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	    target_long target = GET_FIELDs(insn, 2, 31) << 2;
1037

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#ifdef TARGET_SPARC64
	    if (dc->pc == (uint32_t)dc->pc) {
		gen_op_movl_T0_im(dc->pc);
	    } else {
		gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
	    }
#else
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	    gen_op_movl_T0_im(dc->pc);
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#endif
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	    gen_movl_T0_reg(15);
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	    target += dc->pc;
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            gen_mov_pc_npc(dc);
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	    dc->npc = target;
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	}
	goto jmp_insn;
    case 2:			/* FPU & Logical Operations */
	{
	    unsigned int xop = GET_FIELD(insn, 7, 12);
	    if (xop == 0x3a) {	/* generate trap */
                int cond;
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                rs1 = GET_FIELD(insn, 13, 17);
                gen_movl_reg_T0(rs1);
		if (IS_IMM) {
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		    rs2 = GET_FIELD(insn, 25, 31);
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#if defined(OPTIM)
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		    if (rs2 != 0) {
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#endif
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			gen_movl_simm_T1(rs2);
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			gen_op_add_T1_T0();
#if defined(OPTIM)
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		    }
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#endif
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                } else {
                    rs2 = GET_FIELD(insn, 27, 31);
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#if defined(OPTIM)
		    if (rs2 != 0) {
#endif
			gen_movl_reg_T1(rs2);
			gen_op_add_T1_T0();
#if defined(OPTIM)
		    }
#endif
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                }
                save_state(dc);
                cond = GET_FIELD(insn, 3, 6);
                if (cond == 0x8) {
                    gen_op_trap_T0();
                    dc->is_br = 1;
                    goto jmp_insn;
1088
                } else if (cond != 0) {
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#ifdef TARGET_SPARC64
		    /* V9 icc/xcc */
		    int cc = GET_FIELD_SP(insn, 11, 12);
		    if (cc == 0)
			gen_cond[0][cond]();
		    else if (cc == 2)
			gen_cond[1][cond]();
		    else
			goto illegal_insn;
#else
		    gen_cond[0][cond]();
#endif
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                    gen_op_trapcc_T0();
                }
            } else if (xop == 0x28) {
                rs1 = GET_FIELD(insn, 13, 17);
                switch(rs1) {
                case 0: /* rdy */
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		    gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
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                    gen_movl_T0_reg(rd);
                    break;
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                case 15: /* stbar / V9 membar */
1111
		    break; /* no effect? */
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#ifdef TARGET_SPARC64
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		case 0x2: /* V9 rdccr */
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                    gen_op_rdccr();
                    gen_movl_T0_reg(rd);
                    break;
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		case 0x3: /* V9 rdasi */
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		    gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
                    gen_movl_T0_reg(rd);
                    break;
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		case 0x4: /* V9 rdtick */
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                    gen_op_rdtick();
                    gen_movl_T0_reg(rd);
                    break;
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		case 0x5: /* V9 rdpc */
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		    if (dc->pc == (uint32_t)dc->pc) {
			gen_op_movl_T0_im(dc->pc);
		    } else {
			gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
		    }
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		    gen_movl_T0_reg(rd);
		    break;
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		case 0x6: /* V9 rdfprs */
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		    gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
                    gen_movl_T0_reg(rd);
                    break;
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		case 0x17: /* Tick compare */
		    gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
                    gen_movl_T0_reg(rd);
                    break;
		case 0x18: /* System tick */
                    gen_op_rdtick(); // XXX
                    gen_movl_T0_reg(rd);
                    break;
		case 0x19: /* System tick compare */
		    gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
                    gen_movl_T0_reg(rd);
                    break;
		case 0x10: /* Performance Control */
		case 0x11: /* Performance Instrumentation Counter */
		case 0x12: /* Dispatch Control */
		case 0x13: /* Graphics Status */
		case 0x14: /* Softint set, WO */
		case 0x15: /* Softint clear, WO */
		case 0x16: /* Softint write */
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#endif
                default:
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                    goto illegal_insn;
                }
1160
#if !defined(CONFIG_USER_ONLY)
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#ifndef TARGET_SPARC64
            } else if (xop == 0x29) { /* rdpsr / V9 unimp */
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		if (!supervisor(dc))
		    goto priv_insn;
                gen_op_rdpsr();
                gen_movl_T0_reg(rd);
                break;
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#endif
            } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
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		if (!supervisor(dc))
		    goto priv_insn;
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#ifdef TARGET_SPARC64
                rs1 = GET_FIELD(insn, 13, 17);
		switch (rs1) {
		case 0: // tpc
		    gen_op_rdtpc();
		    break;
		case 1: // tnpc
		    gen_op_rdtnpc();
		    break;
		case 2: // tstate
		    gen_op_rdtstate();
		    break;
		case 3: // tt
		    gen_op_rdtt();
		    break;
		case 4: // tick
		    gen_op_rdtick();
		    break;
		case 5: // tba
		    gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
		    break;
		case 6: // pstate
		    gen_op_rdpstate();
		    break;
		case 7: // tl
		    gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
		    break;
		case 8: // pil
		    gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
		    break;
		case 9: // cwp
		    gen_op_rdcwp();
		    break;
		case 10: // cansave
		    gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
		    break;
		case 11: // canrestore
		    gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
		    break;
		case 12: // cleanwin
		    gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
		    break;
		case 13: // otherwin
		    gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
		    break;
		case 14: // wstate
		    gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
		    break;
		case 31: // ver
		    gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
		    break;
		case 15: // fq
		default:
		    goto illegal_insn;
		}
#else
		gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
#endif
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                gen_movl_T0_reg(rd);
                break;
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            } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
#ifdef TARGET_SPARC64
		gen_op_flushw();
#else
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		if (!supervisor(dc))
		    goto priv_insn;
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		gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
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                gen_movl_T0_reg(rd);
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#endif
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                break;
#endif
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	    } else if (xop == 0x34) {	/* FPU Operations */
#if !defined(CONFIG_USER_ONLY)
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		save_state(dc);
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		gen_op_trap_ifnofpu();
#endif
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                rs1 = GET_FIELD(insn, 13, 17);
	        rs2 = GET_FIELD(insn, 27, 31);
	        xop = GET_FIELD(insn, 18, 26);
		switch (xop) {
		    case 0x1: /* fmovs */
                	gen_op_load_fpr_FT0(rs2);
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x5: /* fnegs */
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fnegs();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x9: /* fabss */
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fabss();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x29: /* fsqrts */
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fsqrts();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x2a: /* fsqrtd */
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                	gen_op_load_fpr_DT1(DFPREG(rs2));
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			gen_op_fsqrtd();
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			gen_op_store_DT0_fpr(DFPREG(rd));
1275
			break;
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		    case 0x2b: /* fsqrtq */
		        goto nfpu_insn;
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		    case 0x41:
                	gen_op_load_fpr_FT0(rs1);
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fadds();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x42:
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                	gen_op_load_fpr_DT0(DFPREG(rs1));
                	gen_op_load_fpr_DT1(DFPREG(rs2));
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			gen_op_faddd();
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			gen_op_store_DT0_fpr(DFPREG(rd));
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			break;
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		    case 0x43: /* faddq */
		        goto nfpu_insn;
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		    case 0x45:
                	gen_op_load_fpr_FT0(rs1);
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fsubs();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x46:
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                	gen_op_load_fpr_DT0(DFPREG(rs1));
                	gen_op_load_fpr_DT1(DFPREG(rs2));
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			gen_op_fsubd();
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			gen_op_store_DT0_fpr(DFPREG(rd));
1303
			break;
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		    case 0x47: /* fsubq */
		        goto nfpu_insn;
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		    case 0x49:
                	gen_op_load_fpr_FT0(rs1);
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fmuls();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x4a:
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                	gen_op_load_fpr_DT0(DFPREG(rs1));
                	gen_op_load_fpr_DT1(DFPREG(rs2));
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			gen_op_fmuld();
			gen_op_store_DT0_fpr(rd);
			break;
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		    case 0x4b: /* fmulq */
		        goto nfpu_insn;
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		    case 0x4d:
                	gen_op_load_fpr_FT0(rs1);
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fdivs();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x4e:
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                	gen_op_load_fpr_DT0(DFPREG(rs1));
			gen_op_load_fpr_DT1(DFPREG(rs2));
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			gen_op_fdivd();
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			gen_op_store_DT0_fpr(DFPREG(rd));
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			break;
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		    case 0x4f: /* fdivq */
		        goto nfpu_insn;
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		    case 0x69:
                	gen_op_load_fpr_FT0(rs1);
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fsmuld();
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			gen_op_store_DT0_fpr(DFPREG(rd));
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			break;
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		    case 0x6e: /* fdmulq */
		        goto nfpu_insn;
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		    case 0xc4:
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fitos();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0xc6:
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                	gen_op_load_fpr_DT1(DFPREG(rs2));
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			gen_op_fdtos();
			gen_op_store_FT0_fpr(rd);
			break;
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		    case 0xc7: /* fqtos */
		        goto nfpu_insn;
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		    case 0xc8:
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fitod();
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			gen_op_store_DT0_fpr(DFPREG(rd));
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			break;
		    case 0xc9:
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fstod();
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			gen_op_store_DT0_fpr(DFPREG(rd));
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			break;
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		    case 0xcb: /* fqtod */
		        goto nfpu_insn;
		    case 0xcc: /* fitoq */
		        goto nfpu_insn;
		    case 0xcd: /* fstoq */
		        goto nfpu_insn;
		    case 0xce: /* fdtoq */
		        goto nfpu_insn;
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		    case 0xd1:
                	gen_op_load_fpr_FT1(rs2);
			gen_op_fstoi();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0xd2:
                	gen_op_load_fpr_DT1(rs2);
			gen_op_fdtoi();
			gen_op_store_FT0_fpr(rd);
			break;
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		    case 0xd3: /* fqtoi */
		        goto nfpu_insn;
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#ifdef TARGET_SPARC64
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		    case 0x2: /* V9 fmovd */
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                	gen_op_load_fpr_DT0(DFPREG(rs2));
			gen_op_store_DT0_fpr(DFPREG(rd));
			break;
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		    case 0x6: /* V9 fnegd */
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                	gen_op_load_fpr_DT1(DFPREG(rs2));
			gen_op_fnegd();
			gen_op_store_DT0_fpr(DFPREG(rd));
			break;
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		    case 0xa: /* V9 fabsd */
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                	gen_op_load_fpr_DT1(DFPREG(rs2));
			gen_op_fabsd();
			gen_op_store_DT0_fpr(DFPREG(rd));
			break;
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		    case 0x81: /* V9 fstox */
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                	gen_op_load_fpr_FT1(rs2);
			gen_op_fstox();
			gen_op_store_DT0_fpr(DFPREG(rd));
			break;
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		    case 0x82: /* V9 fdtox */
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                	gen_op_load_fpr_DT1(DFPREG(rs2));
			gen_op_fdtox();
			gen_op_store_DT0_fpr(DFPREG(rd));
			break;
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		    case 0x84: /* V9 fxtos */
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                	gen_op_load_fpr_DT1(DFPREG(rs2));
			gen_op_fxtos();
			gen_op_store_FT0_fpr(rd);
			break;
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		    case 0x88: /* V9 fxtod */
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                	gen_op_load_fpr_DT1(DFPREG(rs2));
			gen_op_fxtod();
			gen_op_store_DT0_fpr(DFPREG(rd));
			break;
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		    case 0x3: /* V9 fmovq */
		    case 0x7: /* V9 fnegq */
		    case 0xb: /* V9 fabsq */
		    case 0x83: /* V9 fqtox */
		    case 0x8c: /* V9 fxtoq */
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		        goto nfpu_insn;
#endif
		    default:
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                	goto illegal_insn;
		}
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	    } else if (xop == 0x35) {	/* FPU Operations */
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#ifdef TARGET_SPARC64
		int cond;
#endif
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#if !defined(CONFIG_USER_ONLY)
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		save_state(dc);
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		gen_op_trap_ifnofpu();
#endif
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                rs1 = GET_FIELD(insn, 13, 17);
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	        rs2 = GET_FIELD(insn, 27, 31);
	        xop = GET_FIELD(insn, 18, 26);
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#ifdef TARGET_SPARC64
		if ((xop & 0x11f) == 0x005) { // V9 fmovsr
		    cond = GET_FIELD_SP(insn, 14, 17);
		    gen_op_load_fpr_FT0(rd);
		    gen_op_load_fpr_FT1(rs2);
		    rs1 = GET_FIELD(insn, 13, 17);
		    gen_movl_reg_T0(rs1);
		    flush_T2(dc);
		    gen_cond_reg(cond);
		    gen_op_fmovs_cc();
		    gen_op_store_FT0_fpr(rd);
		    break;
		} else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
		    cond = GET_FIELD_SP(insn, 14, 17);
		    gen_op_load_fpr_DT0(rd);
		    gen_op_load_fpr_DT1(rs2);
		    flush_T2(dc);
		    rs1 = GET_FIELD(insn, 13, 17);
		    gen_movl_reg_T0(rs1);
		    gen_cond_reg(cond);
		    gen_op_fmovs_cc();
		    gen_op_store_DT0_fpr(rd);
		    break;
		} else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
		    goto nfpu_insn;
		}
#endif
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		switch (xop) {
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</