eepro100.c 69.2 KB
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/*
 * QEMU i8255x (PRO100) emulation
 *
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 * Copyright (C) 2006-2011 Stefan Weil
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 *
 * Portions of the code are copies from grub / etherboot eepro100.c
 * and linux e100.c.
 *
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 * This program is free software: you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation, either version 2 of the License, or
 * (at your option) version 3 or any later version.
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 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
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 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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 *
 * Tested features (i82559):
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 *      PXE boot (i386 guest, i386 / mips / mipsel / ppc host) ok
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 *      Linux networking (i386) ok
 *
 * Untested:
 *      Windows networking
 *
 * References:
 *
 * Intel 8255x 10/100 Mbps Ethernet Controller Family
 * Open Source Software Developer Manual
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 *
 * TODO:
 *      * PHY emulation should be separated from nic emulation.
 *        Most nic emulations could share the same phy code.
 *      * i82550 is untested. It is programmed like the i82559.
 *      * i82562 is untested. It is programmed like the i82559.
 *      * Power management (i82558 and later) is not implemented.
 *      * Wake-on-LAN is not implemented.
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 */

#include <stddef.h>             /* offsetof */
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#include "hw.h"
#include "pci.h"
#include "net.h"
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#include "eeprom93xx.h"
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#include "sysemu.h"
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/* QEMU sends frames smaller than 60 bytes to ethernet nics.
 * Such frames are rejected by real nics and their emulations.
 * To avoid this behaviour, other nic emulations pad received
 * frames. The following definition enables this padding for
 * eepro100, too. We keep the define around in case it might
 * become useful the future if the core networking is ever
 * changed to pad short packets itself. */
#define CONFIG_PAD_RECEIVED_FRAMES

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#define KiB 1024

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/* Debug EEPRO100 card. */
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#if 0
# define DEBUG_EEPRO100
#endif
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#ifdef DEBUG_EEPRO100
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#define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
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#else
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#define logout(fmt, ...) ((void)0)
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#endif

/* Set flags to 0 to disable debug output. */
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#define INT     1       /* interrupt related actions */
#define MDI     1       /* mdi related actions */
#define OTHER   1
#define RXTX    1
#define EEPROM  1       /* eeprom related actions */
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#define TRACE(flag, command) ((flag) ? (command) : (void)0)

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#define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
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#define MAX_ETH_FRAME_SIZE 1514

/* This driver supports several different devices which are declared here. */
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#define i82550          0x82550
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#define i82551          0x82551
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#define i82557A         0x82557a
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#define i82557B         0x82557b
#define i82557C         0x82557c
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#define i82558A         0x82558a
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#define i82558B         0x82558b
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#define i82559A         0x82559a
#define i82559B         0x82559b
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#define i82559C         0x82559c
#define i82559ER        0x82559e
#define i82562          0x82562
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#define i82801          0x82801
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/* Use 64 word EEPROM. TODO: could be a runtime option. */
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#define EEPROM_SIZE     64

#define PCI_MEM_SIZE            (4 * KiB)
#define PCI_IO_SIZE             64
#define PCI_FLASH_SIZE          (128 * KiB)

#define BIT(n) (1 << (n))
#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)

/* The SCB accepts the following controls for the Tx and Rx units: */
#define  CU_NOP         0x0000  /* No operation. */
#define  CU_START       0x0010  /* CU start. */
#define  CU_RESUME      0x0020  /* CU resume. */
#define  CU_STATSADDR   0x0040  /* Load dump counters address. */
#define  CU_SHOWSTATS   0x0050  /* Dump statistical counters. */
#define  CU_CMD_BASE    0x0060  /* Load CU base address. */
#define  CU_DUMPSTATS   0x0070  /* Dump and reset statistical counters. */
#define  CU_SRESUME     0x00a0  /* CU static resume. */

#define  RU_NOP         0x0000
#define  RX_START       0x0001
#define  RX_RESUME      0x0002
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#define  RU_ABORT       0x0004
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#define  RX_ADDR_LOAD   0x0006
#define  RX_RESUMENR    0x0007
#define INT_MASK        0x0100
#define DRVR_INT        0x0200  /* Driver generated interrupt. */

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typedef struct {
    PCIDeviceInfo pci;
    uint32_t device;
    uint16_t device_id;
    uint8_t revision;
    uint8_t stats_size;
    bool has_extended_tcb_support;
    bool power_management;
} E100PCIDeviceInfo;

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/* Offsets to the various registers.
   All accesses need not be longword aligned. */
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typedef enum {
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    SCBStatus = 0,              /* Status Word. */
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    SCBAck = 1,
    SCBCmd = 2,                 /* Rx/Command Unit command and status. */
    SCBIntmask = 3,
    SCBPointer = 4,             /* General purpose pointer. */
    SCBPort = 8,                /* Misc. commands and operands.  */
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    SCBflash = 12,              /* Flash memory control. */
    SCBeeprom = 14,             /* EEPROM control. */
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    SCBCtrlMDI = 16,            /* MDI interface control. */
    SCBEarlyRx = 20,            /* Early receive byte count. */
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    SCBFlow = 24,               /* Flow Control. */
    SCBpmdr = 27,               /* Power Management Driver. */
    SCBgctrl = 28,              /* General Control. */
    SCBgstat = 29,              /* General Status. */
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} E100RegisterOffset;
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/* A speedo3 transmit buffer descriptor with two buffers... */
typedef struct {
    uint16_t status;
    uint16_t command;
    uint32_t link;              /* void * */
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    uint32_t tbd_array_addr;    /* transmit buffer descriptor array address. */
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    uint16_t tcb_bytes;         /* transmit command block byte count (in lower 14 bits */
    uint8_t tx_threshold;       /* transmit threshold */
    uint8_t tbd_count;          /* TBD number */
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#if 0
    /* This constitutes two "TBD" entries: hdr and data */
    uint32_t tx_buf_addr0;  /* void *, header of frame to be transmitted.  */
    int32_t  tx_buf_size0;  /* Length of Tx hdr. */
    uint32_t tx_buf_addr1;  /* void *, data to be transmitted.  */
    int32_t  tx_buf_size1;  /* Length of Tx data. */
#endif
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} eepro100_tx_t;
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/* Receive frame descriptor. */
typedef struct {
    int16_t status;
    uint16_t command;
    uint32_t link;              /* struct RxFD * */
    uint32_t rx_buf_addr;       /* void * */
    uint16_t count;
    uint16_t size;
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    /* Ethernet frame data follows. */
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} eepro100_rx_t;
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typedef enum {
    COMMAND_EL = BIT(15),
    COMMAND_S = BIT(14),
    COMMAND_I = BIT(13),
    COMMAND_NC = BIT(4),
    COMMAND_SF = BIT(3),
    COMMAND_CMD = BITS(2, 0),
} scb_command_bit;

typedef enum {
    STATUS_C = BIT(15),
    STATUS_OK = BIT(13),
} scb_status_bit;

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typedef struct {
    uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
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             tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
             tx_multiple_collisions, tx_total_collisions;
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    uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
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             rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
             rx_short_frame_errors;
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    uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
    uint16_t xmt_tco_frames, rcv_tco_frames;
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    /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
    uint32_t reserved[4];
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} eepro100_stats_t;
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typedef enum {
    cu_idle = 0,
    cu_suspended = 1,
    cu_active = 2,
    cu_lpq_active = 2,
    cu_hqp_active = 3
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} cu_state_t;
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typedef enum {
    ru_idle = 0,
    ru_suspended = 1,
    ru_no_resources = 2,
    ru_ready = 4
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} ru_state_t;
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typedef struct {
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    PCIDevice dev;
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    /* Hash register (multicast mask array, multiple individual addresses). */
    uint8_t mult[8];
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    int mmio_index;
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    NICState *nic;
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    NICConf conf;
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    uint8_t scb_stat;           /* SCB stat/ack byte */
    uint8_t int_stat;           /* PCI interrupt status */
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    /* region must not be saved by nic_save. */
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    uint32_t region1;           /* PCI region 1 address */
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    uint16_t mdimem[32];
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    eeprom_t *eeprom;
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    uint32_t device;            /* device variant */
    uint32_t pointer;
    /* (cu_base + cu_offset) address the next command block in the command block list. */
    uint32_t cu_base;           /* CU base address */
    uint32_t cu_offset;         /* CU address offset */
    /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
    uint32_t ru_base;           /* RU base address */
    uint32_t ru_offset;         /* RU address offset */
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    uint32_t statsaddr;         /* pointer to eepro100_stats_t */
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    /* Temporary status information (no need to save these values),
     * used while processing CU commands. */
    eepro100_tx_t tx;           /* transmit buffer descriptor */
    uint32_t cb_address;        /* = cu_base + cu_offset */

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    /* Statistical counters. Also used for wake-up packet (i82559). */
    eepro100_stats_t statistics;

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    /* Data in mem is always in the byte order of the controller (le).
     * It must be dword aligned to allow direct access to 32 bit values. */
    uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8)));;

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    /* Configuration bytes. */
    uint8_t configuration[22];

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    /* vmstate for each particular nic */
    VMStateDescription *vmstate;
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    /* Quasi static device properties (no need to save them). */
    uint16_t stats_size;
    bool has_extended_tcb_support;
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} EEPRO100State;

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/* Word indices in EEPROM. */
typedef enum {
    EEPROM_CNFG_MDIX  = 0x03,
    EEPROM_ID         = 0x05,
    EEPROM_PHY_ID     = 0x06,
    EEPROM_VENDOR_ID  = 0x0c,
    EEPROM_CONFIG_ASF = 0x0d,
    EEPROM_DEVICE_ID  = 0x23,
    EEPROM_SMBUS_ADDR = 0x90,
} EEPROMOffset;

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/* Bit values for EEPROM ID word. */
typedef enum {
    EEPROM_ID_MDM = BIT(0),     /* Modem */
    EEPROM_ID_STB = BIT(1),     /* Standby Enable */
    EEPROM_ID_WMR = BIT(2),     /* ??? */
    EEPROM_ID_WOL = BIT(5),     /* Wake on LAN */
    EEPROM_ID_DPD = BIT(6),     /* Deep Power Down */
    EEPROM_ID_ALT = BIT(7),     /* */
    /* BITS(10, 8) device revision */
    EEPROM_ID_BD = BIT(11),     /* boot disable */
    EEPROM_ID_ID = BIT(13),     /* id bit */
    /* BITS(15, 14) signature */
    EEPROM_ID_VALID = BIT(14),  /* signature for valid eeprom */
} eeprom_id_bit;

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/* Default values for MDI (PHY) registers */
static const uint16_t eepro100_mdi_default[] = {
    /* MDI Registers 0 - 6, 7 */
    0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
    /* MDI Registers 8 - 15 */
    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
    /* MDI Registers 16 - 31 */
    0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
};

/* Readonly mask for MDI (PHY) registers */
static const uint16_t eepro100_mdi_mask[] = {
    0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
    0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
    0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
};

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/* Read a 16 bit little endian value from physical memory. */
static uint16_t e100_ldw_le_phys(target_phys_addr_t addr)
{
    /* Load 16 bit (little endian) word from emulated hardware. */
    uint16_t val;
    cpu_physical_memory_read(addr, &val, sizeof(val));
    return le16_to_cpu(val);
}

/* Read a 32 bit little endian value from physical memory. */
static uint32_t e100_ldl_le_phys(target_phys_addr_t addr)
{
    /* Load 32 bit (little endian) word from emulated hardware. */
    uint32_t val;
    cpu_physical_memory_read(addr, &val, sizeof(val));
    return le32_to_cpu(val);
}

/* Write a 16 bit little endian value to physical memory. */
static void e100_stw_le_phys(target_phys_addr_t addr, uint16_t val)
{
    val = cpu_to_le16(val);
    cpu_physical_memory_write(addr, &val, sizeof(val));
}

/* Write a 32 bit little endian value to physical memory. */
static void e100_stl_le_phys(target_phys_addr_t addr, uint32_t val)
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{
    val = cpu_to_le32(val);
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    cpu_physical_memory_write(addr, &val, sizeof(val));
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}

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#define POLYNOMIAL 0x04c11db6

/* From FreeBSD */
/* XXX: optimize */
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static unsigned compute_mcast_idx(const uint8_t * ep)
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{
    uint32_t crc;
    int carry, i, j;
    uint8_t b;

    crc = 0xffffffff;
    for (i = 0; i < 6; i++) {
        b = *ep++;
        for (j = 0; j < 8; j++) {
            carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
            crc <<= 1;
            b >>= 1;
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            if (carry) {
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                crc = ((crc ^ POLYNOMIAL) | carry);
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            }
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        }
    }
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    return (crc & BITS(7, 2)) >> 2;
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}

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/* Read a 16 bit control/status (CSR) register. */
static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
{
    assert(!((uintptr_t)&s->mem[addr] & 1));
    return le16_to_cpup((uint16_t *)&s->mem[addr]);
}

/* Read a 32 bit control/status (CSR) register. */
static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr)
{
    assert(!((uintptr_t)&s->mem[addr] & 3));
    return le32_to_cpup((uint32_t *)&s->mem[addr]);
}

/* Write a 16 bit control/status (CSR) register. */
static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr,
                            uint16_t val)
{
    assert(!((uintptr_t)&s->mem[addr] & 1));
    cpu_to_le16w((uint16_t *)&s->mem[addr], val);
}

/* Read a 32 bit control/status (CSR) register. */
static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr,
                            uint32_t val)
{
    assert(!((uintptr_t)&s->mem[addr] & 3));
    cpu_to_le32w((uint32_t *)&s->mem[addr], val);
}

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#if defined(DEBUG_EEPRO100)
static const char *nic_dump(const uint8_t * buf, unsigned size)
{
    static char dump[3 * 16 + 1];
    char *p = &dump[0];
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    if (size > 16) {
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        size = 16;
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    }
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    while (size-- > 0) {
        p += sprintf(p, " %02x", *buf++);
    }
    return dump;
}
#endif                          /* DEBUG_EEPRO100 */

enum scb_stat_ack {
    stat_ack_not_ours = 0x00,
    stat_ack_sw_gen = 0x04,
    stat_ack_rnr = 0x10,
    stat_ack_cu_idle = 0x20,
    stat_ack_frame_rx = 0x40,
    stat_ack_cu_cmd_done = 0x80,
    stat_ack_not_present = 0xFF,
    stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
    stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
};

static void disable_interrupt(EEPRO100State * s)
{
    if (s->int_stat) {
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        TRACE(INT, logout("interrupt disabled\n"));
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        qemu_irq_lower(s->dev.irq[0]);
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        s->int_stat = 0;
    }
}

static void enable_interrupt(EEPRO100State * s)
{
    if (!s->int_stat) {
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        TRACE(INT, logout("interrupt enabled\n"));
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        qemu_irq_raise(s->dev.irq[0]);
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        s->int_stat = 1;
    }
}

static void eepro100_acknowledge(EEPRO100State * s)
{
    s->scb_stat &= ~s->mem[SCBAck];
    s->mem[SCBAck] = s->scb_stat;
    if (s->scb_stat == 0) {
        disable_interrupt(s);
    }
}

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static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
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{
    uint8_t mask = ~s->mem[SCBIntmask];
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    s->mem[SCBAck] |= status;
    status = s->scb_stat = s->mem[SCBAck];
    status &= (mask | 0x0f);
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#if 0
    status &= (~s->mem[SCBIntmask] | 0x0xf);
#endif
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    if (status && (mask & 0x01)) {
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        /* SCB mask and SCB Bit M do not disable interrupt. */
        enable_interrupt(s);
    } else if (s->int_stat) {
        disable_interrupt(s);
    }
}

static void eepro100_cx_interrupt(EEPRO100State * s)
{
    /* CU completed action command. */
    /* Transmit not ok (82557 only, not in emulation). */
    eepro100_interrupt(s, 0x80);
}

static void eepro100_cna_interrupt(EEPRO100State * s)
{
    /* CU left the active state. */
    eepro100_interrupt(s, 0x20);
}

static void eepro100_fr_interrupt(EEPRO100State * s)
{
    /* RU received a complete frame. */
    eepro100_interrupt(s, 0x40);
}

static void eepro100_rnr_interrupt(EEPRO100State * s)
{
    /* RU is not ready. */
    eepro100_interrupt(s, 0x10);
}

static void eepro100_mdi_interrupt(EEPRO100State * s)
{
    /* MDI completed read or write cycle. */
    eepro100_interrupt(s, 0x08);
}

static void eepro100_swi_interrupt(EEPRO100State * s)
{
    /* Software has requested an interrupt. */
    eepro100_interrupt(s, 0x04);
}

#if 0
static void eepro100_fcp_interrupt(EEPRO100State * s)
{
    /* Flow control pause interrupt (82558 and later). */
    eepro100_interrupt(s, 0x01);
}
#endif

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static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device)
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{
    uint32_t device = s->device;
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    uint8_t *pci_conf = s->dev.config;
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    TRACE(OTHER, logout("%p\n", s));
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    /* PCI Vendor ID */
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    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
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    /* PCI Device ID */
    pci_config_set_device_id(pci_conf, e100_device->device_id);
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    /* PCI Status */
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    pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
                                        PCI_STATUS_FAST_BACK);
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    /* PCI Revision ID */
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    pci_config_set_revision(pci_conf, e100_device->revision);
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    pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
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    /* PCI Latency Timer */
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    pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20);   /* latency timer = 32 clocks */
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    /* Capability Pointer is set by PCI framework. */
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    /* Interrupt Line */
    /* Interrupt Pin */
    pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1);      /* interrupt pin A */
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    /* Minimum Grant */
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    pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
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    /* Maximum Latency */
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    pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
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    s->stats_size = e100_device->stats_size;
    s->has_extended_tcb_support = e100_device->has_extended_tcb_support;

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    switch (device) {
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    case i82550:
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    case i82551:
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    case i82557A:
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    case i82557B:
    case i82557C:
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    case i82558A:
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    case i82558B:
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    case i82559A:
    case i82559B:
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    case i82559ER:
    case i82562:
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    case i82801:
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        break;
    case i82559C:
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#if EEPROM_SIZE > 0
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        pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_INTEL);
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        pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0040);
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#endif
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        break;
    default:
        logout("Device %X is undefined!\n", device);
    }

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    /* Standard TxCB. */
    s->configuration[6] |= BIT(4);

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    /* Standard statistical counters. */
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    s->configuration[6] |= BIT(5);

    if (s->stats_size == 80) {
        /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
        if (s->configuration[6] & BIT(2)) {
            /* TCO statistical counters. */
            assert(s->configuration[6] & BIT(5));
        } else {
            if (s->configuration[6] & BIT(5)) {
                /* No extended statistical counters, i82557 compatible. */
                s->stats_size = 64;
            } else {
                /* i82558 compatible. */
                s->stats_size = 76;
            }
        }
    } else {
        if (s->configuration[6] & BIT(5)) {
            /* No extended statistical counters. */
            s->stats_size = 64;
        }
    }
    assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));

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    if (e100_device->power_management) {
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        /* Power Management Capabilities */
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        int cfg_offset = 0xdc;
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        int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
                                   cfg_offset, PCI_PM_SIZEOF);
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        assert(r >= 0);
        pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
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#if 0 /* TODO: replace dummy code for power management emulation. */
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        /* TODO: Power Management Control / Status. */
        pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
        /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
        pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
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#endif
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    }

#if EEPROM_SIZE > 0
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    if (device == i82557C || device == i82558B || device == i82559C) {
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        /*
        TODO: get vendor id from EEPROM for i82557C or later.
        TODO: get device id from EEPROM for i82557C or later.
        TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
        TODO: header type is determined by EEPROM for i82559.
        TODO: get subsystem id from EEPROM for i82557C or later.
        TODO: get subsystem vendor id from EEPROM for i82557C or later.
        TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
        TODO: capability pointer depends on EEPROM for i82558.
        */
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        logout("Get device id and revision from EEPROM!!!\n");
    }
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#endif /* EEPROM_SIZE > 0 */
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}

static void nic_selective_reset(EEPRO100State * s)
{
    size_t i;
    uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
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#if 0
    eeprom93xx_reset(s->eeprom);
#endif
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    memcpy(eeprom_contents, s->conf.macaddr.a, 6);
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    eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
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    if (s->device == i82557B || s->device == i82557C)
        eeprom_contents[5] = 0x0100;
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    eeprom_contents[EEPROM_PHY_ID] = 1;
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    uint16_t sum = 0;
    for (i = 0; i < EEPROM_SIZE - 1; i++) {
        sum += eeprom_contents[i];
    }
    eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
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    TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
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    memset(s->mem, 0, sizeof(s->mem));
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    e100_write_reg4(s, SCBCtrlMDI, BIT(21));
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    assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
    memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
}

static void nic_reset(void *opaque)
{
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    EEPRO100State *s = opaque;
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    TRACE(OTHER, logout("%p\n", s));
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    /* TODO: Clearing of hash register for selective reset, too? */
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    memset(&s->mult[0], 0, sizeof(s->mult));
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    nic_selective_reset(s);
}

#if defined(DEBUG_EEPRO100)
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static const char * const e100_reg[PCI_IO_SIZE / 4] = {
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    "Command/Status",
    "General Pointer",
    "Port",
    "EEPROM/Flash Control",
    "MDI Control",
    "Receive DMA Byte Count",
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    "Flow Control",
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    "General Status/Control"
};

static char *regname(uint32_t addr)
{
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    static char buf[32];
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    if (addr < PCI_IO_SIZE) {
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        const char *r = e100_reg[addr / 4];
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        if (r != 0) {
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            snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
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        } else {
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            snprintf(buf, sizeof(buf), "0x%02x", addr);
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        }
    } else {
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        snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
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    }
    return buf;
}
#endif                          /* DEBUG_EEPRO100 */

/*****************************************************************************
 *
 * Command emulation.
 *
 ****************************************************************************/

#if 0
static uint16_t eepro100_read_command(EEPRO100State * s)
{
    uint16_t val = 0xffff;
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    TRACE(OTHER, logout("val=0x%04x\n", val));
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    return val;
}
#endif

/* Commands that can be put in a command list entry. */
enum commands {
    CmdNOp = 0,
    CmdIASetup = 1,
    CmdConfigure = 2,
    CmdMulticastList = 3,
    CmdTx = 4,
    CmdTDR = 5,                 /* load microcode */
    CmdDump = 6,
    CmdDiagnose = 7,

    /* And some extra flags: */
    CmdSuspend = 0x4000,        /* Suspend after completion. */
    CmdIntr = 0x2000,           /* Interrupt after completion. */
    CmdTxFlex = 0x0008,         /* Use "Flexible mode" for CmdTx command. */
};

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static cu_state_t get_cu_state(EEPRO100State * s)
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{
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    return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
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}

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static void set_cu_state(EEPRO100State * s, cu_state_t state)
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{
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    s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
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}

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static ru_state_t get_ru_state(EEPRO100State * s)
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{
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    return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
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}

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static void set_ru_state(EEPRO100State * s, ru_state_t state)
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{
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    s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
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}

static void dump_statistics(EEPRO100State * s)
{
    /* Dump statistical data. Most data is never changed by the emulation
     * and always 0, so we first just copy the whole block and then those
     * values which really matter.
     * Number of data should check configuration!!!
     */
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    cpu_physical_memory_write(s->statsaddr, &s->statistics, s->stats_size);
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    e100_stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
    e100_stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
    e100_stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
    e100_stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
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#if 0
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    e100_stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
    e100_stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
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    missing("CU dump statistical counters");
#endif
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}

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static void read_cb(EEPRO100State *s)
{
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    cpu_physical_memory_read(s->cb_address, &s->tx, sizeof(s->tx));
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    s->tx.status = le16_to_cpu(s->tx.status);
    s->tx.command = le16_to_cpu(s->tx.command);
    s->tx.link = le32_to_cpu(s->tx.link);
    s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
    s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
}

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static void tx_command(EEPRO100State *s)
{
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    uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
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    uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
    /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
    uint8_t buf[2600];
    uint16_t size = 0;
    uint32_t tbd_address = s->cb_address + 0x10;
    TRACE(RXTX, logout
        ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
         tbd_array, tcb_bytes, s->tx.tbd_count));

    if (tcb_bytes > 2600) {
        logout("TCB byte count too large, using 2600\n");
        tcb_bytes = 2600;
    }
    if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
        logout
            ("illegal values of TBD array address and TCB byte count!\n");
    }
    assert(tcb_bytes <= sizeof(buf));
    while (size < tcb_bytes) {
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        uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address);
        uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
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#if 0
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        uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
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#endif
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        tbd_address += 8;
        TRACE(RXTX, logout
            ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
             tx_buffer_address, tx_buffer_size));
        tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
        cpu_physical_memory_read(tx_buffer_address, &buf[size],
                                 tx_buffer_size);
        size += tx_buffer_size;
    }
    if (tbd_array == 0xffffffff) {
        /* Simplified mode. Was already handled by code above. */
    } else {
        /* Flexible mode. */
        uint8_t tbd_count = 0;
        if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
            /* Extended Flexible TCB. */
            for (; tbd_count < 2; tbd_count++) {
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                uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address);
                uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
                uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
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                tbd_address += 8;
                TRACE(RXTX, logout
                    ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
                     tx_buffer_address, tx_buffer_size));
                tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
                cpu_physical_memory_read(tx_buffer_address, &buf[size],
                                         tx_buffer_size);
                size += tx_buffer_size;
                if (tx_buffer_el & 1) {
                    break;
                }
            }
        }
        tbd_address = tbd_array;
        for (; tbd_count < s->tx.tbd_count; tbd_count++) {
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            uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address);
            uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
            uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
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            tbd_address += 8;
            TRACE(RXTX, logout
                ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
                 tx_buffer_address, tx_buffer_size));
            tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
            cpu_physical_memory_read(tx_buffer_address, &buf[size],
                                     tx_buffer_size);
            size += tx_buffer_size;
            if (tx_buffer_el & 1) {
                break;
            }
        }
    }
    TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
    qemu_send_packet(&s->nic->nc, buf, size);
    s->statistics.tx_good_frames++;
    /* Transmit with bad status would raise an CX/TNO interrupt.
     * (82557 only). Emulation never has bad status. */
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#if 0
    eepro100_cx_interrupt(s);
#endif
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}

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static void set_multicast_list(EEPRO100State *s)
{
    uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
    uint16_t i;
    memset(&s->mult[0], 0, sizeof(s->mult));
    TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
    for (i = 0; i < multicast_count; i += 6) {
        uint8_t multicast_addr[6];
        cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
        TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
        unsigned mcast_idx = compute_mcast_idx(multicast_addr);
        assert(mcast_idx < 64);
        s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
    }
}

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static void action_command(EEPRO100State *s)
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{
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    for (;;) {
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        bool bit_el;
        bool bit_s;
        bool bit_i;
        bool bit_nc;
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        uint16_t ok_status = STATUS_OK;
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        s->cb_address = s->cu_base + s->cu_offset;
        read_cb(s);
        bit_el = ((s->tx.command & COMMAND_EL) != 0);
        bit_s = ((s->tx.command & COMMAND_S) != 0);
        bit_i = ((s->tx.command & COMMAND_I) != 0);
        bit_nc = ((s->tx.command & COMMAND_NC) != 0);
#if 0
        bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
#endif
        s->cu_offset = s->tx.link;
        TRACE(OTHER,
              logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
                     s->tx.status, s->tx.command, s->tx.link));
        switch (s->tx.command & COMMAND_CMD) {
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        case CmdNOp:
            /* Do nothing. */
            break;
        case CmdIASetup:
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            cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
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            TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
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            break;
        case CmdConfigure:
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            cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
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                                     sizeof(s->configuration));
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            TRACE(OTHER, logout("configuration: %s\n",
                                nic_dump(&s->configuration[0], 16)));
            TRACE(OTHER, logout("configuration: %s\n",
                                nic_dump(&s->configuration[16],
                                ARRAY_SIZE(s->configuration) - 16)));
            if (s->configuration[20] & BIT(6)) {
                TRACE(OTHER, logout("Multiple IA bit\n"));
            }
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            break;
        case CmdMulticastList:
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            set_multicast_list(s);
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            break;
        case CmdTx:
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            if (bit_nc) {
                missing("CmdTx: NC = 0");
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                ok_status = 0;
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                break;
            }
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            tx_command(s);
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            break;
        case CmdTDR:
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            TRACE(OTHER, logout("load microcode\n"));
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            /* Starting with offset 8, the command contains
             * 64 dwords microcode which we just ignore here. */
            break;
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        case CmdDiagnose:
            TRACE(OTHER, logout("diagnose\n"));
            /* Make sure error flag is not set. */
            s->tx.status = 0;
            break;
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        default:
            missing("undefined command");
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            ok_status = 0;
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            break;
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        }
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        /* Write new status. */
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        e100_stw_le_phys(s->cb_address, s->tx.status | ok_status | STATUS_C);
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        if (bit_i) {
            /* CU completed action. */
            eepro100_cx_interrupt(s);
        }
        if (bit_el) {
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            /* CU becomes idle. Terminate command loop. */
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            set_cu_state(s, cu_idle);
            eepro100_cna_interrupt(s);
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            break;
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        } else if (bit_s) {
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            /* CU becomes suspended. Terminate command loop. */
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            set_cu_state(s, cu_suspended);
            eepro100_cna_interrupt(s);
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            break;
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        } else {
            /* More entries in list. */
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            TRACE(OTHER, logout("CU list with at least one more entry\n"));
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        }
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    }
    TRACE(OTHER, logout("CU list empty\n"));
    /* List is empty. Now CU is idle or suspended. */
}

static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
{
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    cu_state_t cu_state;
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    switch (val) {
    case CU_NOP:
        /* No operation. */
        break;
    case CU_START:
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        cu_state = get_cu_state(s);
        if (cu_state != cu_idle && cu_state != cu_suspended) {
            /* Intel documentation says that CU must be idle or suspended
             * for the CU start command. */
            logout("unexpected CU state is %u\n", cu_state);
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        }
        set_cu_state(s, cu_active);
        s->cu_offset = s->pointer;
        action_command(s);
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        break;
    case CU_RESUME:
        if (get_cu_state(s) != cu_suspended) {
            logout("bad CU resume from CU state %u\n", get_cu_state(s));
            /* Workaround for bad Linux eepro100 driver which resumes
             * from idle state. */
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#if 0
            missing("cu resume");
#endif
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            set_cu_state(s, cu_suspended);
        }
        if (get_cu_state(s) == cu_suspended) {
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            TRACE(OTHER, logout("CU resuming\n"));
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            set_cu_state(s, cu_active);
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            action_command(s);
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        }
        break;
    case CU_STATSADDR:
        /* Load dump counters address. */
        s->statsaddr = s->pointer;
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        TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
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        break;
    case CU_SHOWSTATS:
        /* Dump statistical counters. */
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        TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
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        dump_statistics(s);
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        e100_stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
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        break;
    case CU_CMD_BASE:
        /* Load CU base. */
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        TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
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        s->cu_base = s->pointer;
        break;
    case CU_DUMPSTATS:
        /* Dump and reset statistical counters. */
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        TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
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        dump_statistics(s);
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        e100_stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
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        memset(&s->statistics, 0, sizeof(s->statistics));
        break;
    case CU_SRESUME:
        /* CU static resume. */
        missing("CU static resume");
        break;
    default:
        missing("Undefined CU command");
    }
}

static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
{
    switch (val) {
    case RU_NOP:
        /* No operation. */
        break;
    case RX_START:
        /* RU start. */
        if (get_ru_state(s) != ru_idle) {
            logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
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#if 0
            assert(!"wrong RU state");
#endif
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        }
        set_ru_state(s, ru_ready);
        s->ru_offset = s->pointer;
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        TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
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        break;
    case RX_RESUME:
        /* Restart RU. */
        if (get_ru_state(s) != ru_suspended) {
            logout("RU state is %u, should be %u\n", get_ru_state(s),
                   ru_suspended);
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#if 0
            assert(!"wrong RU state");
#endif
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        }
        set_ru_state(s, ru_ready);
        break;
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    case RU_ABORT:
        /* RU abort. */
        if (get_ru_state(s) == ru_ready) {
            eepro100_rnr_interrupt(s);
        }
        set_ru_state(s, ru_idle);
        break;
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    case RX_ADDR_LOAD:
        /* Load RU base. */
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        TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
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        s->ru_base = s->pointer;
        break;
    default:
        logout("val=0x%02x (undefined RU command)\n", val);
        missing("Undefined SU command");
    }
}

static void eepro100_write_command(EEPRO100State * s, uint8_t val)
{
    eepro100_ru_command(s, val & 0x0f);
    eepro100_cu_command(s, val & 0xf0);
    if ((val) == 0) {
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        TRACE(OTHER, logout("val=0x%02x\n", val));
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    }
    /* Clear command byte after command was accepted. */
    s->mem[SCBCmd] = 0;
}

/*****************************************************************************
 *
 * EEPROM emulation.
 *
 ****************************************************************************/

#define EEPROM_CS       0x02
#define EEPROM_SK       0x01
#define EEPROM_DI       0x04
#define EEPROM_DO       0x08

static uint16_t eepro100_read_eeprom(EEPRO100State * s)
{
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    uint16_t val = e100_read_reg2(s, SCBeeprom);
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    if (eeprom93xx_read(s->eeprom)) {
        val |= EEPROM_DO;
    } else {
        val &= ~EEPROM_DO;
    }
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    TRACE(EEPROM, logout("val=0x%04x\n", val));
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    return val;
}

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static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
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{
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    TRACE(EEPROM, logout("val=0x%02x\n", val));
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    /* mask unwriteable bits */
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#if 0
    val = SET_MASKED(val, 0x31, eeprom->value);
#endif
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    int eecs = ((val & EEPROM_CS) != 0);
    int eesk = ((val & EEPROM_SK) != 0);
    int eedi = ((val & EEPROM_DI) != 0);
    eeprom93xx_write(eeprom, eecs, eesk, eedi);
}

static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
{
    s->pointer = le32_to_cpu(val);
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    TRACE(OTHER, logout("val=0x%08x\n", val));
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}

/*****************************************************************************
 *
 * MDI emulation.
 *
 ****************************************************************************/

#if defined(DEBUG_EEPRO100)
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static const char * const mdi_op_name[] = {
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    "opcode 0",
    "write",
    "read",
    "opcode 3"
};

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static const char * const mdi_reg_name[] = {
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    "Control",
    "Status",
    "PHY Identification (Word 1)",
    "PHY Identification (Word 2)",
    "Auto-Negotiation Advertisement",
    "Auto-Negotiation Link Partner Ability",
    "Auto-Negotiation Expansion"
};
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static const char *reg2name(uint8_t reg)
{
    static char buffer[10];
    const char *p = buffer;
    if (reg < ARRAY_SIZE(mdi_reg_name)) {
        p = mdi_reg_name[reg];
    } else {
        snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
    }
    return p;
}
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#endif                          /* DEBUG_EEPRO100 */

static uint32_t eepro100_read_mdi(EEPRO100State * s)
{
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    uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
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#ifdef DEBUG_EEPRO100
    uint8_t raiseint = (val & BIT(29)) >> 29;
    uint8_t opcode = (val & BITS(27, 26)) >> 26;
    uint8_t phy = (val & BITS(25, 21)) >> 21;
    uint8_t reg = (val & BITS(20, 16)) >> 16;
    uint16_t data = (val & BITS(15, 0));
#endif
    /* Emulation takes no time to finish MDI transaction. */
    val |= BIT(28);
    TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
                      val, raiseint, mdi_op_name[opcode], phy,
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                      reg2name(reg), data));
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    return val;
}

static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
{
    uint8_t raiseint = (val & BIT(29)) >> 29;
    uint8_t opcode = (val & BITS(27, 26)) >> 26;
    uint8_t phy = (val & BITS(25, 21)) >> 21;
    uint8_t reg = (val & BITS(20, 16)) >> 16;
    uint16_t data = (val & BITS(15, 0));
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    TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
          val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
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    if (phy != 1) {
        /* Unsupported PHY address. */
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#if 0
        logout("phy must be 1 but is %u\n", phy);
#endif
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        data = 0;
    } else if (opcode != 1 && opcode != 2) {
        /* Unsupported opcode. */
        logout("opcode must be 1 or 2 but is %u\n", opcode);
        data = 0;
    } else if (reg > 6) {
        /* Unsupported register. */
        logout("register must be 0...6 but is %u\n", reg);
        data = 0;
    } else {
        TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
                          val, raiseint, mdi_op_name[opcode], phy,
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                          reg2name(reg), data));
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        if (opcode == 1) {
            /* MDI write */
            switch (reg) {
            case 0:            /* Control Register */
                if (data & 0x8000) {
                    /* Reset status and control registers to default. */
                    s->mdimem[0] = eepro100_mdi_default[0];
                    s->mdimem[1] = eepro100_mdi_default[1];
                    data = s->mdimem[reg];
                } else {
                    /* Restart Auto Configuration = Normal Operation */
                    data &= ~0x0200;
                }
                break;
            case 1:            /* Status Register */
                missing("not writable");
                data = s->mdimem[reg];
                break;
            case 2:            /* PHY Identification Register (Word 1) */
            case 3:            /* PHY Identification Register (Word 2) */
                missing("not implemented");
                break;
            case 4:            /* Auto-Negotiation Advertisement Register */
            case 5:            /* Auto-Negotiation Link Partner Ability Register */
                break;
            case 6:            /* Auto-Negotiation Expansion Register */
            default:
                missing("not implemented");
            }
            s->mdimem[reg] = data;
        } else if (opcode == 2) {
            /* MDI read */
            switch (reg) {
            case 0:            /* Control Register */
                if (data & 0x8000) {
                    /* Reset status and control registers to default. */
                    s->mdimem[0] = eepro100_mdi_default[0];
                    s->mdimem[1] = eepro100_mdi_default[1];
                }
                break;
            case 1:            /* Status Register */
                s->mdimem[reg] |= 0x0020;
                break;
            case 2:            /* PHY Identification Register (Word 1) */
            case 3:            /* PHY Identification Register (Word 2) */
            case 4:            /* Auto-Negotiation Advertisement Register */
                break;
            case 5:            /* Auto-Negotiation Link Partner Ability Register */
                s->mdimem[reg] = 0x41fe;
                break;
            case 6:            /* Auto-Negotiation Expansion Register */
                s->mdimem[reg] = 0x0001;
                break;
            }
            data = s->mdimem[reg];
        }
        /* Emulation takes no time to finish MDI transaction.
         * Set MDI bit in SCB status register. */
        s->mem[SCBAck] |= 0x08;
        val |= BIT(28);
        if (raiseint) {
            eepro100_mdi_interrupt(s);
        }
    }
    val = (val & 0xffff0000) + data;
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    e100_write_reg4(s, SCBCtrlMDI, val);
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}

/*****************************************************************************
 *
 * Port emulation.
 *
 ****************************************************************************/

#define PORT_SOFTWARE_RESET     0
#define PORT_SELFTEST           1
#define PORT_SELECTIVE_RESET    2
#define PORT_DUMP               3
#define PORT_SELECTION_MASK     3

typedef struct {
    uint32_t st_sign;           /* Self Test Signature */
    uint32_t st_result;         /* Self Test Results */
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} eepro100_selftest_t;
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static uint32_t eepro100_read_port(EEPRO100State * s)
{
    return 0;
}

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static void eepro100_write_port(EEPRO100State *s)
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{
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    uint32_t val = e100_read_reg4(s, SCBPort);
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    uint32_t address = (val & ~PORT_SELECTION_MASK);
    uint8_t selection = (val & PORT_SELECTION_MASK);
    switch (selection) {
    case PORT_SOFTWARE_RESET:
        nic_reset(s);
        break;
    case PORT_SELFTEST:
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        TRACE(OTHER, logout("selftest address=0x%08x\n", address));
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        eepro100_selftest_t data;
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        cpu_physical_memory_read(address, &data, sizeof(data));
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        data.st_sign = 0xffffffff;
        data.st_result = 0;
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        cpu_physical_memory_write(address, &data, sizeof(data));
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        break;
    case PORT_SELECTIVE_RESET:
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        TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
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