translate.c 350 KB
Newer Older
bellard's avatar
bellard committed
1
2
/*
 *  MIPS32 emulation for qemu: main translation routines.
3
 *
bellard's avatar
bellard committed
4
 *  Copyright (c) 2004-2005 Jocelyn Mayer
bellard's avatar
bellard committed
5
 *  Copyright (c) 2006 Marius Groeger (FPU operations)
ths's avatar
ths committed
6
 *  Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
7
 *  Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
bellard's avatar
bellard committed
8
9
10
11
12
13
14
15
16
17
18
19
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
20
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard's avatar
bellard committed
21
22
23
24
25
26
27
28
29
30
31
 */

#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>

#include "cpu.h"
#include "exec-all.h"
#include "disas.h"
bellard's avatar
bellard committed
32
#include "tcg-op.h"
33
#include "qemu-common.h"
bellard's avatar
bellard committed
34

pbrook's avatar
pbrook committed
35
36
37
38
#include "helper.h"
#define GEN_HELPER 1
#include "helper.h"

39
//#define MIPS_DEBUG_DISAS
40
//#define MIPS_DEBUG_SIGN_EXTENSIONS
bellard's avatar
bellard committed
41

42
43
/* MIPS major opcodes */
#define MASK_OP_MAJOR(op)  (op & (0x3F << 26))
44
45
46

enum {
    /* indirect opcode tables */
47
48
49
50
51
52
53
54
    OPC_SPECIAL  = (0x00 << 26),
    OPC_REGIMM   = (0x01 << 26),
    OPC_CP0      = (0x10 << 26),
    OPC_CP1      = (0x11 << 26),
    OPC_CP2      = (0x12 << 26),
    OPC_CP3      = (0x13 << 26),
    OPC_SPECIAL2 = (0x1C << 26),
    OPC_SPECIAL3 = (0x1F << 26),
55
    /* arithmetic with immediate */
56
57
58
59
    OPC_ADDI     = (0x08 << 26),
    OPC_ADDIU    = (0x09 << 26),
    OPC_SLTI     = (0x0A << 26),
    OPC_SLTIU    = (0x0B << 26),
60
    /* logic with immediate */
61
62
63
64
    OPC_ANDI     = (0x0C << 26),
    OPC_ORI      = (0x0D << 26),
    OPC_XORI     = (0x0E << 26),
    OPC_LUI      = (0x0F << 26),
65
    /* arithmetic with immediate */
66
67
    OPC_DADDI    = (0x18 << 26),
    OPC_DADDIU   = (0x19 << 26),
68
    /* Jump and branches */
69
70
    OPC_J        = (0x02 << 26),
    OPC_JAL      = (0x03 << 26),
Nathan Froyd's avatar
Nathan Froyd committed
71
    OPC_JALS     = OPC_JAL | 0x5,
72
73
74
75
76
77
78
79
80
    OPC_BEQ      = (0x04 << 26),  /* Unconditional if rs = rt = 0 (B) */
    OPC_BEQL     = (0x14 << 26),
    OPC_BNE      = (0x05 << 26),
    OPC_BNEL     = (0x15 << 26),
    OPC_BLEZ     = (0x06 << 26),
    OPC_BLEZL    = (0x16 << 26),
    OPC_BGTZ     = (0x07 << 26),
    OPC_BGTZL    = (0x17 << 26),
    OPC_JALX     = (0x1D << 26),  /* MIPS 16 only */
Nathan Froyd's avatar
Nathan Froyd committed
81
    OPC_JALXS    = OPC_JALX | 0x5,
82
    /* Load and stores */
83
84
85
86
87
88
    OPC_LDL      = (0x1A << 26),
    OPC_LDR      = (0x1B << 26),
    OPC_LB       = (0x20 << 26),
    OPC_LH       = (0x21 << 26),
    OPC_LWL      = (0x22 << 26),
    OPC_LW       = (0x23 << 26),
89
    OPC_LWPC     = OPC_LW | 0x5,
90
91
92
93
94
95
96
97
98
99
100
101
102
103
    OPC_LBU      = (0x24 << 26),
    OPC_LHU      = (0x25 << 26),
    OPC_LWR      = (0x26 << 26),
    OPC_LWU      = (0x27 << 26),
    OPC_SB       = (0x28 << 26),
    OPC_SH       = (0x29 << 26),
    OPC_SWL      = (0x2A << 26),
    OPC_SW       = (0x2B << 26),
    OPC_SDL      = (0x2C << 26),
    OPC_SDR      = (0x2D << 26),
    OPC_SWR      = (0x2E << 26),
    OPC_LL       = (0x30 << 26),
    OPC_LLD      = (0x34 << 26),
    OPC_LD       = (0x37 << 26),
104
    OPC_LDPC     = OPC_LD | 0x5,
105
106
107
    OPC_SC       = (0x38 << 26),
    OPC_SCD      = (0x3C << 26),
    OPC_SD       = (0x3F << 26),
108
    /* Floating point load/store */
109
110
111
112
113
114
115
116
117
118
    OPC_LWC1     = (0x31 << 26),
    OPC_LWC2     = (0x32 << 26),
    OPC_LDC1     = (0x35 << 26),
    OPC_LDC2     = (0x36 << 26),
    OPC_SWC1     = (0x39 << 26),
    OPC_SWC2     = (0x3A << 26),
    OPC_SDC1     = (0x3D << 26),
    OPC_SDC2     = (0x3E << 26),
    /* MDMX ASE specific */
    OPC_MDMX     = (0x1E << 26),
119
    /* Cache and prefetch */
120
121
122
123
    OPC_CACHE    = (0x2F << 26),
    OPC_PREF     = (0x33 << 26),
    /* Reserved major opcode */
    OPC_MAJOR3B_RESERVED = (0x3B << 26),
124
125
126
};

/* MIPS special opcodes */
127
128
#define MASK_SPECIAL(op)   MASK_OP_MAJOR(op) | (op & 0x3F)

129
130
enum {
    /* Shifts */
131
    OPC_SLL      = 0x00 | OPC_SPECIAL,
132
133
    /* NOP is SLL r0, r0, 0   */
    /* SSNOP is SLL r0, r0, 1 */
134
135
    /* EHB is SLL r0, r0, 3 */
    OPC_SRL      = 0x02 | OPC_SPECIAL, /* also ROTR */
136
    OPC_ROTR     = OPC_SRL | (1 << 21),
137
138
    OPC_SRA      = 0x03 | OPC_SPECIAL,
    OPC_SLLV     = 0x04 | OPC_SPECIAL,
139
    OPC_SRLV     = 0x06 | OPC_SPECIAL, /* also ROTRV */
140
    OPC_ROTRV    = OPC_SRLV | (1 << 6),
141
142
143
    OPC_SRAV     = 0x07 | OPC_SPECIAL,
    OPC_DSLLV    = 0x14 | OPC_SPECIAL,
    OPC_DSRLV    = 0x16 | OPC_SPECIAL, /* also DROTRV */
144
    OPC_DROTRV   = OPC_DSRLV | (1 << 6),
145
146
147
    OPC_DSRAV    = 0x17 | OPC_SPECIAL,
    OPC_DSLL     = 0x38 | OPC_SPECIAL,
    OPC_DSRL     = 0x3A | OPC_SPECIAL, /* also DROTR */
148
    OPC_DROTR    = OPC_DSRL | (1 << 21),
149
150
151
    OPC_DSRA     = 0x3B | OPC_SPECIAL,
    OPC_DSLL32   = 0x3C | OPC_SPECIAL,
    OPC_DSRL32   = 0x3E | OPC_SPECIAL, /* also DROTR32 */
152
    OPC_DROTR32  = OPC_DSRL32 | (1 << 21),
153
    OPC_DSRA32   = 0x3F | OPC_SPECIAL,
154
    /* Multiplication / division */
155
156
157
158
159
160
161
162
    OPC_MULT     = 0x18 | OPC_SPECIAL,
    OPC_MULTU    = 0x19 | OPC_SPECIAL,
    OPC_DIV      = 0x1A | OPC_SPECIAL,
    OPC_DIVU     = 0x1B | OPC_SPECIAL,
    OPC_DMULT    = 0x1C | OPC_SPECIAL,
    OPC_DMULTU   = 0x1D | OPC_SPECIAL,
    OPC_DDIV     = 0x1E | OPC_SPECIAL,
    OPC_DDIVU    = 0x1F | OPC_SPECIAL,
163
    /* 2 registers arithmetic / logic */
164
165
166
167
168
169
170
171
172
173
174
175
176
177
    OPC_ADD      = 0x20 | OPC_SPECIAL,
    OPC_ADDU     = 0x21 | OPC_SPECIAL,
    OPC_SUB      = 0x22 | OPC_SPECIAL,
    OPC_SUBU     = 0x23 | OPC_SPECIAL,
    OPC_AND      = 0x24 | OPC_SPECIAL,
    OPC_OR       = 0x25 | OPC_SPECIAL,
    OPC_XOR      = 0x26 | OPC_SPECIAL,
    OPC_NOR      = 0x27 | OPC_SPECIAL,
    OPC_SLT      = 0x2A | OPC_SPECIAL,
    OPC_SLTU     = 0x2B | OPC_SPECIAL,
    OPC_DADD     = 0x2C | OPC_SPECIAL,
    OPC_DADDU    = 0x2D | OPC_SPECIAL,
    OPC_DSUB     = 0x2E | OPC_SPECIAL,
    OPC_DSUBU    = 0x2F | OPC_SPECIAL,
178
    /* Jumps */
179
180
    OPC_JR       = 0x08 | OPC_SPECIAL, /* Also JR.HB */
    OPC_JALR     = 0x09 | OPC_SPECIAL, /* Also JALR.HB */
181
    OPC_JALRC    = OPC_JALR | (0x5 << 6),
Nathan Froyd's avatar
Nathan Froyd committed
182
    OPC_JALRS    = 0x10 | OPC_SPECIAL | (0x5 << 6),
183
    /* Traps */
184
185
186
187
188
189
    OPC_TGE      = 0x30 | OPC_SPECIAL,
    OPC_TGEU     = 0x31 | OPC_SPECIAL,
    OPC_TLT      = 0x32 | OPC_SPECIAL,
    OPC_TLTU     = 0x33 | OPC_SPECIAL,
    OPC_TEQ      = 0x34 | OPC_SPECIAL,
    OPC_TNE      = 0x36 | OPC_SPECIAL,
190
    /* HI / LO registers load & stores */
191
192
193
194
    OPC_MFHI     = 0x10 | OPC_SPECIAL,
    OPC_MTHI     = 0x11 | OPC_SPECIAL,
    OPC_MFLO     = 0x12 | OPC_SPECIAL,
    OPC_MTLO     = 0x13 | OPC_SPECIAL,
195
    /* Conditional moves */
196
197
    OPC_MOVZ     = 0x0A | OPC_SPECIAL,
    OPC_MOVN     = 0x0B | OPC_SPECIAL,
198

199
    OPC_MOVCI    = 0x01 | OPC_SPECIAL,
200
201

    /* Special */
Stefan Weil's avatar
Stefan Weil committed
202
    OPC_PMON     = 0x05 | OPC_SPECIAL, /* unofficial */
203
204
    OPC_SYSCALL  = 0x0C | OPC_SPECIAL,
    OPC_BREAK    = 0x0D | OPC_SPECIAL,
Stefan Weil's avatar
Stefan Weil committed
205
    OPC_SPIM     = 0x0E | OPC_SPECIAL, /* unofficial */
206
207
208
209
210
211
212
213
214
215
216
    OPC_SYNC     = 0x0F | OPC_SPECIAL,

    OPC_SPECIAL15_RESERVED = 0x15 | OPC_SPECIAL,
    OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL,
    OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL,
    OPC_SPECIAL35_RESERVED = 0x35 | OPC_SPECIAL,
    OPC_SPECIAL37_RESERVED = 0x37 | OPC_SPECIAL,
    OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL,
    OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,
};

217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
/* Multiplication variants of the vr54xx. */
#define MASK_MUL_VR54XX(op)   MASK_SPECIAL(op) | (op & (0x1F << 6))

enum {
    OPC_VR54XX_MULS    = (0x03 << 6) | OPC_MULT,
    OPC_VR54XX_MULSU   = (0x03 << 6) | OPC_MULTU,
    OPC_VR54XX_MACC    = (0x05 << 6) | OPC_MULT,
    OPC_VR54XX_MACCU   = (0x05 << 6) | OPC_MULTU,
    OPC_VR54XX_MSAC    = (0x07 << 6) | OPC_MULT,
    OPC_VR54XX_MSACU   = (0x07 << 6) | OPC_MULTU,
    OPC_VR54XX_MULHI   = (0x09 << 6) | OPC_MULT,
    OPC_VR54XX_MULHIU  = (0x09 << 6) | OPC_MULTU,
    OPC_VR54XX_MULSHI  = (0x0B << 6) | OPC_MULT,
    OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
    OPC_VR54XX_MACCHI  = (0x0D << 6) | OPC_MULT,
    OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU,
    OPC_VR54XX_MSACHI  = (0x0F << 6) | OPC_MULT,
    OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
};

237
238
239
240
241
242
243
244
245
/* REGIMM (rt field) opcodes */
#define MASK_REGIMM(op)    MASK_OP_MAJOR(op) | (op & (0x1F << 16))

enum {
    OPC_BLTZ     = (0x00 << 16) | OPC_REGIMM,
    OPC_BLTZL    = (0x02 << 16) | OPC_REGIMM,
    OPC_BGEZ     = (0x01 << 16) | OPC_REGIMM,
    OPC_BGEZL    = (0x03 << 16) | OPC_REGIMM,
    OPC_BLTZAL   = (0x10 << 16) | OPC_REGIMM,
246
    OPC_BLTZALS  = OPC_BLTZAL | 0x5, /* microMIPS */
247
248
    OPC_BLTZALL  = (0x12 << 16) | OPC_REGIMM,
    OPC_BGEZAL   = (0x11 << 16) | OPC_REGIMM,
249
    OPC_BGEZALS  = OPC_BGEZAL | 0x5, /* microMIPS */
250
251
252
253
254
255
256
257
    OPC_BGEZALL  = (0x13 << 16) | OPC_REGIMM,
    OPC_TGEI     = (0x08 << 16) | OPC_REGIMM,
    OPC_TGEIU    = (0x09 << 16) | OPC_REGIMM,
    OPC_TLTI     = (0x0A << 16) | OPC_REGIMM,
    OPC_TLTIU    = (0x0B << 16) | OPC_REGIMM,
    OPC_TEQI     = (0x0C << 16) | OPC_REGIMM,
    OPC_TNEI     = (0x0E << 16) | OPC_REGIMM,
    OPC_SYNCI    = (0x1F << 16) | OPC_REGIMM,
258
259
};

260
261
262
/* Special2 opcodes */
#define MASK_SPECIAL2(op)  MASK_OP_MAJOR(op) | (op & 0x3F)

263
enum {
264
265
266
267
268
269
    /* Multiply & xxx operations */
    OPC_MADD     = 0x00 | OPC_SPECIAL2,
    OPC_MADDU    = 0x01 | OPC_SPECIAL2,
    OPC_MUL      = 0x02 | OPC_SPECIAL2,
    OPC_MSUB     = 0x04 | OPC_SPECIAL2,
    OPC_MSUBU    = 0x05 | OPC_SPECIAL2,
270
    /* Misc */
271
272
273
274
    OPC_CLZ      = 0x20 | OPC_SPECIAL2,
    OPC_CLO      = 0x21 | OPC_SPECIAL2,
    OPC_DCLZ     = 0x24 | OPC_SPECIAL2,
    OPC_DCLO     = 0x25 | OPC_SPECIAL2,
275
    /* Special */
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
    OPC_SDBBP    = 0x3F | OPC_SPECIAL2,
};

/* Special3 opcodes */
#define MASK_SPECIAL3(op)  MASK_OP_MAJOR(op) | (op & 0x3F)

enum {
    OPC_EXT      = 0x00 | OPC_SPECIAL3,
    OPC_DEXTM    = 0x01 | OPC_SPECIAL3,
    OPC_DEXTU    = 0x02 | OPC_SPECIAL3,
    OPC_DEXT     = 0x03 | OPC_SPECIAL3,
    OPC_INS      = 0x04 | OPC_SPECIAL3,
    OPC_DINSM    = 0x05 | OPC_SPECIAL3,
    OPC_DINSU    = 0x06 | OPC_SPECIAL3,
    OPC_DINS     = 0x07 | OPC_SPECIAL3,
291
292
    OPC_FORK     = 0x08 | OPC_SPECIAL3,
    OPC_YIELD    = 0x09 | OPC_SPECIAL3,
293
294
295
    OPC_BSHFL    = 0x20 | OPC_SPECIAL3,
    OPC_DBSHFL   = 0x24 | OPC_SPECIAL3,
    OPC_RDHWR    = 0x3B | OPC_SPECIAL3,
296
297
};

298
299
300
/* BSHFL opcodes */
#define MASK_BSHFL(op)     MASK_SPECIAL3(op) | (op & (0x1F << 6))

301
enum {
302
303
304
    OPC_WSBH     = (0x02 << 6) | OPC_BSHFL,
    OPC_SEB      = (0x10 << 6) | OPC_BSHFL,
    OPC_SEH      = (0x18 << 6) | OPC_BSHFL,
305
306
};

307
308
309
/* DBSHFL opcodes */
#define MASK_DBSHFL(op)    MASK_SPECIAL3(op) | (op & (0x1F << 6))

310
enum {
311
312
    OPC_DSBH     = (0x02 << 6) | OPC_DBSHFL,
    OPC_DSHD     = (0x05 << 6) | OPC_DBSHFL,
313
314
};

315
316
317
/* Coprocessor 0 (rs field) */
#define MASK_CP0(op)       MASK_OP_MAJOR(op) | (op & (0x1F << 21))

bellard's avatar
bellard committed
318
enum {
319
320
321
322
    OPC_MFC0     = (0x00 << 21) | OPC_CP0,
    OPC_DMFC0    = (0x01 << 21) | OPC_CP0,
    OPC_MTC0     = (0x04 << 21) | OPC_CP0,
    OPC_DMTC0    = (0x05 << 21) | OPC_CP0,
323
    OPC_MFTR     = (0x08 << 21) | OPC_CP0,
324
325
    OPC_RDPGPR   = (0x0A << 21) | OPC_CP0,
    OPC_MFMC0    = (0x0B << 21) | OPC_CP0,
326
    OPC_MTTR     = (0x0C << 21) | OPC_CP0,
327
328
329
330
    OPC_WRPGPR   = (0x0E << 21) | OPC_CP0,
    OPC_C0       = (0x10 << 21) | OPC_CP0,
    OPC_C0_FIRST = (0x10 << 21) | OPC_CP0,
    OPC_C0_LAST  = (0x1F << 21) | OPC_CP0,
bellard's avatar
bellard committed
331
};
332
333

/* MFMC0 opcodes */
334
#define MASK_MFMC0(op)     MASK_CP0(op) | (op & 0xFFFF)
335
336

enum {
337
338
339
340
    OPC_DMT      = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
    OPC_EMT      = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
    OPC_DVPE     = 0x01 | (0 << 5) | OPC_MFMC0,
    OPC_EVPE     = 0x01 | (1 << 5) | OPC_MFMC0,
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
    OPC_DI       = (0 << 5) | (0x0C << 11) | OPC_MFMC0,
    OPC_EI       = (1 << 5) | (0x0C << 11) | OPC_MFMC0,
};

/* Coprocessor 0 (with rs == C0) */
#define MASK_C0(op)        MASK_CP0(op) | (op & 0x3F)

enum {
    OPC_TLBR     = 0x01 | OPC_C0,
    OPC_TLBWI    = 0x02 | OPC_C0,
    OPC_TLBWR    = 0x06 | OPC_C0,
    OPC_TLBP     = 0x08 | OPC_C0,
    OPC_RFE      = 0x10 | OPC_C0,
    OPC_ERET     = 0x18 | OPC_C0,
    OPC_DERET    = 0x1F | OPC_C0,
    OPC_WAIT     = 0x20 | OPC_C0,
};

/* Coprocessor 1 (rs field) */
#define MASK_CP1(op)       MASK_OP_MAJOR(op) | (op & (0x1F << 21))

362
363
364
/* Values for the fmt field in FP instructions */
enum {
    /* 0 - 15 are reserved */
365
366
367
368
369
370
371
    FMT_S = 16,          /* single fp */
    FMT_D = 17,          /* double fp */
    FMT_E = 18,          /* extended fp */
    FMT_Q = 19,          /* quad fp */
    FMT_W = 20,          /* 32-bit fixed */
    FMT_L = 21,          /* 64-bit fixed */
    FMT_PS = 22,         /* paired single fp */
372
373
374
    /* 23 - 31 are reserved */
};

375
376
377
378
enum {
    OPC_MFC1     = (0x00 << 21) | OPC_CP1,
    OPC_DMFC1    = (0x01 << 21) | OPC_CP1,
    OPC_CFC1     = (0x02 << 21) | OPC_CP1,
379
    OPC_MFHC1    = (0x03 << 21) | OPC_CP1,
380
381
382
    OPC_MTC1     = (0x04 << 21) | OPC_CP1,
    OPC_DMTC1    = (0x05 << 21) | OPC_CP1,
    OPC_CTC1     = (0x06 << 21) | OPC_CP1,
383
    OPC_MTHC1    = (0x07 << 21) | OPC_CP1,
384
    OPC_BC1      = (0x08 << 21) | OPC_CP1, /* bc */
385
386
    OPC_BC1ANY2  = (0x09 << 21) | OPC_CP1,
    OPC_BC1ANY4  = (0x0A << 21) | OPC_CP1,
387
388
389
390
391
392
393
    OPC_S_FMT    = (FMT_S << 21) | OPC_CP1,
    OPC_D_FMT    = (FMT_D << 21) | OPC_CP1,
    OPC_E_FMT    = (FMT_E << 21) | OPC_CP1,
    OPC_Q_FMT    = (FMT_Q << 21) | OPC_CP1,
    OPC_W_FMT    = (FMT_W << 21) | OPC_CP1,
    OPC_L_FMT    = (FMT_L << 21) | OPC_CP1,
    OPC_PS_FMT   = (FMT_PS << 21) | OPC_CP1,
394
395
};

396
397
398
#define MASK_CP1_FUNC(op)       MASK_CP1(op) | (op & 0x3F)
#define MASK_BC1(op)            MASK_CP1(op) | (op & (0x3 << 16))

399
400
401
402
403
404
405
enum {
    OPC_BC1F     = (0x00 << 16) | OPC_BC1,
    OPC_BC1T     = (0x01 << 16) | OPC_BC1,
    OPC_BC1FL    = (0x02 << 16) | OPC_BC1,
    OPC_BC1TL    = (0x03 << 16) | OPC_BC1,
};

406
407
408
409
410
411
412
413
414
enum {
    OPC_BC1FANY2     = (0x00 << 16) | OPC_BC1ANY2,
    OPC_BC1TANY2     = (0x01 << 16) | OPC_BC1ANY2,
};

enum {
    OPC_BC1FANY4     = (0x00 << 16) | OPC_BC1ANY4,
    OPC_BC1TANY4     = (0x01 << 16) | OPC_BC1ANY4,
};
415
416

#define MASK_CP2(op)       MASK_OP_MAJOR(op) | (op & (0x1F << 21))
ths's avatar
ths committed
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447

enum {
    OPC_MFC2    = (0x00 << 21) | OPC_CP2,
    OPC_DMFC2   = (0x01 << 21) | OPC_CP2,
    OPC_CFC2    = (0x02 << 21) | OPC_CP2,
    OPC_MFHC2   = (0x03 << 21) | OPC_CP2,
    OPC_MTC2    = (0x04 << 21) | OPC_CP2,
    OPC_DMTC2   = (0x05 << 21) | OPC_CP2,
    OPC_CTC2    = (0x06 << 21) | OPC_CP2,
    OPC_MTHC2   = (0x07 << 21) | OPC_CP2,
    OPC_BC2     = (0x08 << 21) | OPC_CP2,
};

#define MASK_CP3(op)       MASK_OP_MAJOR(op) | (op & 0x3F)

enum {
    OPC_LWXC1   = 0x00 | OPC_CP3,
    OPC_LDXC1   = 0x01 | OPC_CP3,
    OPC_LUXC1   = 0x05 | OPC_CP3,
    OPC_SWXC1   = 0x08 | OPC_CP3,
    OPC_SDXC1   = 0x09 | OPC_CP3,
    OPC_SUXC1   = 0x0D | OPC_CP3,
    OPC_PREFX   = 0x0F | OPC_CP3,
    OPC_ALNV_PS = 0x1E | OPC_CP3,
    OPC_MADD_S  = 0x20 | OPC_CP3,
    OPC_MADD_D  = 0x21 | OPC_CP3,
    OPC_MADD_PS = 0x26 | OPC_CP3,
    OPC_MSUB_S  = 0x28 | OPC_CP3,
    OPC_MSUB_D  = 0x29 | OPC_CP3,
    OPC_MSUB_PS = 0x2E | OPC_CP3,
    OPC_NMADD_S = 0x30 | OPC_CP3,
448
    OPC_NMADD_D = 0x31 | OPC_CP3,
ths's avatar
ths committed
449
450
451
452
453
454
    OPC_NMADD_PS= 0x36 | OPC_CP3,
    OPC_NMSUB_S = 0x38 | OPC_CP3,
    OPC_NMSUB_D = 0x39 | OPC_CP3,
    OPC_NMSUB_PS= 0x3E | OPC_CP3,
};

455
/* global register indices */
pbrook's avatar
pbrook committed
456
457
static TCGv_ptr cpu_env;
static TCGv cpu_gpr[32], cpu_PC;
458
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC];
459
460
static TCGv cpu_dspctrl, btarget, bcond;
static TCGv_i32 hflags;
pbrook's avatar
pbrook committed
461
static TCGv_i32 fpu_fcr0, fpu_fcr31;
ths's avatar
ths committed
462

463
464
static uint32_t gen_opc_hflags[OPC_BUF_SIZE];

pbrook's avatar
pbrook committed
465
466
#include "gen-icount.h"

pbrook's avatar
pbrook committed
467
468
469
470
471
#define gen_helper_0i(name, arg) do {                             \
    TCGv_i32 helper_tmp = tcg_const_i32(arg);                     \
    gen_helper_##name(helper_tmp);                                \
    tcg_temp_free_i32(helper_tmp);                                \
    } while(0)
472

pbrook's avatar
pbrook committed
473
474
475
476
477
#define gen_helper_1i(name, arg1, arg2) do {                      \
    TCGv_i32 helper_tmp = tcg_const_i32(arg2);                    \
    gen_helper_##name(arg1, helper_tmp);                          \
    tcg_temp_free_i32(helper_tmp);                                \
    } while(0)
478

pbrook's avatar
pbrook committed
479
480
481
482
483
#define gen_helper_2i(name, arg1, arg2, arg3) do {                \
    TCGv_i32 helper_tmp = tcg_const_i32(arg3);                    \
    gen_helper_##name(arg1, arg2, helper_tmp);                    \
    tcg_temp_free_i32(helper_tmp);                                \
    } while(0)
484

pbrook's avatar
pbrook committed
485
486
487
488
489
#define gen_helper_3i(name, arg1, arg2, arg3, arg4) do {          \
    TCGv_i32 helper_tmp = tcg_const_i32(arg4);                    \
    gen_helper_##name(arg1, arg2, arg3, helper_tmp);              \
    tcg_temp_free_i32(helper_tmp);                                \
    } while(0)
ths's avatar
ths committed
490

491
492
493
494
typedef struct DisasContext {
    struct TranslationBlock *tb;
    target_ulong pc, saved_pc;
    uint32_t opcode;
495
    int singlestep_enabled;
496
497
498
499
500
501
502
503
504
    /* Routine used to access memory */
    int mem_idx;
    uint32_t hflags, saved_hflags;
    int bstate;
    target_ulong btarget;
} DisasContext;

enum {
    BS_NONE     = 0, /* We go out of the TB without reaching a branch or an
ths's avatar
ths committed
505
                      * exception condition */
506
507
508
509
510
511
    BS_STOP     = 1, /* We want to stop translation for any reason */
    BS_BRANCH   = 2, /* We reached a branch condition     */
    BS_EXCP     = 3, /* We reached an exception condition */
};

static const char *regnames[] =
bellard's avatar
bellard committed
512
513
514
515
516
    { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
      "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
      "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
      "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };

517
518
519
520
521
522
523
524
525
static const char *regnames_HI[] =
    { "HI0", "HI1", "HI2", "HI3", };

static const char *regnames_LO[] =
    { "LO0", "LO1", "LO2", "LO3", };

static const char *regnames_ACX[] =
    { "ACX0", "ACX1", "ACX2", "ACX3", };

526
527
528
529
530
static const char *fregnames[] =
    { "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
      "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
      "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
      "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
ths's avatar
ths committed
531

532
#ifdef MIPS_DEBUG_DISAS
533
#define MIPS_DEBUG(fmt, ...)                         \
534
535
        qemu_log_mask(CPU_LOG_TB_IN_ASM,                \
                       TARGET_FMT_lx ": %08x " fmt "\n", \
536
                       ctx->pc, ctx->opcode , ## __VA_ARGS__)
537
#define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
538
#else
539
#define MIPS_DEBUG(fmt, ...) do { } while(0)
540
#define LOG_DISAS(...) do { } while (0)
541
#endif
ths's avatar
ths committed
542

543
544
545
546
547
#define MIPS_INVAL(op)                                                        \
do {                                                                          \
    MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26,            \
               ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F));             \
} while (0)
548

549
550
/* General purpose registers moves. */
static inline void gen_load_gpr (TCGv t, int reg)
551
{
552
553
554
    if (reg == 0)
        tcg_gen_movi_tl(t, 0);
    else
555
        tcg_gen_mov_tl(t, cpu_gpr[reg]);
556
557
}

558
static inline void gen_store_gpr (TCGv t, int reg)
559
{
560
    if (reg != 0)
561
        tcg_gen_mov_tl(cpu_gpr[reg], t);
562
563
}

aurel32's avatar
aurel32 committed
564
/* Moves to/from ACX register.  */
565
static inline void gen_load_ACX (TCGv t, int reg)
566
{
567
    tcg_gen_mov_tl(t, cpu_ACX[reg]);
568
569
}

570
static inline void gen_store_ACX (TCGv t, int reg)
571
{
572
    tcg_gen_mov_tl(cpu_ACX[reg], t);
573
574
}

575
/* Moves to/from shadow registers. */
576
static inline void gen_load_srsgpr (int from, int to)
577
{
578
    TCGv t0 = tcg_temp_new();
579
580

    if (from == 0)
581
        tcg_gen_movi_tl(t0, 0);
582
    else {
583
        TCGv_i32 t2 = tcg_temp_new_i32();
pbrook's avatar
pbrook committed
584
        TCGv_ptr addr = tcg_temp_new_ptr();
585

586
587
588
589
590
        tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
        tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
        tcg_gen_andi_i32(t2, t2, 0xf);
        tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
        tcg_gen_ext_i32_ptr(addr, t2);
pbrook's avatar
pbrook committed
591
        tcg_gen_add_ptr(addr, cpu_env, addr);
592

593
        tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from);
pbrook's avatar
pbrook committed
594
        tcg_temp_free_ptr(addr);
595
        tcg_temp_free_i32(t2);
596
    }
597
598
    gen_store_gpr(t0, to);
    tcg_temp_free(t0);
599
600
}

601
static inline void gen_store_srsgpr (int from, int to)
602
{
603
    if (to != 0) {
604
605
        TCGv t0 = tcg_temp_new();
        TCGv_i32 t2 = tcg_temp_new_i32();
pbrook's avatar
pbrook committed
606
        TCGv_ptr addr = tcg_temp_new_ptr();
607

608
609
610
611
612
613
        gen_load_gpr(t0, from);
        tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
        tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
        tcg_gen_andi_i32(t2, t2, 0xf);
        tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
        tcg_gen_ext_i32_ptr(addr, t2);
pbrook's avatar
pbrook committed
614
        tcg_gen_add_ptr(addr, cpu_env, addr);
615

616
        tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to);
pbrook's avatar
pbrook committed
617
        tcg_temp_free_ptr(addr);
618
619
        tcg_temp_free_i32(t2);
        tcg_temp_free(t0);
620
    }
621
622
623
}

/* Floating point register moves. */
pbrook's avatar
pbrook committed
624
static inline void gen_load_fpr32 (TCGv_i32 t, int reg)
ths's avatar
ths committed
625
{
626
    tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
bellard's avatar
bellard committed
627
628
}

pbrook's avatar
pbrook committed
629
static inline void gen_store_fpr32 (TCGv_i32 t, int reg)
ths's avatar
ths committed
630
{
631
632
633
634
635
636
637
638
639
640
641
    tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
}

static inline void gen_load_fpr32h (TCGv_i32 t, int reg)
{
    tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
}

static inline void gen_store_fpr32h (TCGv_i32 t, int reg)
{
    tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
ths's avatar
ths committed
642
}
bellard's avatar
bellard committed
643

pbrook's avatar
pbrook committed
644
static inline void gen_load_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
ths's avatar
ths committed
645
{
aurel32's avatar
aurel32 committed
646
    if (ctx->hflags & MIPS_HFLAG_F64) {
647
        tcg_gen_ld_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
aurel32's avatar
aurel32 committed
648
    } else {
649
650
651
652
653
654
655
        TCGv_i32 t0 = tcg_temp_new_i32();
        TCGv_i32 t1 = tcg_temp_new_i32();
        gen_load_fpr32(t0, reg & ~1);
        gen_load_fpr32(t1, reg | 1);
        tcg_gen_concat_i32_i64(t, t0, t1);
        tcg_temp_free_i32(t0);
        tcg_temp_free_i32(t1);
ths's avatar
ths committed
656
657
    }
}
bellard's avatar
bellard committed
658

pbrook's avatar
pbrook committed
659
static inline void gen_store_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
ths's avatar
ths committed
660
{
aurel32's avatar
aurel32 committed
661
    if (ctx->hflags & MIPS_HFLAG_F64) {
662
        tcg_gen_st_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
aurel32's avatar
aurel32 committed
663
    } else {
664
665
666
667
668
669
670
671
672
        TCGv_i64 t0 = tcg_temp_new_i64();
        TCGv_i32 t1 = tcg_temp_new_i32();
        tcg_gen_trunc_i64_i32(t1, t);
        gen_store_fpr32(t1, reg & ~1);
        tcg_gen_shri_i64(t0, t, 32);
        tcg_gen_trunc_i64_i32(t1, t0);
        gen_store_fpr32(t1, reg | 1);
        tcg_temp_free_i32(t1);
        tcg_temp_free_i64(t0);
ths's avatar
ths committed
673
674
    }
}
bellard's avatar
bellard committed
675

676
static inline int get_fp_bit (int cc)
677
{
678
679
680
681
    if (cc)
        return 24 + cc;
    else
        return 23;
682
683
}

684
/* Tests */
685
686
static inline void gen_save_pc(target_ulong pc)
{
aurel32's avatar
aurel32 committed
687
    tcg_gen_movi_tl(cpu_PC, pc);
688
}
689

690
static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
bellard's avatar
bellard committed
691
{
692
    LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
bellard's avatar
bellard committed
693
    if (do_save_pc && ctx->pc != ctx->saved_pc) {
694
        gen_save_pc(ctx->pc);
bellard's avatar
bellard committed
695
696
697
        ctx->saved_pc = ctx->pc;
    }
    if (ctx->hflags != ctx->saved_hflags) {
698
        tcg_gen_movi_i32(hflags, ctx->hflags);
bellard's avatar
bellard committed
699
        ctx->saved_hflags = ctx->hflags;
700
        switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
701
702
703
704
705
        case MIPS_HFLAG_BR:
            break;
        case MIPS_HFLAG_BC:
        case MIPS_HFLAG_BL:
        case MIPS_HFLAG_B:
ths's avatar
ths committed
706
            tcg_gen_movi_tl(btarget, ctx->btarget);
707
            break;
bellard's avatar
bellard committed
708
709
710
711
        }
    }
}

712
static inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
713
{
714
    ctx->saved_hflags = ctx->hflags;
715
    switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
716
717
718
719
    case MIPS_HFLAG_BR:
        break;
    case MIPS_HFLAG_BC:
    case MIPS_HFLAG_BL:
720
    case MIPS_HFLAG_B:
721
722
        ctx->btarget = env->btarget;
        break;
723
724
725
    }
}

726
static inline void
727
generate_exception_err (DisasContext *ctx, int excp, int err)
728
{
pbrook's avatar
pbrook committed
729
730
    TCGv_i32 texcp = tcg_const_i32(excp);
    TCGv_i32 terr = tcg_const_i32(err);
731
    save_cpu_state(ctx, 1);
pbrook's avatar
pbrook committed
732
733
734
    gen_helper_raise_exception_err(texcp, terr);
    tcg_temp_free_i32(terr);
    tcg_temp_free_i32(texcp);
735
736
}

737
static inline void
738
generate_exception (DisasContext *ctx, int excp)
739
{
bellard's avatar
bellard committed
740
    save_cpu_state(ctx, 1);
pbrook's avatar
pbrook committed
741
    gen_helper_0i(raise_exception, excp);
bellard's avatar
bellard committed
742
743
}

744
/* Addresses computation */
745
static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
bellard's avatar
bellard committed
746
{
747
    tcg_gen_add_tl(ret, arg0, arg1);
748
749
750
751
752

#if defined(TARGET_MIPS64)
    /* For compatibility with 32-bit code, data reference in user mode
       with Status_UX = 0 should be casted to 32-bit and sign extended.
       See the MIPS64 PRA manual, section 4.10. */
753
754
    if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
        !(ctx->hflags & MIPS_HFLAG_UX)) {
755
        tcg_gen_ext32s_i64(ret, ret);
756
757
    }
#endif
bellard's avatar
bellard committed
758
759
}

760
static inline void check_cp0_enabled(DisasContext *ctx)
761
{
762
    if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
763
        generate_exception_err(ctx, EXCP_CpU, 0);
764
765
}

766
static inline void check_cp1_enabled(DisasContext *ctx)
767
{
768
    if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))
769
770
771
        generate_exception_err(ctx, EXCP_CpU, 1);
}

772
773
774
775
/* Verify that the processor is running with COP1X instructions enabled.
   This is associated with the nabla symbol in the MIPS32 and MIPS64
   opcode tables.  */

776
static inline void check_cop1x(DisasContext *ctx)
777
778
779
780
781
782
783
784
{
    if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X)))
        generate_exception(ctx, EXCP_RI);
}

/* Verify that the processor is running with 64-bit floating-point
   operations enabled.  */

785
static inline void check_cp1_64bitmode(DisasContext *ctx)
786
{
787
    if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X)))
788
789
790
791
792
793
794
795
796
797
798
799
800
801
        generate_exception(ctx, EXCP_RI);
}

/*
 * Verify if floating point register is valid; an operation is not defined
 * if bit 0 of any register specification is set and the FR bit in the
 * Status register equals zero, since the register numbers specify an
 * even-odd pair of adjacent coprocessor general registers. When the FR bit
 * in the Status register equals one, both even and odd register numbers
 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
 *
 * Multiple 64 bit wide registers can be checked by calling
 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
 */
802
static inline void check_cp1_registers(DisasContext *ctx, int regs)
803
{
804
    if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1)))
805
806
807
        generate_exception(ctx, EXCP_RI);
}

808
/* This code generates a "reserved instruction" exception if the
809
   CPU does not support the instruction set corresponding to flags. */
810
static inline void check_insn(CPUState *env, DisasContext *ctx, int flags)
811
{
812
    if (unlikely(!(env->insn_flags & flags)))
813
814
815
        generate_exception(ctx, EXCP_RI);
}

816
817
/* This code generates a "reserved instruction" exception if 64-bit
   instructions are not enabled. */
818
static inline void check_mips_64(DisasContext *ctx)
819
{
820
    if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
821
822
823
        generate_exception(ctx, EXCP_RI);
}

824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
/* Define small wrappers for gen_load_fpr* so that we have a uniform
   calling interface for 32 and 64-bit FPRs.  No sense in changing
   all callers for gen_load_fpr32 when we need the CTX parameter for
   this one use.  */
#define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(x, y)
#define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y)
#define FOP_CONDS(type, abs, fmt, ifmt, bits)                                 \
static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n,      \
                                               int ft, int fs, int cc)        \
{                                                                             \
    TCGv_i##bits fp0 = tcg_temp_new_i##bits ();                               \
    TCGv_i##bits fp1 = tcg_temp_new_i##bits ();                               \
    switch (ifmt) {                                                           \
    case FMT_PS:                                                              \
        check_cp1_64bitmode(ctx);                                             \
        break;                                                                \
    case FMT_D:                                                               \
        if (abs) {                                                            \
            check_cop1x(ctx);                                                 \
        }                                                                     \
        check_cp1_registers(ctx, fs | ft);                                    \
        break;                                                                \
    case FMT_S:                                                               \
        if (abs) {                                                            \
            check_cop1x(ctx);                                                 \
        }                                                                     \
        break;                                                                \
    }                                                                         \
    gen_ldcmp_fpr##bits (ctx, fp0, fs);                                       \
    gen_ldcmp_fpr##bits (ctx, fp1, ft);                                       \
    switch (n) {                                                              \
    case  0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc);    break;\
    case  1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc);   break;\
    case  2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc);   break;\
    case  3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc);  break;\
    case  4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc);  break;\
    case  5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc);  break;\
    case  6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc);  break;\
    case  7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc);  break;\
    case  8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc);   break;\
    case  9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); break;\
    case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc);  break;\
    case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc);  break;\
    case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc);   break;\
    case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc);  break;\
    case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc);   break;\
    case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc);  break;\
    default: abort();                                                         \
    }                                                                         \
    tcg_temp_free_i##bits (fp0);                                              \
    tcg_temp_free_i##bits (fp1);                                              \
}

FOP_CONDS(, 0, d, FMT_D, 64)
FOP_CONDS(abs, 1, d, FMT_D, 64)
FOP_CONDS(, 0, s, FMT_S, 32)
FOP_CONDS(abs, 1, s, FMT_S, 32)
FOP_CONDS(, 0, ps, FMT_PS, 64)
FOP_CONDS(abs, 1, ps, FMT_PS, 64)
#undef FOP_CONDS
#undef gen_ldcmp_fpr32
#undef gen_ldcmp_fpr64

ths's avatar
ths committed
887
/* load/store instructions. */
888
889
890
891
#define OP_LD(insn,fname)                                                 \
static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
{                                                                         \
    tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx);                        \
892
893
894
895
896
897
898
899
900
901
902
903
}
OP_LD(lb,ld8s);
OP_LD(lbu,ld8u);
OP_LD(lh,ld16s);
OP_LD(lhu,ld16u);
OP_LD(lw,ld32s);
#if defined(TARGET_MIPS64)
OP_LD(lwu,ld32u);
OP_LD(ld,ld64);
#endif
#undef OP_LD

904
905
906
907
#define OP_ST(insn,fname)                                                  \
static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \
{                                                                          \
    tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx);                        \
908
909
910
911
912
913
914
915
916
}
OP_ST(sb,st8);
OP_ST(sh,st16);
OP_ST(sw,st32);
#if defined(TARGET_MIPS64)
OP_ST(sd,st64);
#endif
#undef OP_ST

917
#ifdef CONFIG_USER_ONLY
918
919
920
921
922
923
#define OP_LD_ATOMIC(insn,fname)                                           \
static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx)  \
{                                                                          \
    TCGv t0 = tcg_temp_new();                                              \
    tcg_gen_mov_tl(t0, arg1);                                              \
    tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx);                         \
924
    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr));                \
Paul Brook's avatar
Paul Brook committed
925
    tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval));                \
926
    tcg_temp_free(t0);                                                     \
927
}
928
929
930
931
932
933
934
#else
#define OP_LD_ATOMIC(insn,fname)                                           \
static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx)  \
{                                                                          \
    gen_helper_2i(insn, ret, arg1, ctx->mem_idx);                          \
}
#endif
935
936
937
938
939
940
OP_LD_ATOMIC(ll,ld32s);
#if defined(TARGET_MIPS64)
OP_LD_ATOMIC(lld,ld64);
#endif
#undef OP_LD_ATOMIC

Paul Brook's avatar
Paul Brook committed
941
942
943
944
945
946
947
948
949
950
951
952
953
#ifdef CONFIG_USER_ONLY
#define OP_ST_ATOMIC(insn,fname,ldname,almask)                               \
static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
{                                                                            \
    TCGv t0 = tcg_temp_new();                                                \
    int l1 = gen_new_label();                                                \
    int l2 = gen_new_label();                                                \
                                                                             \
    tcg_gen_andi_tl(t0, arg2, almask);                                       \
    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);                              \
    tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr));          \
    generate_exception(ctx, EXCP_AdES);                                      \
    gen_set_label(l1);                                                       \
954
    tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr));                  \
Paul Brook's avatar
Paul Brook committed
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
    tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2);                            \
    tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20));                        \
    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, llreg));                   \
    tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUState, llnewval));              \
    gen_helper_0i(raise_exception, EXCP_SC);                                 \
    gen_set_label(l2);                                                       \
    tcg_gen_movi_tl(t0, 0);                                                  \
    gen_store_gpr(t0, rt);                                                   \
    tcg_temp_free(t0);                                                       \
}
#else
#define OP_ST_ATOMIC(insn,fname,ldname,almask)                               \
static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
{                                                                            \
    TCGv t0 = tcg_temp_new();                                                \
970
    gen_helper_3i(insn, t0, arg1, arg2, ctx->mem_idx);                       \
Paul Brook's avatar
Paul Brook committed
971
972
973
974
975
    gen_store_gpr(t0, rt);                                                   \
    tcg_temp_free(t0);                                                       \
}
#endif
OP_ST_ATOMIC(sc,st32,ld32s,0x3);
976
#if defined(TARGET_MIPS64)
Paul Brook's avatar
Paul Brook committed
977
OP_ST_ATOMIC(scd,st64,ld64,0x7);
978
979
980
#endif
#undef OP_ST_ATOMIC

981
982
983
984
985
986
987
988
989
990
991
992
993
static void gen_base_offset_addr (DisasContext *ctx, TCGv addr,
                                  int base, int16_t offset)
{
    if (base == 0) {
        tcg_gen_movi_tl(addr, offset);
    } else if (offset == 0) {
        gen_load_gpr(addr, base);
    } else {
        tcg_gen_movi_tl(addr, offset);
        gen_op_addr_add(ctx, addr, cpu_gpr[base], addr);
    }
}

994
995
996
997
998
999
1000
static target_ulong pc_relative_pc (DisasContext *ctx)
{
    target_ulong pc = ctx->pc;

    if (ctx->hflags & MIPS_HFLAG_BMASK) {
        int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4;

For faster browsing, not all history is shown. View entire blame