cpu.h 68.4 KB
Newer Older
bellard's avatar
bellard committed
1
/*
2
 *  PowerPC emulation cpu definitions for qemu.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
bellard's avatar
bellard committed
5 6 7 8 9 10 11 12 13 14 15 16
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
17
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard's avatar
bellard committed
18 19 20 21
 */
#if !defined (__CPU_PPC_H__)
#define __CPU_PPC_H__

22
#include "config.h"
23
#include "qemu-common.h"
24

25 26
//#define PPC_EMULATE_32BITS_HYPV

27
#if defined (TARGET_PPC64)
28
/* PowerPC 64 definitions */
29
#define TARGET_LONG_BITS 64
30
#define TARGET_PAGE_BITS 12
31

32 33 34 35 36 37 38 39 40 41 42 43 44 45
/* Note that the official physical address space bits is 62-M where M
   is implementation dependent.  I've not looked up M for the set of
   cpus we emulate at the system level.  */
#define TARGET_PHYS_ADDR_SPACE_BITS 62

/* Note that the PPC environment architecture talks about 80 bit virtual
   addresses, with segmentation.  Obviously that's not all visible to a
   single process, which is all we're concerned with here.  */
#ifdef TARGET_ABI32
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#else
# define TARGET_VIRT_ADDR_SPACE_BITS 64
#endif

46 47
#else /* defined (TARGET_PPC64) */
/* PowerPC 32 definitions */
48
#define TARGET_LONG_BITS 32
49 50 51 52 53 54 55 56

#if defined(TARGET_PPCEMB)
/* Specific definitions for PowerPC embedded */
/* BookE have 36 bits physical address space */
#if defined(CONFIG_USER_ONLY)
/* It looks like a lot of Linux programs assume page size
 * is 4kB long. This is evil, but we have to deal with it...
 */
57
#define TARGET_PAGE_BITS 12
58 59 60 61 62 63 64 65 66
#else /* defined(CONFIG_USER_ONLY) */
/* Pages can be 1 kB small */
#define TARGET_PAGE_BITS 10
#endif /* defined(CONFIG_USER_ONLY) */
#else /* defined(TARGET_PPCEMB) */
/* "standard" PowerPC 32 definitions */
#define TARGET_PAGE_BITS 12
#endif /* defined(TARGET_PPCEMB) */

67 68 69
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32

70
#endif /* defined (TARGET_PPC64) */
bellard's avatar
bellard committed
71

72 73
#define CPUState struct CPUPPCState

bellard's avatar
bellard committed
74 75 76 77
#include "cpu-defs.h"

#include <setjmp.h>

78 79
#include "softfloat.h"

80 81
#define TARGET_HAS_ICE 1

82
#if defined (TARGET_PPC64)
83 84 85 86
#define ELF_MACHINE     EM_PPC64
#else
#define ELF_MACHINE     EM_PPC
#endif
87

88
/*****************************************************************************/
89
/* MMU model                                                                 */
90 91
typedef enum powerpc_mmu_t powerpc_mmu_t;
enum powerpc_mmu_t {
92
    POWERPC_MMU_UNKNOWN    = 0x00000000,
93
    /* Standard 32 bits PowerPC MMU                            */
94
    POWERPC_MMU_32B        = 0x00000001,
95
    /* PowerPC 6xx MMU with software TLB                       */
96
    POWERPC_MMU_SOFT_6xx   = 0x00000002,
97
    /* PowerPC 74xx MMU with software TLB                      */
98
    POWERPC_MMU_SOFT_74xx  = 0x00000003,
99
    /* PowerPC 4xx MMU with software TLB                       */
100
    POWERPC_MMU_SOFT_4xx   = 0x00000004,
101
    /* PowerPC 4xx MMU with software TLB and zones protections */
102
    POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
103
    /* PowerPC MMU in real mode only                           */
104
    POWERPC_MMU_REAL       = 0x00000006,
105
    /* Freescale MPC8xx MMU model                              */
106
    POWERPC_MMU_MPC8xx     = 0x00000007,
107
    /* BookE MMU model                                         */
108
    POWERPC_MMU_BOOKE      = 0x00000008,
109
    /* BookE FSL MMU model                                     */
110
    POWERPC_MMU_BOOKE_FSL  = 0x00000009,
j_mayer's avatar
j_mayer committed
111
    /* PowerPC 601 MMU model (specific BATs format)            */
112
    POWERPC_MMU_601        = 0x0000000A,
113
#if defined(TARGET_PPC64)
114
#define POWERPC_MMU_64       0x00010000
115
    /* 64 bits PowerPC MMU                                     */
116 117 118
    POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,
    /* 620 variant (no segment exceptions)                     */
    POWERPC_MMU_620        = POWERPC_MMU_64 | 0x00000002,
119
#endif /* defined(TARGET_PPC64) */
120 121 122
};

/*****************************************************************************/
123
/* Exception model                                                           */
124 125
typedef enum powerpc_excp_t powerpc_excp_t;
enum powerpc_excp_t {
126
    POWERPC_EXCP_UNKNOWN   = 0,
127
    /* Standard PowerPC exception model */
128
    POWERPC_EXCP_STD,
129
    /* PowerPC 40x exception model      */
130
    POWERPC_EXCP_40x,
131
    /* PowerPC 601 exception model      */
132
    POWERPC_EXCP_601,
133
    /* PowerPC 602 exception model      */
134
    POWERPC_EXCP_602,
135
    /* PowerPC 603 exception model      */
136 137 138 139 140
    POWERPC_EXCP_603,
    /* PowerPC 603e exception model     */
    POWERPC_EXCP_603E,
    /* PowerPC G2 exception model       */
    POWERPC_EXCP_G2,
141
    /* PowerPC 604 exception model      */
142
    POWERPC_EXCP_604,
143
    /* PowerPC 7x0 exception model      */
144
    POWERPC_EXCP_7x0,
145
    /* PowerPC 7x5 exception model      */
146
    POWERPC_EXCP_7x5,
147
    /* PowerPC 74xx exception model     */
148
    POWERPC_EXCP_74xx,
149
    /* BookE exception model            */
150
    POWERPC_EXCP_BOOKE,
151 152 153 154
#if defined(TARGET_PPC64)
    /* PowerPC 970 exception model      */
    POWERPC_EXCP_970,
#endif /* defined(TARGET_PPC64) */
155 156
};

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174
/*****************************************************************************/
/* Exception vectors definitions                                             */
enum {
    POWERPC_EXCP_NONE    = -1,
    /* The 64 first entries are used by the PowerPC embedded specification   */
    POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
    POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
    POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
    POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
    POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
    POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
    POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
    POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
    POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
    POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
    POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
    POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
    POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
175 176
    POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
    POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204
    POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
    /* Vectors 16 to 31 are reserved                                         */
    POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
    POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
    POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
    POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
    POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
    POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
    /* Vectors 38 to 63 are reserved                                         */
    /* Exceptions defined in the PowerPC server specification                */
    POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
    POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
    POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
    POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
    POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
    POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
    POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
    POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
    POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
    POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
    /* 40x specific exceptions                                               */
    POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
    /* 601 specific exceptions                                               */
    POWERPC_EXCP_IO       = 75, /* IO error exception                        */
    POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
    /* 602 specific exceptions                                               */
    POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
    /* 602/603 specific exceptions                                           */
205
    POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
206 207 208 209
    POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
    POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
    /* Exceptions available on most PowerPC                                  */
    POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
210 211 212 213
    POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
    POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
    POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
    POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
214
    /* 7xx/74xx specific exceptions                                          */
215
    POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
216
    /* 74xx specific exceptions                                              */
217
    POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
218
    /* 970FX specific exceptions                                             */
219 220 221 222 223 224 225
    POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
    POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
    /* Freescale embeded cores specific exceptions                           */
    POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
    POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
    POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
    POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
226 227 228 229 230 231 232 233
    /* EOL                                                                   */
    POWERPC_EXCP_NB       = 96,
    /* Qemu exceptions: used internally during code translation              */
    POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
    POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
    /* Qemu exceptions: special cases we want to stop translation            */
    POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
    POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
234
    POWERPC_EXCP_STCX         = 0x204 /* Conditional stores in user mode     */
235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252
};

/* Exceptions error codes                                                    */
enum {
    /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
    POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
    POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
    POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
    POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
    POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
    POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
    /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
    /* FP exceptions                                                         */
    POWERPC_EXCP_FP            = 0x10,
    POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
    POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
    POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
    POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
253
    POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275
    POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
    POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
    POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
    POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
    POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
    POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
    POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
    POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
    /* Invalid instruction                                                   */
    POWERPC_EXCP_INVAL         = 0x20,
    POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
    POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
    POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
    POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
    /* Privileged instruction                                                */
    POWERPC_EXCP_PRIV          = 0x30,
    POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
    POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
    /* Trap                                                                  */
    POWERPC_EXCP_TRAP          = 0x40,
};

276 277
/*****************************************************************************/
/* Input pins model                                                          */
278 279
typedef enum powerpc_input_t powerpc_input_t;
enum powerpc_input_t {
280
    PPC_FLAGS_INPUT_UNKNOWN = 0,
281
    /* PowerPC 6xx bus                  */
282
    PPC_FLAGS_INPUT_6xx,
283
    /* BookE bus                        */
284 285 286
    PPC_FLAGS_INPUT_BookE,
    /* PowerPC 405 bus                  */
    PPC_FLAGS_INPUT_405,
287
    /* PowerPC 970 bus                  */
288 289 290
    PPC_FLAGS_INPUT_970,
    /* PowerPC 401 bus                  */
    PPC_FLAGS_INPUT_401,
291 292
    /* Freescale RCPU bus               */
    PPC_FLAGS_INPUT_RCPU,
293 294
};

295
#define PPC_INPUT(env) (env->bus_model)
296

297
/*****************************************************************************/
298 299
typedef struct ppc_def_t ppc_def_t;
typedef struct opc_handler_t opc_handler_t;
bellard's avatar
bellard committed
300

301 302 303
/*****************************************************************************/
/* Types used to describe some PowerPC registers */
typedef struct CPUPPCState CPUPPCState;
304 305 306 307 308
typedef struct ppc_tb_t ppc_tb_t;
typedef struct ppc_spr_t ppc_spr_t;
typedef struct ppc_dcr_t ppc_dcr_t;
typedef union ppc_avr_t ppc_avr_t;
typedef union ppc_tlb_t ppc_tlb_t;
309

310
/* SPR access micro-ops generations callbacks */
311
struct ppc_spr_t {
312 313
    void (*uea_read)(void *opaque, int gpr_num, int spr_num);
    void (*uea_write)(void *opaque, int spr_num, int gpr_num);
314
#if !defined(CONFIG_USER_ONLY)
315 316 317 318
    void (*oea_read)(void *opaque, int gpr_num, int spr_num);
    void (*oea_write)(void *opaque, int spr_num, int gpr_num);
    void (*hea_read)(void *opaque, int gpr_num, int spr_num);
    void (*hea_write)(void *opaque, int spr_num, int gpr_num);
319
#endif
320
    const char *name;
321 322 323
};

/* Altivec registers (128 bits) */
324
union ppc_avr_t {
aurel32's avatar
aurel32 committed
325
    float32 f[4];
326 327 328
    uint8_t u8[16];
    uint16_t u16[8];
    uint32_t u32[4];
329 330 331
    int8_t s8[16];
    int16_t s16[8];
    int32_t s32[4];
332
    uint64_t u64[2];
333
};
334

335
#if !defined(CONFIG_USER_ONLY)
336
/* Software TLB cache */
337 338
typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
struct ppc6xx_tlb_t {
339 340 341
    target_ulong pte0;
    target_ulong pte1;
    target_ulong EPN;
342 343
};

344 345 346
typedef struct ppcemb_tlb_t ppcemb_tlb_t;
struct ppcemb_tlb_t {
    target_phys_addr_t RPN;
347
    target_ulong EPN;
348
    target_ulong PID;
349 350 351
    target_ulong size;
    uint32_t prot;
    uint32_t attr; /* Storage attributes */
352 353
};

354 355 356
union ppc_tlb_t {
    ppc6xx_tlb_t tlb6;
    ppcemb_tlb_t tlbe;
357
};
358
#endif
359

360 361
typedef struct ppc_slb_t ppc_slb_t;
struct ppc_slb_t {
blueswir1's avatar
blueswir1 committed
362 363 364 365
    uint64_t tmp64;
    uint32_t tmp;
};

366 367
/*****************************************************************************/
/* Machine state register bits definition                                    */
368
#define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
j_mayer's avatar
j_mayer committed
369
#define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
370
#define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
371
#define MSR_SHV  60 /* hypervisor state                               hflags */
372 373
#define MSR_CM   31 /* Computation mode for BookE                     hflags */
#define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
374
#define MSR_THV  29 /* hypervisor state for 32 bits PowerPC           hflags */
375
#define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
376 377
#define MSR_VR   25 /* altivec available                            x hflags */
#define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
378 379
#define MSR_AP   23 /* Access privilege state on 602                  hflags */
#define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
380
#define MSR_KEY  19 /* key bit on 603e                                       */
381
#define MSR_POW  18 /* Power management                                      */
382 383
#define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
#define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
384 385
#define MSR_ILE  16 /* Interrupt little-endian mode                          */
#define MSR_EE   15 /* External interrupt enable                             */
386 387
#define MSR_PR   14 /* Problem state                                  hflags */
#define MSR_FP   13 /* Floating point available                       hflags */
388
#define MSR_ME   12 /* Machine check interrupt enable                        */
389
#define MSR_FE0  11 /* Floating point exception mode 0                hflags */
390 391 392 393 394
#define MSR_SE   10 /* Single-step trace enable                     x hflags */
#define MSR_DWE  10 /* Debug wait enable on 405                     x        */
#define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
#define MSR_BE   9  /* Branch trace enable                          x hflags */
#define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
395
#define MSR_FE1  8  /* Floating point exception mode 1                hflags */
396
#define MSR_AL   7  /* AL bit on POWER                                       */
397
#define MSR_EP   6  /* Exception prefix on 601                               */
398 399
#define MSR_IR   5  /* Instruction relocate                                  */
#define MSR_DR   4  /* Data relocate                                         */
400
#define MSR_PE   3  /* Protection enable on 403                              */
401 402 403 404
#define MSR_PX   2  /* Protection exclusive on 403                  x        */
#define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
#define MSR_RI   1  /* Recoverable interrupt                        1        */
#define MSR_LE   0  /* Little-endian mode                           1 hflags */
405 406 407

#define msr_sf   ((env->msr >> MSR_SF)   & 1)
#define msr_isf  ((env->msr >> MSR_ISF)  & 1)
408
#define msr_shv  ((env->msr >> MSR_SHV)  & 1)
409 410
#define msr_cm   ((env->msr >> MSR_CM)   & 1)
#define msr_icm  ((env->msr >> MSR_ICM)  & 1)
411
#define msr_thv  ((env->msr >> MSR_THV)  & 1)
412 413
#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
#define msr_vr   ((env->msr >> MSR_VR)   & 1)
aurel32's avatar
aurel32 committed
414
#define msr_spe  ((env->msr >> MSR_SPE)  & 1)
415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441
#define msr_ap   ((env->msr >> MSR_AP)   & 1)
#define msr_sa   ((env->msr >> MSR_SA)   & 1)
#define msr_key  ((env->msr >> MSR_KEY)  & 1)
#define msr_pow  ((env->msr >> MSR_POW)  & 1)
#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
#define msr_ce   ((env->msr >> MSR_CE)   & 1)
#define msr_ile  ((env->msr >> MSR_ILE)  & 1)
#define msr_ee   ((env->msr >> MSR_EE)   & 1)
#define msr_pr   ((env->msr >> MSR_PR)   & 1)
#define msr_fp   ((env->msr >> MSR_FP)   & 1)
#define msr_me   ((env->msr >> MSR_ME)   & 1)
#define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
#define msr_se   ((env->msr >> MSR_SE)   & 1)
#define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
#define msr_uble ((env->msr >> MSR_UBLE) & 1)
#define msr_be   ((env->msr >> MSR_BE)   & 1)
#define msr_de   ((env->msr >> MSR_DE)   & 1)
#define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
#define msr_al   ((env->msr >> MSR_AL)   & 1)
#define msr_ep   ((env->msr >> MSR_EP)   & 1)
#define msr_ir   ((env->msr >> MSR_IR)   & 1)
#define msr_dr   ((env->msr >> MSR_DR)   & 1)
#define msr_pe   ((env->msr >> MSR_PE)   & 1)
#define msr_px   ((env->msr >> MSR_PX)   & 1)
#define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
#define msr_ri   ((env->msr >> MSR_RI)   & 1)
#define msr_le   ((env->msr >> MSR_LE)   & 1)
442 443 444 445 446 447 448 449 450 451 452 453 454
/* Hypervisor bit is more specific */
#if defined(TARGET_PPC64)
#define MSR_HVB (1ULL << MSR_SHV)
#define msr_hv  msr_shv
#else
#if defined(PPC_EMULATE_32BITS_HYPV)
#define MSR_HVB (1ULL << MSR_THV)
#define msr_hv  msr_thv
#else
#define MSR_HVB (0ULL)
#define msr_hv  (0)
#endif
#endif
bellard's avatar
bellard committed
455

456 457 458
/* Exception state register bits definition                                  */
#define ESR_ST    23    /* Exception was caused by a store type access.      */

459
enum {
460
    POWERPC_FLAG_NONE     = 0x00000000,
461
    /* Flag for MSR bit 25 signification (VRE/SPE)                           */
462 463
    POWERPC_FLAG_SPE      = 0x00000001,
    POWERPC_FLAG_VRE      = 0x00000002,
464
    /* Flag for MSR bit 17 signification (TGPR/CE)                           */
465 466
    POWERPC_FLAG_TGPR     = 0x00000004,
    POWERPC_FLAG_CE       = 0x00000008,
467
    /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
468 469 470
    POWERPC_FLAG_SE       = 0x00000010,
    POWERPC_FLAG_DWE      = 0x00000020,
    POWERPC_FLAG_UBLE     = 0x00000040,
471
    /* Flag for MSR bit 9 signification (BE/DE)                              */
472 473
    POWERPC_FLAG_BE       = 0x00000080,
    POWERPC_FLAG_DE       = 0x00000100,
474
    /* Flag for MSR bit 2 signification (PX/PMM)                             */
475 476 477 478 479 480
    POWERPC_FLAG_PX       = 0x00000200,
    POWERPC_FLAG_PMM      = 0x00000400,
    /* Flag for special features                                             */
    /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
    POWERPC_FLAG_RTC_CLK  = 0x00010000,
    POWERPC_FLAG_BUS_CLK  = 0x00020000,
481 482
};

483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553
/*****************************************************************************/
/* Floating point status and control register                                */
#define FPSCR_FX     31 /* Floating-point exception summary                  */
#define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
#define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
#define FPSCR_OX     28 /* Floating-point overflow exception                 */
#define FPSCR_UX     27 /* Floating-point underflow exception                */
#define FPSCR_ZX     26 /* Floating-point zero divide exception              */
#define FPSCR_XX     25 /* Floating-point inexact exception                  */
#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
#define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
#define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
#define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
#define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
#define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
#define FPSCR_FR     18 /* Floating-point fraction rounded                   */
#define FPSCR_FI     17 /* Floating-point fraction inexact                   */
#define FPSCR_C      16 /* Floating-point result class descriptor            */
#define FPSCR_FL     15 /* Floating-point less than or negative              */
#define FPSCR_FG     14 /* Floating-point greater than or negative           */
#define FPSCR_FE     13 /* Floating-point equal or zero                      */
#define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
#define FPSCR_FPCC   12 /* Floating-point condition code                     */
#define FPSCR_FPRF   12 /* Floating-point result flags                       */
#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
#define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
#define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
#define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
#define FPSCR_OE     6  /* Floating-point overflow exception enable          */
#define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
#define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
#define FPSCR_XE     3  /* Floating-point inexact exception enable           */
#define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
#define FPSCR_RN1    1
#define FPSCR_RN     0  /* Floating-point rounding control                   */
#define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
#define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
#define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
#define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
#define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
#define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
#define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
#define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
#define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
#define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
#define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
#define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
#define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
#define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
#define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
#define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
#define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
#define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
#define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
#define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)
/* Invalid operation exception summary */
#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
                                  (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
                                  (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
                                  (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
                                  (1 << FPSCR_VXCVI)))
/* exception summary */
#define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
/* enabled exception summary */
#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
                   0x1F)

/*****************************************************************************/
aurel32's avatar
aurel32 committed
554 555 556 557 558 559 560
/* Vector status and control register */
#define VSCR_NJ		16 /* Vector non-java */
#define VSCR_SAT	0 /* Vector saturation */
#define vscr_nj		(((env->vscr) >> VSCR_NJ)	& 0x1)
#define vscr_sat	(((env->vscr) >> VSCR_SAT)	& 0x1)

/*****************************************************************************/
561
/* The whole PowerPC CPU context */
562 563
#define NB_MMU_MODES 3

564 565 566 567
struct CPUPPCState {
    /* First are the most commonly used resources
     * during translated code execution
     */
bellard's avatar
bellard committed
568
    /* general purpose registers */
aurel32's avatar
aurel32 committed
569
    target_ulong gpr[32];
570
#if !defined(TARGET_PPC64)
571
    /* Storage for GPR MSB, used by the SPE extension */
aurel32's avatar
aurel32 committed
572
    target_ulong gprh[32];
573
#endif
574 575 576 577 578
    /* LR */
    target_ulong lr;
    /* CTR */
    target_ulong ctr;
    /* condition register */
aurel32's avatar
aurel32 committed
579
    uint32_t crf[8];
bellard's avatar
bellard committed
580
    /* XER */
581
    target_ulong xer;
bellard's avatar
bellard committed
582
    /* Reservation address */
583 584 585
    target_ulong reserve_addr;
    /* Reservation value */
    target_ulong reserve_val;
586 587 588 589
    /* Reservation store address */
    target_ulong reserve_ea;
    /* Reserved store source register and size */
    target_ulong reserve_info;
590 591

    /* Those ones are used in supervisor mode only */
bellard's avatar
bellard committed
592
    /* machine state register */
593
    target_ulong msr;
594
    /* temporary general purpose registers */
aurel32's avatar
aurel32 committed
595
    target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
596 597

    /* Floating point execution context */
598
    float_status fp_status;
599 600 601
    /* floating point registers */
    float64 fpr[32];
    /* floating point status and control register */
602
    uint32_t fpscr;
603

604 605
    /* Next instruction pointer */
    target_ulong nip;
606

607 608
    int access_type; /* when a memory exception occurs, the access
                        type is stored here */
609

610 611
    CPU_COMMON

612 613 614
    /* MMU context - only relevant for full system emulation */
#if !defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
615 616
    /* Address space register */
    target_ulong asr;
617
    /* PowerPC 64 SLB area */
618
    ppc_slb_t slb[64];
619 620
    int slb_nr;
#endif
621 622
    /* segment registers */
    target_ulong sdr1;
623
    target_ulong sr[32];
624 625 626 627
    /* BATs */
    int nb_BATs;
    target_ulong DBAT[2][8];
    target_ulong IBAT[2][8];
628 629 630 631 632 633 634
    /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
    int nb_tlb;      /* Total number of TLB                                  */
    int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
    int nb_ways;     /* Number of ways in the TLB set                        */
    int last_way;    /* Last used way used to allocate TLB in a LRU way      */
    int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
    int nb_pids;     /* Number of available PID registers                    */
635
    ppc_tlb_t *tlb;  /* TLB is optional. Allocate them only if needed        */
636 637 638
    /* 403 dedicated access protection registers */
    target_ulong pb[4];
#endif
639

640 641 642
    /* Other registers */
    /* Special purpose registers */
    target_ulong spr[1024];
643
    ppc_spr_t spr_cb[1024];
644
    /* Altivec registers */
645
    ppc_avr_t avr[32];
646
    uint32_t vscr;
647
    /* SPE registers */
aurel32's avatar
aurel32 committed
648
    uint64_t spe_acc;
649
    uint32_t spe_fscr;
aurel32's avatar
aurel32 committed
650 651 652
    /* SPE and Altivec can share a status since they will never be used
     * simultaneously */
    float_status vec_status;
653 654

    /* Internal devices resources */
655
    /* Time base and decrementer */
656
    ppc_tb_t *tb_env;
657
    /* Device control registers */
658
    ppc_dcr_t *dcr_env;
659

660 661 662
    int dcache_line_size;
    int icache_line_size;

663 664
    /* Those resources are used during exception processing */
    /* CPU model definition */
665
    target_ulong msr_mask;
666 667 668
    powerpc_mmu_t mmu_model;
    powerpc_excp_t excp_model;
    powerpc_input_t bus_model;
669
    int bfd_mach;
670
    uint32_t flags;
671
    uint64_t insns_flags;
672 673

    int error_code;
674
    uint32_t pending_interrupts;
675 676 677 678 679 680
#if !defined(CONFIG_USER_ONLY)
    /* This is the IRQ controller, which is implementation dependant
     * and only relevant when emulating a complete machine.
     */
    uint32_t irq_input_state;
    void **irq_inputs;
681 682 683
    /* Exception vectors */
    target_ulong excp_vectors[POWERPC_EXCP_NB];
    target_ulong excp_prefix;
Blue Swirl's avatar
Blue Swirl committed
684
    target_ulong hreset_excp_prefix;
685 686
    target_ulong ivor_mask;
    target_ulong ivpr_mask;
687
    target_ulong hreset_vector;
688
#endif
689 690 691

    /* Those resources are used only during code translation */
    /* opcode handlers */
692
    opc_handler_t *opcodes[0x40];
693 694

    /* Those resources are used only in Qemu core */
695 696
    target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */
    target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
697
    int mmu_idx;         /* precomputed MMU index to speed up mem accesses */
698

699 700
    /* Power management */
    int power_mode;
701
    int (*check_pow)(CPUPPCState *env);
702

703 704 705
#if !defined(CONFIG_USER_ONLY)
    void *load_info;    /* Holds boot loading state.  */
#endif
706
};
bellard's avatar
bellard committed
707

708
#if !defined(CONFIG_USER_ONLY)
709
/* Context used internally during MMU translations */
710 711 712 713
typedef struct mmu_ctx_t mmu_ctx_t;
struct mmu_ctx_t {
    target_phys_addr_t raddr;      /* Real address              */
    target_phys_addr_t eaddr;      /* Effective address         */
714
    int prot;                      /* Protection bits           */
715
    target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
716 717
    target_ulong ptem;             /* Virtual segment ID | API  */
    int key;                       /* Access key                */
718
    int nx;                        /* Non-execute area          */
719
};
720
#endif
721

722
/*****************************************************************************/
723
CPUPPCState *cpu_ppc_init (const char *cpu_model);
pbrook's avatar
pbrook committed
724
void ppc_translate_init(void);
725 726
int cpu_ppc_exec (CPUPPCState *s);
void cpu_ppc_close (CPUPPCState *s);
bellard's avatar
bellard committed
727 728 729
/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
730 731
int cpu_ppc_signal_handler (int host_signum, void *pinfo,
                            void *puc);
732 733
int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
                              int mmu_idx, int is_softmmu);
734
#define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
735
#if !defined(CONFIG_USER_ONLY)
736
int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
737
                          int rw, int access_type);
738
#endif
739
void do_interrupt (CPUPPCState *env);
740
void ppc_hw_interrupt (CPUPPCState *env);
741

742
void cpu_dump_rfi (target_ulong RA, target_ulong msr);
743

744
#if !defined(CONFIG_USER_ONLY)
745 746
void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,
                       target_ulong pte0, target_ulong pte1);
747 748 749 750 751 752 753
void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
754 755
#if defined(TARGET_PPC64)
void ppc_store_asr (CPUPPCState *env, target_ulong value);
756
target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
blueswir1's avatar
blueswir1 committed
757 758
target_ulong ppc_load_sr (CPUPPCState *env, int sr_nr);
void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
759
#endif /* defined(TARGET_PPC64) */
760
void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value);
761
#endif /* !defined(CONFIG_USER_ONLY) */
762
void ppc_store_msr (CPUPPCState *env, target_ulong value);
763

764
void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
765

766 767
const ppc_def_t *cpu_ppc_find_by_name (const char *name);
int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
bellard's avatar
bellard committed
768

769 770
/* Time-base and decrementer management */
#ifndef NO_CPU_IO_DEFS
Alexander Graf's avatar
Alexander Graf committed
771
uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
772 773 774
uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
775
uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
776 777 778
uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
779 780
uint32_t cpu_ppc_load_decr (CPUPPCState *env);
void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
781 782 783 784
uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
uint64_t cpu_ppc_load_purr (CPUPPCState *env);
void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
785 786 787 788 789 790 791
uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
#if !defined(CONFIG_USER_ONLY)
void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
target_ulong load_40x_pit (CPUPPCState *env);
void store_40x_pit (CPUPPCState *env, target_ulong val);
792
void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
793
void store_40x_sler (CPUPPCState *env, uint32_t val);
794 795
void store_booke_tcr (CPUPPCState *env, target_ulong val);
void store_booke_tsr (CPUPPCState *env, target_ulong val);
796
void ppc_tlb_invalidate_all (CPUPPCState *env);
797 798 799 800 801
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
#if defined(TARGET_PPC64)
void ppc_slb_invalidate_all (CPUPPCState *env);
void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
#endif
802
int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
803
#endif
804
#endif
bellard's avatar
bellard committed
805

806
static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823
{
    uint64_t gprv;

    gprv = env->gpr[gprn];
#if !defined(TARGET_PPC64)
    if (env->flags & POWERPC_FLAG_SPE) {
        /* If the CPU implements the SPE extension, we have to get the
         * high bits of the GPR from the gprh storage area
         */
        gprv &= 0xFFFFFFFFULL;
        gprv |= (uint64_t)env->gprh[gprn] << 32;
    }
#endif

    return gprv;
}

824
/* Device control registers */
Alexander Graf's avatar
Alexander Graf committed
825 826
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
827

828 829 830 831
#define cpu_init cpu_ppc_init
#define cpu_exec cpu_ppc_exec
#define cpu_gen_code cpu_ppc_gen_code
#define cpu_signal_handler cpu_ppc_signal_handler
j_mayer's avatar
j_mayer committed
832
#define cpu_list ppc_cpu_list
833

Blue Swirl's avatar
Blue Swirl committed
834
#define CPU_SAVE_VERSION 4
835

836 837 838 839 840 841 842 843 844 845
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _user
#define MMU_MODE1_SUFFIX _kernel
#define MMU_MODE2_SUFFIX _hypv
#define MMU_USER_IDX 0
static inline int cpu_mmu_index (CPUState *env)
{
    return env->mmu_idx;
}

846 847 848
#if defined(CONFIG_USER_ONLY)
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
{
pbrook's avatar
pbrook committed
849
    if (newsp)
850
        env->gpr[1] = newsp;
851
    env->gpr[3] = 0;
852 853 854
}
#endif

bellard's avatar
bellard committed
855 856
#include "cpu-all.h"

857
/*****************************************************************************/
858
/* CRF definitions */
859 860 861 862
#define CRF_LT        3
#define CRF_GT        2
#define CRF_EQ        1
#define CRF_SO        0
863 864 865 866
#define CRF_CH        (1 << CRF_LT)
#define CRF_CL        (1 << CRF_GT)
#define CRF_CH_OR_CL  (1 << CRF_EQ)
#define CRF_CH_AND_CL (1 << CRF_SO)
867 868

/* XER definitions */
869 870 871 872 873 874 875 876 877 878
#define XER_SO  31
#define XER_OV  30
#define XER_CA  29
#define XER_CMP  8
#define XER_BC   0
#define xer_so  ((env->xer >> XER_SO)  &    1)
#define xer_ov  ((env->xer >> XER_OV)  &    1)
#define xer_ca  ((env->xer >> XER_CA)  &    1)
#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
#define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
bellard's avatar
bellard committed
879

880
/* SPR definitions */
881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092
#define SPR_MQ                (0x000)
#define SPR_XER               (0x001)
#define SPR_601_VRTCU         (0x004)
#define SPR_601_VRTCL         (0x005)
#define SPR_601_UDECR         (0x006)
#define SPR_LR                (0x008)
#define SPR_CTR               (0x009)
#define SPR_DSISR             (0x012)
#define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
#define SPR_601_RTCU          (0x014)
#define SPR_601_RTCL          (0x015)
#define SPR_DECR              (0x016)
#define SPR_SDR1              (0x019)
#define SPR_SRR0              (0x01A)
#define SPR_SRR1              (0x01B)
#define SPR_AMR               (0x01D)
#define SPR_BOOKE_PID         (0x030)
#define SPR_BOOKE_DECAR       (0x036)
#define SPR_BOOKE_CSRR0       (0x03A)
#define SPR_BOOKE_CSRR1       (0x03B)
#define SPR_BOOKE_DEAR        (0x03D)
#define SPR_BOOKE_ESR         (0x03E)
#define SPR_BOOKE_IVPR        (0x03F)
#define SPR_MPC_EIE           (0x050)
#define SPR_MPC_EID           (0x051)
#define SPR_MPC_NRI           (0x052)
#define SPR_CTRL              (0x088)
#define SPR_MPC_CMPA          (0x090)
#define SPR_MPC_CMPB          (0x091)
#define SPR_MPC_CMPC          (0x092)
#define SPR_MPC_CMPD          (0x093)
#define SPR_MPC_ECR           (0x094)
#define SPR_MPC_DER           (0x095)
#define SPR_MPC_COUNTA        (0x096)
#define SPR_MPC_COUNTB        (0x097)
#define SPR_UCTRL             (0x098)
#define SPR_MPC_CMPE          (0x098)
#define SPR_MPC_CMPF          (0x099)
#define SPR_MPC_CMPG          (0x09A)
#define SPR_MPC_CMPH          (0x09B)
#define SPR_MPC_LCTRL1        (0x09C)
#define SPR_MPC_LCTRL2        (0x09D)
#define SPR_MPC_ICTRL         (0x09E)
#define SPR_MPC_BAR           (0x09F)
#define SPR_VRSAVE            (0x100)
#define SPR_USPRG0            (0x100)
#define SPR_USPRG1            (0x101)
#define SPR_USPRG2            (0x102)
#define SPR_USPRG3            (0x103)
#define SPR_USPRG4            (0x104)
#define SPR_USPRG5            (0x105)
#define SPR_USPRG6            (0x106)
#define SPR_USPRG7            (0x107)
#define SPR_VTBL              (0x10C)
#define SPR_VTBU              (0x10D)
#define SPR_SPRG0             (0x110)
#define SPR_SPRG1             (0x111)
#define SPR_SPRG2             (0x112)
#define SPR_SPRG3             (0x113)
#define SPR_SPRG4             (0x114)
#define SPR_SCOMC             (0x114)
#define SPR_SPRG5             (0x115)
#define SPR_SCOMD             (0x115)
#define SPR_SPRG6             (0x116)
#define SPR_SPRG7             (0x117)
#define SPR_ASR               (0x118)
#define SPR_EAR               (0x11A)
#define SPR_TBL               (0x11C)
#define SPR_TBU               (0x11D)
#define SPR_TBU40             (0x11E)
#define SPR_SVR               (0x11E)
#define SPR_BOOKE_PIR         (0x11E)
#define SPR_PVR               (0x11F)
#define SPR_HSPRG0            (0x130)
#define SPR_BOOKE_DBSR        (0x130)
#define SPR_HSPRG1            (0x131)
#define SPR_HDSISR            (0x132)
#define SPR_HDAR              (0x133)
#define SPR_BOOKE_DBCR0       (0x134)
#define SPR_IBCR              (0x135)
#define SPR_PURR              (0x135)
#define SPR_BOOKE_DBCR1       (0x135)
#define SPR_DBCR              (0x136)
#define SPR_HDEC              (0x136)
#define SPR_BOOKE_DBCR2       (0x136)
#define SPR_HIOR              (0x137)
#define SPR_MBAR              (0x137)
#define SPR_RMOR              (0x138)
#define SPR_BOOKE_IAC1        (0x138)
#define SPR_HRMOR             (0x139)
#define SPR_BOOKE_IAC2        (0x139)
#define SPR_HSRR0             (0x13A)
#define SPR_BOOKE_IAC3        (0x13A)
#define SPR_HSRR1             (0x13B)
#define SPR_BOOKE_IAC4        (0x13B)
#define SPR_LPCR              (0x13C)
#define SPR_BOOKE_DAC1        (0x13C)
#define SPR_LPIDR             (0x13D)
#define SPR_DABR2             (0x13D)
#define SPR_BOOKE_DAC2        (0x13D)
#define SPR_BOOKE_DVC1        (0x13E)
#define SPR_BOOKE_DVC2        (0x13F)
#define SPR_BOOKE_TSR         (0x150)
#define SPR_BOOKE_TCR         (0x154)
#define SPR_BOOKE_IVOR0       (0x190)
#define SPR_BOOKE_IVOR1       (0x191)
#define SPR_BOOKE_IVOR2       (0x192)
#define SPR_BOOKE_IVOR3       (0x193)
#define SPR_BOOKE_IVOR4       (0x194)
#define SPR_BOOKE_IVOR5       (0x195)
#define SPR_BOOKE_IVOR6       (0x196)
#define SPR_BOOKE_IVOR7       (0x197)
#define SPR_BOOKE_IVOR8       (0x198)
#define SPR_BOOKE_IVOR9       (0x199)
#define SPR_BOOKE_IVOR10      (0x19A)
#define SPR_BOOKE_IVOR11      (0x19B)
#define SPR_BOOKE_IVOR12      (0x19C)
#define SPR_BOOKE_IVOR13      (0x19D)
#define SPR_BOOKE_IVOR14      (0x19E)
#define SPR_BOOKE_IVOR15      (0x19F)
#define SPR_BOOKE_SPEFSCR     (0x200)
#define SPR_Exxx_BBEAR        (0x201)
#define SPR_Exxx_BBTAR        (0x202)
#define SPR_Exxx_L1CFG0       (0x203)
#define SPR_Exxx_NPIDR        (0x205)
#define SPR_ATBL              (0x20E)
#define SPR_ATBU              (0x20F)
#define SPR_IBAT0U            (0x210)
#define SPR_BOOKE_IVOR32      (0x210)
#define SPR_RCPU_MI_GRA       (0x210)
#define SPR_IBAT0L            (0x211)
#define SPR_BOOKE_IVOR33      (0x211)
#define SPR_IBAT1U            (0x212)
#define SPR_BOOKE_IVOR34      (0x212)
#define SPR_IBAT1L            (0x213)
#define SPR_BOOKE_IVOR35      (0x213)
#define SPR_IBAT2U            (0x214)
#define SPR_BOOKE_IVOR36      (0x214)
#define SPR_IBAT2L            (0x215)
#define SPR_BOOKE_IVOR37      (0x215)
#define SPR_IBAT3U            (0x216)
#define SPR_IBAT3L            (0x217)
#define SPR_DBAT0U            (0x218)
#define SPR_RCPU_L2U_GRA      (0x218)
#define SPR_DBAT0L            (0x219)
#define SPR_DBAT1U            (0x21A)
#define SPR_DBAT1L            (0x21B)
#define SPR_DBAT2U            (0x21C)
#define SPR_DBAT2L            (0x21D)
#define SPR_DBAT3U            (0x21E)
#define SPR_DBAT3L            (0x21F)
#define SPR_IBAT4U            (0x230)
#define SPR_RPCU_BBCMCR       (0x230)
#define SPR_MPC_IC_CST        (0x230)
#define SPR_Exxx_CTXCR        (0x230)
#define SPR_IBAT4L            (0x231)
#define SPR_MPC_IC_ADR        (0x231)
#define SPR_Exxx_DBCR3        (0x231)
#define SPR_IBAT5U            (0x232)
#define SPR_MPC_IC_DAT        (0x232)
#define SPR_Exxx_DBCNT        (0x232)
#define SPR_IBAT5L            (0x233)
#define SPR_IBAT6U            (0x234)
#define SPR_IBAT6L            (0x235)
#define SPR_IBAT7U            (0x236)
#define SPR_IBAT7L            (0x237)
#define SPR_DBAT4U            (0x238)
#define SPR_RCPU_L2U_MCR      (0x238)
#define SPR_MPC_DC_CST        (0x238)
#define SPR_Exxx_ALTCTXCR     (0x238)
#define SPR_DBAT4L            (0x239)
#define SPR_MPC_DC_ADR        (0x239)
#define SPR_DBAT5U            (0x23A)
#define SPR_BOOKE_MCSRR0      (0x23A)
#define SPR_MPC_DC_DAT        (0x23A)
#define SPR_DBAT5L            (0x23B)
#define SPR_BOOKE_MCSRR1      (0x23B)
#define SPR_DBAT6U            (0x23C)
#define SPR_BOOKE_MCSR        (0x23C)
#define SPR_DBAT6L            (0x23D)
#define SPR_Exxx_MCAR         (0x23D)
#define SPR_DBAT7U            (0x23E)
#define SPR_BOOKE_DSRR0       (0x23E)
#define SPR_DBAT7L            (0x23F)
#define SPR_BOOKE_DSRR1       (0x23F)
#define SPR_BOOKE_SPRG8       (0x25C)
#define SPR_BOOKE_SPRG9       (0x25D)
#define SPR_BOOKE_MAS0        (0x270)
#define SPR_BOOKE_MAS1        (0x271)
#define SPR_BOOKE_MAS2        (0x272)
#define SPR_BOOKE_MAS3        (0x273)
#define SPR_BOOKE_MAS4        (0x274)
#define SPR_BOOKE_MAS5        (0x275)
#define SPR_BOOKE_MAS6        (0x276)
#define SPR_BOOKE_PID1        (0x279)
#define SPR_BOOKE_PID2        (0x27A)
#define SPR_MPC_DPDR          (0x280)
#define SPR_MPC_IMMR          (0x288)
#define SPR_BOOKE_TLB0CFG     (0x2B0)
#define SPR_BOOKE_TLB1CFG     (0x2B1)
#define SPR_BOOKE_TLB2CFG     (0x2B2)
#define SPR_BOOKE_TLB3CFG     (0x2B3)
#define SPR_BOOKE_EPR         (0x2BE)
#define SPR_PERF0             (0x300)
#define SPR_RCPU_MI_RBA0      (0x300)
#define SPR_MPC_MI_CTR        (0x300)
#define SPR_PERF1             (0x301)
#define SPR_RCPU_MI_RBA1      (0x301)
#define SPR_PERF2             (0x302)
#define SPR_RCPU_MI_RBA2      (0x302)
#define SPR_MPC_MI_AP         (0x302)
#define SPR_PERF3             (0x303)
1093
#define SPR_620_PMC1R         (0x303)
1094 1095 1096
#define SPR_RCPU_MI_RBA3      (0x303)
#define SPR_MPC_MI_EPN        (0x303)
#define SPR_PERF4             (0x304)
1097
#define SPR_620_PMC2R         (0x304)
1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112
#define SPR_PERF5             (0x305)
#define SPR_MPC_MI_TWC        (0x305)
#define SPR_PERF6             (0x306)
#define SPR_MPC_MI_RPN        (0x306)
#define SPR_PERF7             (0x307)
#define SPR_PERF8             (0x308)
#define SPR_RCPU_L2U_RBA0     (0x308)
#define SPR_MPC_MD_CTR        (0x308)
#define SPR_PERF9             (0x309)
#define SPR_RCPU_L2U_RBA1     (0x309)
#define SPR_MPC_MD_CASID      (0x309)
#define SPR_PERFA             (0x30A)
#define SPR_RCPU_L2U_RBA2     (0x30A)
#define SPR_MPC_MD_AP         (0x30A)
#define SPR_PERFB             (0x30B)
1113
#define SPR_620_MMCR0R        (0x30B)
1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127
#define SPR_RCPU_L2U_RBA3     (0x30B)
#define SPR_MPC_MD_EPN        (0x30B)
#define SPR_PERFC             (0x30C)
#define SPR_MPC_MD_TWB        (0x30C)
#define SPR_PERFD             (0x30D)
#define SPR_MPC_MD_TWC        (0x30D)
#define SPR_PERFE             (0x30E)
#define SPR_MPC_MD_RPN        (0x30E)
#define SPR_PERFF             (0x30F)
#define SPR_MPC_MD_TW         (0x30F)
#define SPR_UPERF0            (0x310)
#define SPR_UPERF1            (0x311)
#define SPR_UPERF2            (0x312)
#define SPR_UPERF3            (0x313)
1128
#define SPR_620_PMC1W         (0x313)
1129
#define SPR_UPERF4            (0x314)
1130
#define SPR_620_PMC2W         (0x314)
1131 1132 1133 1134 1135 1136 1137
#define SPR_UPERF5            (0x315)
#define SPR_UPERF6            (0x316)
#define SPR_UPERF7            (0x317)
#define SPR_UPERF8            (0x318)
#define SPR_UPERF9            (0x319)
#define SPR_UPERFA            (0x31A)
#define SPR_UPERFB            (0x31B)
1138
#define SPR_620_MMCR0W        (0x31B)
1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167
#define SPR_UPERFC            (0x31C)
#define SPR_UPERFD            (0x31D)
#define SPR_UPERFE            (0x31E)
#define SPR_UPERFF            (0x31F)
#define SPR_RCPU_MI_RA0       (0x320)
#define SPR_MPC_MI_DBCAM      (0x320)
#define SPR_RCPU_MI_RA1       (0x321)
#define SPR_MPC_MI_DBRAM0     (0x321)
#define SPR_RCPU_MI_RA2       (0x322)
#define SPR_MPC_MI_DBRAM1     (0x322)
#define SPR_RCPU_MI_RA3       (0x323)
#define SPR_RCPU_L2U_RA0      (0x328)
#define SPR_MPC_MD_DBCAM      (0x328)
#define SPR_RCPU_L2U_RA1      (0x329)
#define SPR_MPC_MD_DBRAM0     (0x329)
#define SPR_RCPU_L2U_RA2      (0x32A)
#define SPR_MPC_MD_DBRAM1     (0x32A)
#define SPR_RCPU_L2U_RA3      (0x32B)
#define SPR_440_INV0          (0x370)
#define SPR_440_INV1          (0x371)
#define SPR_440_INV2          (0x372)
#define SPR_440_INV3          (0x373)
#define SPR_440_ITV0          (0x374)
#define SPR_440_ITV1          (0x375)
#define SPR_440_ITV2          (0x376)
#define SPR_440_ITV3          (0x377)
#define SPR_440_CCR1          (0x378)
#define SPR_DCRIPR            (0x37B)
#define SPR_PPR               (0x380)
j_mayer's avatar
j_mayer committed
1168
#define SPR_750_GQR0          (0x390)
1169
#define SPR_440_DNV0          (0x390)
j_mayer's avatar
j_mayer committed
1170
#define SPR_750_GQR1          (0x391)
1171
#define SPR_440_DNV1          (0x391)
j_mayer's avatar
j_mayer committed
1172
#define SPR_750_GQR2          (0x392)
1173
#define SPR_440_DNV2          (0x392)
j_mayer's avatar
j_mayer committed
1174
#define SPR_750_GQR3          (0x393)
1175
#define SPR_440_DNV3          (0x393)
j_mayer's avatar
j_mayer committed
1176
#define SPR_750_GQR4          (0x394)
1177
#define SPR_440_DTV0          (0x394)
j_mayer's avatar
j_mayer committed
1178
#define SPR_750_GQR5          (0x395)
1179
#define SPR_440_DTV1          (0x395)
j_mayer's avatar
j_mayer committed
1180
#define SPR_750_GQR6          (0x396)
1181
#define SPR_440_DTV2          (0x396)
j_mayer's avatar
j_mayer committed
1182
#define SPR_750_GQR7          (0x397)
1183
#define SPR_440_DTV3          (0x397)
j_mayer's avatar
j_mayer committed
1184 1185
#define SPR_750_THRM4         (0x398)
#define SPR_750CL_HID2        (0x398)
1186
#define SPR_440_DVLIM         (0x398)
j_mayer's avatar
j_mayer committed
1187
#define SPR_750_WPAR          (0x399)
1188
#define SPR_440_IVLIM         (0x399)
j_mayer's avatar
j_mayer committed
1189 1190
#define SPR_750_DMAU          (0x39A)
#define SPR_750_DMAL          (0x39B)
1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270
#define SPR_440_RSTCFG        (0x39B)
#define SPR_BOOKE_DCDBTRL     (0x39C)
#define SPR_BOOKE_DCDBTRH     (0x39D)
#define SPR_BOOKE_ICDBTRL     (0x39E)
#define SPR_BOOKE_ICDBTRH     (0x39F)
#define SPR_UMMCR2            (0x3A0)
#define SPR_UPMC5             (0x3A1)
#define SPR_UPMC6             (0x3A2)
#define SPR_UBAMR             (0x3A7)
#define SPR_UMMCR0            (0x3A8)
#define SPR_UPMC1             (0x3A9)
#define SPR_UPMC2             (0x3AA)
#define SPR_USIAR             (0x3AB)
#define SPR_UMMCR1            (0x3AC)
#define SPR_UPMC3             (0x3AD)
#define SPR_UPMC4             (0x3AE)
#define SPR_USDA              (0x3AF)
#define SPR_40x_ZPR           (0x3B0)
#define SPR_BOOKE_MAS7        (0x3B0)
#define SPR_620_PMR0          (0x3B0)
#define SPR_MMCR2             (0x3B0)
#define SPR_PMC5              (0x3B1)
#define SPR_40x_PID           (0x3B1)
#define SPR_620_PMR1          (0x3B1)
#define SPR_PMC6              (0x3B2)
#define SPR_440_MMUCR         (0x3B2)
#define SPR_620_PMR2          (0x3B2)
#define SPR_4xx_CCR0          (0x3B3)
#define SPR_BOOKE_EPLC        (0x3B3)
#define SPR_620_PMR3          (0x3B3)
#define SPR_405_IAC3          (0x3B4)
#define SPR_BOOKE_EPSC        (0x3B4)
#define SPR_620_PMR4          (0x3B4)
#define SPR_405_IAC4          (0x3B5)
#define SPR_620_PMR5          (0x3B5)
#define SPR_405_DVC1          (0x3B6)
#define SPR_620_PMR6          (0x3B6)
#define SPR_405_DVC2          (0x3B7)
#define SPR_620_PMR7          (0x3B7)
#define SPR_BAMR              (0x3B7)
#define SPR_MMCR0             (0x3B8)
#define SPR_620_PMR8          (0x3B8)
#define SPR_PMC1              (0x3B9)
#define SPR_40x_SGR           (0x3B9)
#define SPR_620_PMR9          (0x3B9)
#define SPR_PMC2              (0x3BA)
#define SPR_40x_DCWR          (0x3BA)
#define SPR_620_PMRA          (0x3BA)
#define SPR_SIAR              (0x3BB)
#define SPR_405_SLER          (0x3BB)
#define SPR_620_PMRB          (0x3BB)
#define SPR_MMCR1             (0x3BC)
#define SPR_405_SU0R          (0x3BC)
#define SPR_620_PMRC          (0x3BC)
#define SPR_401_SKR           (0x3BC)
#define SPR_PMC3              (0x3BD)
#define SPR_405_DBCR1         (0x3BD)
#define SPR_620_PMRD          (0x3BD)
#define SPR_PMC4              (0x3BE)
#define SPR_620_PMRE          (0x3BE)
#define SPR_SDA               (0x3BF)
#define SPR_620_PMRF          (0x3BF)
#define SPR_403_VTBL          (0x3CC)
#define SPR_403_VTBU          (0x3CD)
#define SPR_DMISS             (0x3D0)
#define SPR_DCMP              (0x3D1)
#define SPR_HASH1             (0x3D2)
#define SPR_HASH2             (0x3D3)
#define SPR_BOOKE_ICDBDR      (0x3D3)
#define SPR_TLBMISS           (0x3D4)
#define SPR_IMISS             (0x3D4)
#define SPR_40x_ESR           (0x3D4)
#define SPR_PTEHI             (0x3D5)
#define SPR_ICMP              (0x3D5)
#define SPR_40x_DEAR          (0x3D5)
#define SPR_PTELO             (0x3D6)
#define SPR_RPA               (0x3D6)
#define SPR_40x_EVPR          (0x3D6)
#define SPR_L3PM              (0x3D7)
#define SPR_403_CDBCR         (0x3D7)
j_mayer's avatar
j_mayer committed
1271
#define SPR_L3ITCR0           (0x3D8)
1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283
#define SPR_TCR               (0x3D8)
#define SPR_40x_TSR           (0x3D8)
#define SPR_IBR               (0x3DA)
#define SPR_40x_TCR           (0x3DA)
#define SPR_ESASRR            (0x3DB)
#define SPR_40x_PIT           (0x3DB)
#define SPR_403_TBL           (0x3DC)
#define SPR_403_TBU           (0x3DD)
#define SPR_SEBR              (0x3DE)
#define SPR_40x_SRR2          (0x3DE)
#define SPR_SER               (0x3DF)
#define SPR_40x_SRR3          (0x3DF)
j_mayer's avatar
j_mayer committed
1284
#define SPR_L3OHCR            (0x3E8)
1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296
#define SPR_L3ITCR1           (0x3E9)
#define SPR_L3ITCR2           (0x3EA)
#define SPR_L3ITCR3           (0x3EB)
#define SPR_HID0              (0x3F0)
#define SPR_40x_DBSR          (0x3F0)
#define SPR_HID1              (0x3F1)
#define SPR_IABR              (0x3F2)
#define SPR_40x_DBCR0         (0x3F2)
#define SPR_601_HID2          (0x3F2)
#define SPR_Exxx_L1CSR0       (0x3F2)
#define SPR_ICTRL             (0x3F3)
#define SPR_HID2              (0x3F3)
j_mayer's avatar
j_mayer committed
1297
#define SPR_750CL_HID4        (0x3F3)
1298 1299 1300
#define SPR_Exxx_L1CSR1       (0x3F3)
#define SPR_440_DBDR          (0x3F3)
#define SPR_LDSTDB            (0x3F4)
j_mayer's avatar
j_mayer committed
1301
#define SPR_750_TDCL          (0x3F4)
1302 1303 1304
#define SPR_40x_IAC1          (0x3F4)
#define SPR_MMUCSR0           (0x3F4)
#define SPR_DABR              (0x3F5)
1305
#define DABR_MASK (~(target_ulong)0x7)
1306 1307 1308 1309 1310 1311 1312
#define SPR_Exxx_BUCSR        (0x3F5)
#define SPR_40x_IAC2          (0x3F5)
#define SPR_601_HID5          (0x3F5)
#define SPR_40x_DAC1          (0x3F6)
#define SPR_MSSCR0            (0x3F6)
#define SPR_970_HID5          (0x3F6)
#define SPR_MSSSR0            (0x3F7)
j_mayer's avatar
j_mayer committed
1313
#define SPR_MSSCR1            (0x3F7)
1314 1315 1316 1317 1318
#define SPR_DABRX             (0x3F7)
#define SPR_40x_DAC2          (0x3F7)
#define SPR_MMUCFG            (0x3F7)
#define SPR_LDSTCR            (0x3F8)
#define SPR_L2PMCR            (0x3F8)
j_mayer's avatar
j_mayer committed
1319
#define SPR_750FX_HID2        (0x3F8)
1320
#define SPR_620_BUSCSR        (0x3F8)
1321 1322
#define SPR_Exxx_L1FINV0      (0x3F8)
#define SPR_L2CR              (0x3F9)
1323
#define SPR_620_L2CR          (0x3F9)
1324
#define SPR_L3CR              (0x3FA)