mips_jazz.c 10.5 KB
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/*
 * QEMU MIPS Jazz support
 *
 * Copyright (c) 2007-2008 Hervé Poussineau
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw.h"
#include "mips.h"
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#include "mips_cpudevs.h"
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#include "pc.h"
#include "isa.h"
#include "fdc.h"
#include "sysemu.h"
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#include "arch_init.h"
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#include "boards.h"
#include "net.h"
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#include "esp.h"
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#include "mips-bios.h"
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#include "loader.h"
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#include "mc146818rtc.h"
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#include "i8254.h"
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#include "pcspk.h"
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#include "blockdev.h"
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#include "sysbus.h"
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#include "exec-memory.h"
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enum jazz_model_e
{
    JAZZ_MAGNUM,
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    JAZZ_PICA61,
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};

static void main_cpu_reset(void *opaque)
{
    CPUState *env = opaque;
    cpu_reset(env);
}

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static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
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{
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    return cpu_inw(0x71);
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}

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static void rtc_write(void *opaque, target_phys_addr_t addr,
                      uint64_t val, unsigned size)
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{
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    cpu_outw(0x71, val & 0xff);
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}

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static const MemoryRegionOps rtc_ops = {
    .read = rtc_read,
    .write = rtc_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
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};

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static uint64_t dma_dummy_read(void *opaque, target_phys_addr_t addr,
                               unsigned size)
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{
    /* Nothing to do. That is only to ensure that
     * the current DMA acknowledge cycle is completed. */
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    return 0xff;
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}

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static void dma_dummy_write(void *opaque, target_phys_addr_t addr,
                            uint64_t val, unsigned size)
{
    /* Nothing to do. That is only to ensure that
     * the current DMA acknowledge cycle is completed. */
}
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static const MemoryRegionOps dma_dummy_ops = {
    .read = dma_dummy_read,
    .write = dma_dummy_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
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};

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#define MAGNUM_BIOS_SIZE_MAX 0x7e000
#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)

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static void cpu_request_exit(void *opaque, int irq, int level)
{
    CPUState *env = cpu_single_env;

    if (env && level) {
        cpu_exit(env);
    }
}

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static void mips_jazz_init(MemoryRegion *address_space,
                           MemoryRegion *address_space_io,
                           ram_addr_t ram_size,
                           const char *cpu_model,
                           enum jazz_model_e jazz_model)
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{
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    char *filename;
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    int bios_size, n;
    CPUState *env;
    qemu_irq *rc4030, *i8259;
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    rc4030_dma *dmas;
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    void* rc4030_opaque;
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    MemoryRegion *rtc = g_new(MemoryRegion, 1);
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    MemoryRegion *i8042 = g_new(MemoryRegion, 1);
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    MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
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    NICInfo *nd;
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    DeviceState *dev;
    SysBusDevice *sysbus;
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    ISABus *isa_bus;
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    ISADevice *pit;
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    DriveInfo *fds[MAX_FD];
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    qemu_irq esp_reset, dma_enable;
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    qemu_irq *cpu_exit_irq;
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    MemoryRegion *ram = g_new(MemoryRegion, 1);
    MemoryRegion *bios = g_new(MemoryRegion, 1);
    MemoryRegion *bios2 = g_new(MemoryRegion, 1);
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    /* init CPUs */
    if (cpu_model == NULL) {
#ifdef TARGET_MIPS64
        cpu_model = "R4000";
#else
        /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
        cpu_model = "24Kf";
#endif
    }
    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find CPU definition\n");
        exit(1);
    }
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    qemu_register_reset(main_cpu_reset, env);
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    /* allocate RAM */
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    memory_region_init_ram(ram, "mips_jazz.ram", ram_size);
    vmstate_register_ram_global(ram);
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    memory_region_add_subregion(address_space, 0, ram);
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    memory_region_init_ram(bios, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
    vmstate_register_ram_global(bios);
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    memory_region_set_readonly(bios, true);
    memory_region_init_alias(bios2, "mips_jazz.bios", bios,
                             0, MAGNUM_BIOS_SIZE);
    memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
    memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
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    /* load the BIOS image. */
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    if (bios_name == NULL)
        bios_name = BIOS_FILENAME;
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    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
    if (filename) {
        bios_size = load_image_targphys(filename, 0xfff00000LL,
                                        MAGNUM_BIOS_SIZE);
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        g_free(filename);
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    } else {
        bios_size = -1;
    }
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    if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
        fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
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                bios_name);
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        exit(1);
    }

    /* Init CPU internal devices */
    cpu_mips_irq_init_cpu(env);
    cpu_mips_clock_init(env);

    /* Chipset */
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    rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas,
                                address_space);
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    memory_region_init_io(dma_dummy, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
    memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
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    /* ISA devices */
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    isa_bus = isa_bus_new(NULL, address_space_io);
    i8259 = i8259_init(isa_bus, env->irq[4]);
    isa_bus_irqs(isa_bus, i8259);
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    cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
    DMA_init(0, cpu_exit_irq);
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    pit = pit_init(isa_bus, 0x40, 0, NULL);
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    pcspk_init(isa_bus, pit);
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    /* ISA IO space at 0x90000000 */
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    isa_mmio_init(0x90000000, 0x01000000);
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    isa_mem_base = 0x11000000;

    /* Video card */
    switch (jazz_model) {
    case JAZZ_MAGNUM:
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        dev = qdev_create(NULL, "sysbus-g364");
        qdev_init_nofail(dev);
        sysbus = sysbus_from_qdev(dev);
        sysbus_mmio_map(sysbus, 0, 0x60080000);
        sysbus_mmio_map(sysbus, 1, 0x40000000);
        sysbus_connect_irq(sysbus, 0, rc4030[3]);
        {
            /* Simple ROM, so user doesn't have to provide one */
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            MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
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            memory_region_init_ram(rom_mr, "g364fb.rom", 0x80000);
            vmstate_register_ram_global(rom_mr);
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            memory_region_set_readonly(rom_mr, true);
            uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
            memory_region_add_subregion(address_space, 0x60000000, rom_mr);
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            rom[0] = 0x10; /* Mips G364 */
        }
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        break;
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    case JAZZ_PICA61:
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        isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
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        break;
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    default:
        break;
    }

    /* Network controller */
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    for (n = 0; n < nb_nics; n++) {
        nd = &nd_table[n];
        if (!nd->model)
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            nd->model = g_strdup("dp83932");
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        if (strcmp(nd->model, "dp83932") == 0) {
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            dp83932_init(nd, 0x80001000, 2, get_system_memory(), rc4030[4],
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                         rc4030_opaque, rc4030_dma_memory_rw);
            break;
        } else if (strcmp(nd->model, "?") == 0) {
            fprintf(stderr, "qemu: Supported NICs: dp83932\n");
            exit(1);
        } else {
            fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
            exit(1);
        }
    }
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    /* SCSI adapter */
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    esp_init(0x80002000, 0,
             rc4030_dma_read, rc4030_dma_write, dmas[0],
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             rc4030[5], &esp_reset, &dma_enable);
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    /* Floppy */
    if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
        fprintf(stderr, "qemu: too many floppy drives\n");
        exit(1);
    }
    for (n = 0; n < MAX_FD; n++) {
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        fds[n] = drive_get(IF_FLOPPY, 0, n);
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    }
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    fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
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    /* Real time clock */
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    rtc_init(isa_bus, 1980, NULL);
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    memory_region_init_io(rtc, &rtc_ops, NULL, "rtc", 0x1000);
    memory_region_add_subregion(address_space, 0x80004000, rtc);
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    /* Keyboard (i8042) */
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    i8042_mm_init(rc4030[6], rc4030[7], i8042, 0x1000, 0x1);
    memory_region_add_subregion(address_space, 0x80005000, i8042);
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    /* Serial ports */
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    if (serial_hds[0]) {
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        serial_mm_init(address_space, 0x80006000, 0, rc4030[8], 8000000/16,
                       serial_hds[0], DEVICE_NATIVE_ENDIAN);
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    }
    if (serial_hds[1]) {
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        serial_mm_init(address_space, 0x80007000, 0, rc4030[9], 8000000/16,
                       serial_hds[1], DEVICE_NATIVE_ENDIAN);
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    }
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    /* Parallel port */
    if (parallel_hds[0])
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        parallel_mm_init(address_space, 0x80008000, 0, rc4030[0],
                         parallel_hds[0]);
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    /* Sound card */
    /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
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    audio_init(isa_bus, NULL);
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    /* NVRAM */
    dev = qdev_create(NULL, "ds1225y");
    qdev_init_nofail(dev);
    sysbus = sysbus_from_qdev(dev);
    sysbus_mmio_map(sysbus, 0, 0x80009000);
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    /* LED indicator */
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    jazz_led_init(address_space, 0x8000f000);
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}

static
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void mips_magnum_init (ram_addr_t ram_size,
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                       const char *boot_device,
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                       const char *kernel_filename, const char *kernel_cmdline,
                       const char *initrd_filename, const char *cpu_model)
{
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        mips_jazz_init(get_system_memory(), get_system_io(),
                       ram_size, cpu_model, JAZZ_MAGNUM);
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}

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static
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void mips_pica61_init (ram_addr_t ram_size,
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                       const char *boot_device,
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                       const char *kernel_filename, const char *kernel_cmdline,
                       const char *initrd_filename, const char *cpu_model)
{
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    mips_jazz_init(get_system_memory(), get_system_io(),
                   ram_size, cpu_model, JAZZ_PICA61);
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}

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static QEMUMachine mips_magnum_machine = {
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    .name = "magnum",
    .desc = "MIPS Magnum",
    .init = mips_magnum_init,
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    .use_scsi = 1,
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};
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static QEMUMachine mips_pica61_machine = {
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    .name = "pica61",
    .desc = "Acer Pica 61",
    .init = mips_pica61_init,
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    .use_scsi = 1,
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};
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static void mips_jazz_machine_init(void)
{
    qemu_register_machine(&mips_magnum_machine);
    qemu_register_machine(&mips_pica61_machine);
}

machine_init(mips_jazz_machine_init);