helper.c 19.2 KB
Newer Older
1 2
/*
 *  sparc helpers
3
 *
bellard's avatar
bellard committed
4
 *  Copyright (c) 2003-2005 Fabrice Bellard
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
20 21 22 23 24 25 26 27 28 29
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include <assert.h>

#include "cpu.h"
#include "exec-all.h"
30

bellard's avatar
bellard committed
31
//#define DEBUG_MMU
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

/* Sparc MMU emulation */

/* thread support */

spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;

void cpu_lock(void)
{
    spin_lock(&global_cpu_lock);
}

void cpu_unlock(void)
{
    spin_unlock(&global_cpu_lock);
}

49
#if defined(CONFIG_USER_ONLY)
bellard's avatar
bellard committed
50 51

int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
52
                               int mmu_idx, int is_softmmu)
bellard's avatar
bellard committed
53
{
bellard's avatar
bellard committed
54 55 56 57
    if (rw & 2)
        env->exception_index = TT_TFAULT;
    else
        env->exception_index = TT_DFAULT;
bellard's avatar
bellard committed
58 59 60 61
    return 1;
}

#else
62

bellard's avatar
bellard committed
63
#ifndef TARGET_SPARC64
bellard's avatar
bellard committed
64 65 66
/*
 * Sparc V8 Reference MMU (SRMMU)
 */
67 68 69 70 71 72 73 74 75 76 77
static const int access_table[8][8] = {
    { 0, 0, 0, 0, 2, 0, 3, 3 },
    { 0, 0, 0, 0, 2, 0, 0, 0 },
    { 2, 2, 0, 0, 0, 2, 3, 3 },
    { 2, 2, 0, 0, 0, 2, 0, 0 },
    { 2, 0, 2, 0, 2, 2, 3, 3 },
    { 2, 0, 2, 0, 2, 0, 2, 0 },
    { 2, 2, 2, 0, 2, 2, 3, 3 },
    { 2, 2, 2, 0, 2, 2, 2, 0 }
};

bellard's avatar
bellard committed
78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
static const int perm_table[2][8] = {
    {
        PAGE_READ,
        PAGE_READ | PAGE_WRITE,
        PAGE_READ | PAGE_EXEC,
        PAGE_READ | PAGE_WRITE | PAGE_EXEC,
        PAGE_EXEC,
        PAGE_READ | PAGE_WRITE,
        PAGE_READ | PAGE_EXEC,
        PAGE_READ | PAGE_WRITE | PAGE_EXEC
    },
    {
        PAGE_READ,
        PAGE_READ | PAGE_WRITE,
        PAGE_READ | PAGE_EXEC,
        PAGE_READ | PAGE_WRITE | PAGE_EXEC,
        PAGE_EXEC,
        PAGE_READ,
        0,
        0,
    }
99 100
};

101
int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
blueswir1's avatar
blueswir1 committed
102
                          int *access_index, target_ulong address, int rw,
103
                          int mmu_idx)
104
{
bellard's avatar
bellard committed
105 106
    int access_perms = 0;
    target_phys_addr_t pde_ptr;
107 108
    uint32_t pde;
    target_ulong virt_addr;
109
    int error_code = 0, is_dirty, is_user;
bellard's avatar
bellard committed
110
    unsigned long page_offset;
111

112
    is_user = mmu_idx == MMU_USER_IDX;
113
    virt_addr = address & TARGET_PAGE_MASK;
blueswir1's avatar
blueswir1 committed
114

115
    if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
blueswir1's avatar
blueswir1 committed
116
        // Boot mode: instruction fetches are taken from PROM
117
        if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) {
blueswir1's avatar
blueswir1 committed
118 119 120 121
            *physical = 0xff0000000ULL | (address & 0x3ffffULL);
            *prot = PAGE_READ | PAGE_EXEC;
            return 0;
        }
blueswir1's avatar
blueswir1 committed
122
        *physical = address;
bellard's avatar
bellard committed
123
        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
bellard's avatar
bellard committed
124
        return 0;
125 126
    }

bellard's avatar
bellard committed
127
    *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
128
    *physical = 0xffffffffffff0000ULL;
bellard's avatar
bellard committed
129

130 131
    /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
    /* Context base + context number */
bellard's avatar
bellard committed
132
    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
bellard's avatar
bellard committed
133
    pde = ldl_phys(pde_ptr);
134 135 136

    /* Ctx pde */
    switch (pde & PTE_ENTRYTYPE_MASK) {
bellard's avatar
bellard committed
137
    default:
138
    case 0: /* Invalid */
blueswir1's avatar
blueswir1 committed
139
        return 1 << 2;
bellard's avatar
bellard committed
140
    case 2: /* L0 PTE, maybe should not happen? */
141
    case 3: /* Reserved */
bellard's avatar
bellard committed
142
        return 4 << 2;
bellard's avatar
bellard committed
143
    case 1: /* L0 PDE */
blueswir1's avatar
blueswir1 committed
144
        pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
bellard's avatar
bellard committed
145
        pde = ldl_phys(pde_ptr);
146

blueswir1's avatar
blueswir1 committed
147 148 149 150 151 152 153 154
        switch (pde & PTE_ENTRYTYPE_MASK) {
        default:
        case 0: /* Invalid */
            return (1 << 8) | (1 << 2);
        case 3: /* Reserved */
            return (1 << 8) | (4 << 2);
        case 1: /* L1 PDE */
            pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
bellard's avatar
bellard committed
155
            pde = ldl_phys(pde_ptr);
156

blueswir1's avatar
blueswir1 committed
157 158 159 160 161 162 163 164
            switch (pde & PTE_ENTRYTYPE_MASK) {
            default:
            case 0: /* Invalid */
                return (2 << 8) | (1 << 2);
            case 3: /* Reserved */
                return (2 << 8) | (4 << 2);
            case 1: /* L2 PDE */
                pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
bellard's avatar
bellard committed
165
                pde = ldl_phys(pde_ptr);
166

blueswir1's avatar
blueswir1 committed
167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187
                switch (pde & PTE_ENTRYTYPE_MASK) {
                default:
                case 0: /* Invalid */
                    return (3 << 8) | (1 << 2);
                case 1: /* PDE, should not happen */
                case 3: /* Reserved */
                    return (3 << 8) | (4 << 2);
                case 2: /* L3 PTE */
                    virt_addr = address & TARGET_PAGE_MASK;
                    page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
                }
                break;
            case 2: /* L2 PTE */
                virt_addr = address & ~0x3ffff;
                page_offset = address & 0x3ffff;
            }
            break;
        case 2: /* L1 PTE */
            virt_addr = address & ~0xffffff;
            page_offset = address & 0xffffff;
        }
188 189 190
    }

    /* update page modified and dirty bits */
bellard's avatar
bellard committed
191
    is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
192
    if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
blueswir1's avatar
blueswir1 committed
193 194 195
        pde |= PG_ACCESSED_MASK;
        if (is_dirty)
            pde |= PG_MODIFIED_MASK;
bellard's avatar
bellard committed
196
        stl_phys_notdirty(pde_ptr, pde);
197 198 199
    }
    /* check access */
    access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
bellard's avatar
bellard committed
200
    error_code = access_table[*access_index][access_perms];
bellard's avatar
bellard committed
201
    if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
blueswir1's avatar
blueswir1 committed
202
        return error_code;
203 204

    /* the page can be put in the TLB */
bellard's avatar
bellard committed
205 206
    *prot = perm_table[is_user][access_perms];
    if (!(pde & PG_MODIFIED_MASK)) {
207 208
        /* only set write access if already dirty... otherwise wait
           for dirty access */
bellard's avatar
bellard committed
209
        *prot &= ~PAGE_WRITE;
210 211 212 213
    }

    /* Even if large ptes, we map only one 4KB page in the cache to
       avoid filling it too fast */
214
    *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
bellard's avatar
bellard committed
215
    return error_code;
bellard's avatar
bellard committed
216 217 218
}

/* Perform address translation */
219
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
220
                              int mmu_idx, int is_softmmu)
bellard's avatar
bellard committed
221
{
222
    target_phys_addr_t paddr;
223
    target_ulong vaddr;
bellard's avatar
bellard committed
224
    int error_code = 0, prot, ret = 0, access_index;
225

226
    error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx);
bellard's avatar
bellard committed
227
    if (error_code == 0) {
blueswir1's avatar
blueswir1 committed
228 229
        vaddr = address & TARGET_PAGE_MASK;
        paddr &= TARGET_PAGE_MASK;
bellard's avatar
bellard committed
230
#ifdef DEBUG_MMU
blueswir1's avatar
blueswir1 committed
231
        printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
232
               TARGET_FMT_lx "\n", address, paddr, vaddr);
bellard's avatar
bellard committed
233
#endif
234
        ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
blueswir1's avatar
blueswir1 committed
235
        return ret;
bellard's avatar
bellard committed
236
    }
237 238

    if (env->mmuregs[3]) /* Fault status register */
blueswir1's avatar
blueswir1 committed
239
        env->mmuregs[3] = 1; /* overflow (not read before another fault) */
bellard's avatar
bellard committed
240
    env->mmuregs[3] |= (access_index << 5) | error_code | 2;
241 242
    env->mmuregs[4] = address; /* Fault address register */

bellard's avatar
bellard committed
243
    if ((env->mmuregs[0] & MMU_NF) || env->psret == 0)  {
bellard's avatar
bellard committed
244 245 246 247
        // No fault mode: if a mapping is available, just override
        // permissions. If no mapping is available, redirect accesses to
        // neverland. Fake/overridden mappings will be flushed when
        // switching to normal mode.
blueswir1's avatar
blueswir1 committed
248
        vaddr = address & TARGET_PAGE_MASK;
bellard's avatar
bellard committed
249
        prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
250
        ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
blueswir1's avatar
blueswir1 committed
251
        return ret;
bellard's avatar
bellard committed
252 253 254 255 256 257
    } else {
        if (rw & 2)
            env->exception_index = TT_TFAULT;
        else
            env->exception_index = TT_DFAULT;
        return 1;
bellard's avatar
bellard committed
258
    }
259
}
260 261 262 263 264 265 266

target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
{
    target_phys_addr_t pde_ptr;
    uint32_t pde;

    /* Context base + context number */
267 268
    pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
        (env->mmuregs[2] << 2);
269 270 271 272 273 274 275
    pde = ldl_phys(pde_ptr);

    switch (pde & PTE_ENTRYTYPE_MASK) {
    default:
    case 0: /* Invalid */
    case 2: /* PTE, maybe should not happen? */
    case 3: /* Reserved */
blueswir1's avatar
blueswir1 committed
276
        return 0;
277
    case 1: /* L1 PDE */
blueswir1's avatar
blueswir1 committed
278 279 280
        if (mmulev == 3)
            return pde;
        pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
281 282
        pde = ldl_phys(pde_ptr);

blueswir1's avatar
blueswir1 committed
283 284 285 286 287 288 289 290 291 292 293
        switch (pde & PTE_ENTRYTYPE_MASK) {
        default:
        case 0: /* Invalid */
        case 3: /* Reserved */
            return 0;
        case 2: /* L1 PTE */
            return pde;
        case 1: /* L2 PDE */
            if (mmulev == 2)
                return pde;
            pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
294 295
            pde = ldl_phys(pde_ptr);

blueswir1's avatar
blueswir1 committed
296 297 298 299 300 301 302 303 304 305 306
            switch (pde & PTE_ENTRYTYPE_MASK) {
            default:
            case 0: /* Invalid */
            case 3: /* Reserved */
                return 0;
            case 2: /* L2 PTE */
                return pde;
            case 1: /* L3 PDE */
                if (mmulev == 1)
                    return pde;
                pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
307 308
                pde = ldl_phys(pde_ptr);

blueswir1's avatar
blueswir1 committed
309 310 311 312 313 314 315 316 317 318 319
                switch (pde & PTE_ENTRYTYPE_MASK) {
                default:
                case 0: /* Invalid */
                case 1: /* PDE, should not happen */
                case 3: /* Reserved */
                    return 0;
                case 2: /* L3 PTE */
                    return pde;
                }
            }
        }
320 321 322 323 324 325 326
    }
    return 0;
}

#ifdef DEBUG_MMU
void dump_mmu(CPUState *env)
{
327 328 329
    target_ulong va, va1, va2;
    unsigned int n, m, o;
    target_phys_addr_t pde_ptr, pa;
330 331 332 333 334
    uint32_t pde;

    printf("MMU dump:\n");
    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
    pde = ldl_phys(pde_ptr);
335 336
    printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
           (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
337
    for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
blueswir1's avatar
blueswir1 committed
338 339 340 341
        pde = mmu_probe(env, va, 2);
        if (pde) {
            pa = cpu_get_phys_page_debug(env, va);
            printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
342
                   " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
blueswir1's avatar
blueswir1 committed
343 344 345 346 347
            for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
                pde = mmu_probe(env, va1, 1);
                if (pde) {
                    pa = cpu_get_phys_page_debug(env, va1);
                    printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
348
                           " PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
blueswir1's avatar
blueswir1 committed
349 350 351 352 353
                    for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
                        pde = mmu_probe(env, va2, 0);
                        if (pde) {
                            pa = cpu_get_phys_page_debug(env, va2);
                            printf("  VA: " TARGET_FMT_lx ", PA: "
354 355
                                   TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
                                   va2, pa, pde);
blueswir1's avatar
blueswir1 committed
356 357 358 359 360
                        }
                    }
                }
            }
        }
361 362 363 364 365 366
    }
    printf("MMU dump ends\n");
}
#endif /* DEBUG_MMU */

#else /* !TARGET_SPARC64 */
bellard's avatar
bellard committed
367 368 369
/*
 * UltraSparc IIi I/DMMUs
 */
bellard's avatar
bellard committed
370
static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,
blueswir1's avatar
blueswir1 committed
371 372
                          int *access_index, target_ulong address, int rw,
                          int is_user)
bellard's avatar
bellard committed
373 374 375 376 377
{
    target_ulong mask;
    unsigned int i;

    if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
blueswir1's avatar
blueswir1 committed
378 379
        *physical = address;
        *prot = PAGE_READ | PAGE_WRITE;
bellard's avatar
bellard committed
380 381 382 383
        return 0;
    }

    for (i = 0; i < 64; i++) {
blueswir1's avatar
blueswir1 committed
384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410
        switch ((env->dtlb_tte[i] >> 61) & 3) {
        default:
        case 0x0: // 8k
            mask = 0xffffffffffffe000ULL;
            break;
        case 0x1: // 64k
            mask = 0xffffffffffff0000ULL;
            break;
        case 0x2: // 512k
            mask = 0xfffffffffff80000ULL;
            break;
        case 0x3: // 4M
            mask = 0xffffffffffc00000ULL;
            break;
        }
        // ctx match, vaddr match?
        if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
            (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
            // valid, access ok?
            if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
                ((env->dtlb_tte[i] & 0x4) && is_user) ||
                (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
                if (env->dmmuregs[3]) /* Fault status register */
                    env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
                env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
                env->dmmuregs[4] = address; /* Fault address register */
                env->exception_index = TT_DFAULT;
bellard's avatar
bellard committed
411
#ifdef DEBUG_MMU
blueswir1's avatar
blueswir1 committed
412
                printf("DFAULT at 0x%" PRIx64 "\n", address);
bellard's avatar
bellard committed
413
#endif
blueswir1's avatar
blueswir1 committed
414 415 416 417 418 419 420 421
                return 1;
            }
            *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
            *prot = PAGE_READ;
            if (env->dtlb_tte[i] & 0x2)
                *prot |= PAGE_WRITE;
            return 0;
        }
bellard's avatar
bellard committed
422
    }
bellard's avatar
bellard committed
423
#ifdef DEBUG_MMU
bellard's avatar
bellard committed
424
    printf("DMISS at 0x%" PRIx64 "\n", address);
bellard's avatar
bellard committed
425 426
#endif
    env->exception_index = TT_DMISS;
bellard's avatar
bellard committed
427 428 429 430
    return 1;
}

static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,
blueswir1's avatar
blueswir1 committed
431 432
                          int *access_index, target_ulong address, int rw,
                          int is_user)
bellard's avatar
bellard committed
433 434 435 436 437
{
    target_ulong mask;
    unsigned int i;

    if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
blueswir1's avatar
blueswir1 committed
438 439
        *physical = address;
        *prot = PAGE_EXEC;
bellard's avatar
bellard committed
440 441
        return 0;
    }
bellard's avatar
bellard committed
442

bellard's avatar
bellard committed
443
    for (i = 0; i < 64; i++) {
blueswir1's avatar
blueswir1 committed
444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468
        switch ((env->itlb_tte[i] >> 61) & 3) {
        default:
        case 0x0: // 8k
            mask = 0xffffffffffffe000ULL;
            break;
        case 0x1: // 64k
            mask = 0xffffffffffff0000ULL;
            break;
        case 0x2: // 512k
            mask = 0xfffffffffff80000ULL;
            break;
        case 0x3: // 4M
            mask = 0xffffffffffc00000ULL;
                break;
        }
        // ctx match, vaddr match?
        if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
            (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
            // valid, access ok?
            if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
                ((env->itlb_tte[i] & 0x4) && is_user)) {
                if (env->immuregs[3]) /* Fault status register */
                    env->immuregs[3] = 2; /* overflow (not read before another fault) */
                env->immuregs[3] |= (is_user << 3) | 1;
                env->exception_index = TT_TFAULT;
bellard's avatar
bellard committed
469
#ifdef DEBUG_MMU
blueswir1's avatar
blueswir1 committed
470
                printf("TFAULT at 0x%" PRIx64 "\n", address);
bellard's avatar
bellard committed
471
#endif
blueswir1's avatar
blueswir1 committed
472 473 474 475 476 477
                return 1;
            }
            *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
            *prot = PAGE_EXEC;
            return 0;
        }
bellard's avatar
bellard committed
478
    }
bellard's avatar
bellard committed
479
#ifdef DEBUG_MMU
bellard's avatar
bellard committed
480
    printf("TMISS at 0x%" PRIx64 "\n", address);
bellard's avatar
bellard committed
481 482
#endif
    env->exception_index = TT_TMISS;
bellard's avatar
bellard committed
483 484 485 486
    return 1;
}

int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot,
blueswir1's avatar
blueswir1 committed
487
                          int *access_index, target_ulong address, int rw,
488
                          int mmu_idx)
bellard's avatar
bellard committed
489
{
490 491
    int is_user = mmu_idx == MMU_USER_IDX;

bellard's avatar
bellard committed
492
    if (rw == 2)
blueswir1's avatar
blueswir1 committed
493
        return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
bellard's avatar
bellard committed
494
    else
blueswir1's avatar
blueswir1 committed
495
        return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
bellard's avatar
bellard committed
496 497 498 499
}

/* Perform address translation */
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
500
                              int mmu_idx, int is_softmmu)
bellard's avatar
bellard committed
501
{
bellard's avatar
bellard committed
502
    target_ulong virt_addr, vaddr;
bellard's avatar
bellard committed
503 504 505
    target_phys_addr_t paddr;
    int error_code = 0, prot, ret = 0, access_index;

506
    error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx);
bellard's avatar
bellard committed
507
    if (error_code == 0) {
blueswir1's avatar
blueswir1 committed
508 509
        virt_addr = address & TARGET_PAGE_MASK;
        vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
bellard's avatar
bellard committed
510
#ifdef DEBUG_MMU
blueswir1's avatar
blueswir1 committed
511
        printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
bellard's avatar
bellard committed
512
#endif
513
        ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
blueswir1's avatar
blueswir1 committed
514
        return ret;
bellard's avatar
bellard committed
515 516 517 518 519
    }
    // XXX
    return 1;
}

bellard's avatar
bellard committed
520 521 522 523 524 525
#ifdef DEBUG_MMU
void dump_mmu(CPUState *env)
{
    unsigned int i;
    const char *mask;

bellard's avatar
bellard committed
526
    printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]);
bellard's avatar
bellard committed
527
    if ((env->lsu & DMMU_E) == 0) {
blueswir1's avatar
blueswir1 committed
528
        printf("DMMU disabled\n");
bellard's avatar
bellard committed
529
    } else {
blueswir1's avatar
blueswir1 committed
530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557
        printf("DMMU dump:\n");
        for (i = 0; i < 64; i++) {
            switch ((env->dtlb_tte[i] >> 61) & 3) {
            default:
            case 0x0:
                mask = "  8k";
                break;
            case 0x1:
                mask = " 64k";
                break;
            case 0x2:
                mask = "512k";
                break;
            case 0x3:
                mask = "  4M";
                break;
            }
            if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
                printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
                       env->dtlb_tag[i] & ~0x1fffULL,
                       env->dtlb_tte[i] & 0x1ffffffe000ULL,
                       mask,
                       env->dtlb_tte[i] & 0x4? "priv": "user",
                       env->dtlb_tte[i] & 0x2? "RW": "RO",
                       env->dtlb_tte[i] & 0x40? "locked": "unlocked",
                       env->dtlb_tag[i] & 0x1fffULL);
            }
        }
bellard's avatar
bellard committed
558 559
    }
    if ((env->lsu & IMMU_E) == 0) {
blueswir1's avatar
blueswir1 committed
560
        printf("IMMU disabled\n");
bellard's avatar
bellard committed
561
    } else {
blueswir1's avatar
blueswir1 committed
562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588
        printf("IMMU dump:\n");
        for (i = 0; i < 64; i++) {
            switch ((env->itlb_tte[i] >> 61) & 3) {
            default:
            case 0x0:
                mask = "  8k";
                break;
            case 0x1:
                mask = " 64k";
                break;
            case 0x2:
                mask = "512k";
                break;
            case 0x3:
                mask = "  4M";
                break;
            }
            if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
                printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
                       env->itlb_tag[i] & ~0x1fffULL,
                       env->itlb_tte[i] & 0x1ffffffe000ULL,
                       mask,
                       env->itlb_tte[i] & 0x4? "priv": "user",
                       env->itlb_tte[i] & 0x40? "locked": "unlocked",
                       env->itlb_tag[i] & 0x1fffULL);
            }
        }
bellard's avatar
bellard committed
589 590
    }
}
591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606
#endif /* DEBUG_MMU */

#endif /* TARGET_SPARC64 */
#endif /* !CONFIG_USER_ONLY */

void memcpy32(target_ulong *dst, const target_ulong *src)
{
    dst[0] = src[0];
    dst[1] = src[1];
    dst[2] = src[2];
    dst[3] = src[3];
    dst[4] = src[4];
    dst[5] = src[5];
    dst[6] = src[6];
    dst[7] = src[7];
}