translate.c 358 KB
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/*
 *  ARM translation
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 *
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 *  Copyright (c) 2003 Fabrice Bellard
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 *  Copyright (c) 2005-2007 CodeSourcery
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 *  Copyright (c) 2007 OpenedHand, Ltd.
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 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>

#include "cpu.h"
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#include "disas/disas.h"
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#include "tcg-op.h"
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#include "qemu/log.h"
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#include "qemu/bitops.h"
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#include "helper.h"
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#define GEN_HELPER 1
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#include "helper.h"
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#define ENABLE_ARCH_4T    arm_feature(env, ARM_FEATURE_V4T)
#define ENABLE_ARCH_5     arm_feature(env, ARM_FEATURE_V5)
/* currently all emulated v5 cores are also v5TE, so don't bother */
#define ENABLE_ARCH_5TE   arm_feature(env, ARM_FEATURE_V5)
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#define ENABLE_ARCH_5J    0
#define ENABLE_ARCH_6     arm_feature(env, ARM_FEATURE_V6)
#define ENABLE_ARCH_6K   arm_feature(env, ARM_FEATURE_V6K)
#define ENABLE_ARCH_6T2   arm_feature(env, ARM_FEATURE_THUMB2)
#define ENABLE_ARCH_7     arm_feature(env, ARM_FEATURE_V7)
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#define ENABLE_ARCH_8     arm_feature(env, ARM_FEATURE_V8)
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#define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
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#include "translate.h"
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static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];

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#if defined(CONFIG_USER_ONLY)
#define IS_USER(s) 1
#else
#define IS_USER(s) (s->user)
#endif

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/* These instructions trap after executing, so defer them until after the
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   conditional execution state has been updated.  */
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#define DISAS_WFI 4
#define DISAS_SWI 5
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TCGv_ptr cpu_env;
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/* We reuse the same 64-bit temporaries for efficiency.  */
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static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
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static TCGv_i32 cpu_R[16];
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static TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;
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static TCGv_i32 cpu_exclusive_addr;
static TCGv_i32 cpu_exclusive_val;
static TCGv_i32 cpu_exclusive_high;
#ifdef CONFIG_USER_ONLY
static TCGv_i32 cpu_exclusive_test;
static TCGv_i32 cpu_exclusive_info;
#endif
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/* FIXME:  These should be removed.  */
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static TCGv_i32 cpu_F0s, cpu_F1s;
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static TCGv_i64 cpu_F0d, cpu_F1d;
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#include "exec/gen-icount.h"
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static const char *regnames[] =
    { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
      "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };

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/* initialize TCG globals.  */
void arm_translate_init(void)
{
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    int i;

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    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");

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    for (i = 0; i < 16; i++) {
        cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
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                                          offsetof(CPUARMState, regs[i]),
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                                          regnames[i]);
    }
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    cpu_CF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, CF), "CF");
    cpu_NF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, NF), "NF");
    cpu_VF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, VF), "VF");
    cpu_ZF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, ZF), "ZF");

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    cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
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        offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
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    cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
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        offsetof(CPUARMState, exclusive_val), "exclusive_val");
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    cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
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        offsetof(CPUARMState, exclusive_high), "exclusive_high");
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#ifdef CONFIG_USER_ONLY
    cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
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        offsetof(CPUARMState, exclusive_test), "exclusive_test");
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    cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
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        offsetof(CPUARMState, exclusive_info), "exclusive_info");
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#endif
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#define GEN_HELPER 2
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#include "helper.h"
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}

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static inline TCGv_i32 load_cpu_offset(int offset)
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{
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    TCGv_i32 tmp = tcg_temp_new_i32();
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    tcg_gen_ld_i32(tmp, cpu_env, offset);
    return tmp;
}

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#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
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static inline void store_cpu_offset(TCGv_i32 var, int offset)
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{
    tcg_gen_st_i32(var, cpu_env, offset);
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    tcg_temp_free_i32(var);
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}

#define store_cpu_field(var, name) \
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    store_cpu_offset(var, offsetof(CPUARMState, name))
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/* Set a variable to the value of a CPU register.  */
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static void load_reg_var(DisasContext *s, TCGv_i32 var, int reg)
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{
    if (reg == 15) {
        uint32_t addr;
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        /* normally, since we updated PC, we need only to add one insn */
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        if (s->thumb)
            addr = (long)s->pc + 2;
        else
            addr = (long)s->pc + 4;
        tcg_gen_movi_i32(var, addr);
    } else {
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        tcg_gen_mov_i32(var, cpu_R[reg]);
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    }
}

/* Create a new temporary and set it to the value of a CPU register.  */
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static inline TCGv_i32 load_reg(DisasContext *s, int reg)
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{
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    TCGv_i32 tmp = tcg_temp_new_i32();
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    load_reg_var(s, tmp, reg);
    return tmp;
}

/* Set a CPU register.  The source must be a temporary and will be
   marked as dead.  */
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static void store_reg(DisasContext *s, int reg, TCGv_i32 var)
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{
    if (reg == 15) {
        tcg_gen_andi_i32(var, var, ~1);
        s->is_jmp = DISAS_JUMP;
    }
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    tcg_gen_mov_i32(cpu_R[reg], var);
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    tcg_temp_free_i32(var);
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}

/* Value extensions.  */
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#define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
#define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
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#define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
#define gen_sxth(var) tcg_gen_ext16s_i32(var, var)

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#define gen_sxtb16(var) gen_helper_sxtb16(var, var)
#define gen_uxtb16(var) gen_helper_uxtb16(var, var)
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static inline void gen_set_cpsr(TCGv_i32 var, uint32_t mask)
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{
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    TCGv_i32 tmp_mask = tcg_const_i32(mask);
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    gen_helper_cpsr_write(cpu_env, var, tmp_mask);
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    tcg_temp_free_i32(tmp_mask);
}
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/* Set NZCV flags from the high 4 bits of var.  */
#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)

static void gen_exception(int excp)
{
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    TCGv_i32 tmp = tcg_temp_new_i32();
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    tcg_gen_movi_i32(tmp, excp);
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    gen_helper_exception(cpu_env, tmp);
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    tcg_temp_free_i32(tmp);
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}

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static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
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{
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    TCGv_i32 tmp1 = tcg_temp_new_i32();
    TCGv_i32 tmp2 = tcg_temp_new_i32();
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    tcg_gen_ext16s_i32(tmp1, a);
    tcg_gen_ext16s_i32(tmp2, b);
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    tcg_gen_mul_i32(tmp1, tmp1, tmp2);
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    tcg_temp_free_i32(tmp2);
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    tcg_gen_sari_i32(a, a, 16);
    tcg_gen_sari_i32(b, b, 16);
    tcg_gen_mul_i32(b, b, a);
    tcg_gen_mov_i32(a, tmp1);
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    tcg_temp_free_i32(tmp1);
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}

/* Byteswap each halfword.  */
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static void gen_rev16(TCGv_i32 var)
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{
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    TCGv_i32 tmp = tcg_temp_new_i32();
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    tcg_gen_shri_i32(tmp, var, 8);
    tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
    tcg_gen_shli_i32(var, var, 8);
    tcg_gen_andi_i32(var, var, 0xff00ff00);
    tcg_gen_or_i32(var, var, tmp);
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    tcg_temp_free_i32(tmp);
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}

/* Byteswap low halfword and sign extend.  */
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static void gen_revsh(TCGv_i32 var)
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{
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    tcg_gen_ext16u_i32(var, var);
    tcg_gen_bswap16_i32(var, var);
    tcg_gen_ext16s_i32(var, var);
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}

/* Unsigned bitfield extract.  */
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static void gen_ubfx(TCGv_i32 var, int shift, uint32_t mask)
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{
    if (shift)
        tcg_gen_shri_i32(var, var, shift);
    tcg_gen_andi_i32(var, var, mask);
}

/* Signed bitfield extract.  */
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static void gen_sbfx(TCGv_i32 var, int shift, int width)
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{
    uint32_t signbit;

    if (shift)
        tcg_gen_sari_i32(var, var, shift);
    if (shift + width < 32) {
        signbit = 1u << (width - 1);
        tcg_gen_andi_i32(var, var, (1u << width) - 1);
        tcg_gen_xori_i32(var, var, signbit);
        tcg_gen_subi_i32(var, var, signbit);
    }
}

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/* Return (b << 32) + a. Mark inputs as dead */
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static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv_i32 b)
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{
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    TCGv_i64 tmp64 = tcg_temp_new_i64();

    tcg_gen_extu_i32_i64(tmp64, b);
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    tcg_temp_free_i32(b);
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    tcg_gen_shli_i64(tmp64, tmp64, 32);
    tcg_gen_add_i64(a, tmp64, a);

    tcg_temp_free_i64(tmp64);
    return a;
}

/* Return (b << 32) - a. Mark inputs as dead. */
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static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv_i32 b)
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{
    TCGv_i64 tmp64 = tcg_temp_new_i64();

    tcg_gen_extu_i32_i64(tmp64, b);
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    tcg_temp_free_i32(b);
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    tcg_gen_shli_i64(tmp64, tmp64, 32);
    tcg_gen_sub_i64(a, tmp64, a);

    tcg_temp_free_i64(tmp64);
    return a;
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}

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/* 32x32->64 multiply.  Marks inputs as dead.  */
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static TCGv_i64 gen_mulu_i64_i32(TCGv_i32 a, TCGv_i32 b)
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{
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    TCGv_i32 lo = tcg_temp_new_i32();
    TCGv_i32 hi = tcg_temp_new_i32();
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    TCGv_i64 ret;
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    tcg_gen_mulu2_i32(lo, hi, a, b);
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    tcg_temp_free_i32(a);
    tcg_temp_free_i32(b);
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    ret = tcg_temp_new_i64();
    tcg_gen_concat_i32_i64(ret, lo, hi);
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    tcg_temp_free_i32(lo);
    tcg_temp_free_i32(hi);
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    return ret;
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}

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static TCGv_i64 gen_muls_i64_i32(TCGv_i32 a, TCGv_i32 b)
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{
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    TCGv_i32 lo = tcg_temp_new_i32();
    TCGv_i32 hi = tcg_temp_new_i32();
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    TCGv_i64 ret;
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    tcg_gen_muls2_i32(lo, hi, a, b);
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    tcg_temp_free_i32(a);
    tcg_temp_free_i32(b);
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    ret = tcg_temp_new_i64();
    tcg_gen_concat_i32_i64(ret, lo, hi);
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    tcg_temp_free_i32(lo);
    tcg_temp_free_i32(hi);
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    return ret;
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}

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/* Swap low and high halfwords.  */
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static void gen_swap_half(TCGv_i32 var)
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{
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    TCGv_i32 tmp = tcg_temp_new_i32();
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    tcg_gen_shri_i32(tmp, var, 16);
    tcg_gen_shli_i32(var, var, 16);
    tcg_gen_or_i32(var, var, tmp);
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    tcg_temp_free_i32(tmp);
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}

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/* Dual 16-bit add.  Result placed in t0 and t1 is marked as dead.
    tmp = (t0 ^ t1) & 0x8000;
    t0 &= ~0x8000;
    t1 &= ~0x8000;
    t0 = (t0 + t1) ^ tmp;
 */

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static void gen_add16(TCGv_i32 t0, TCGv_i32 t1)
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{
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    TCGv_i32 tmp = tcg_temp_new_i32();
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    tcg_gen_xor_i32(tmp, t0, t1);
    tcg_gen_andi_i32(tmp, tmp, 0x8000);
    tcg_gen_andi_i32(t0, t0, ~0x8000);
    tcg_gen_andi_i32(t1, t1, ~0x8000);
    tcg_gen_add_i32(t0, t0, t1);
    tcg_gen_xor_i32(t0, t0, tmp);
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    tcg_temp_free_i32(tmp);
    tcg_temp_free_i32(t1);
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}

/* Set CF to the top bit of var.  */
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static void gen_set_CF_bit31(TCGv_i32 var)
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{
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    tcg_gen_shri_i32(cpu_CF, var, 31);
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}

/* Set N and Z flags from var.  */
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static inline void gen_logic_CC(TCGv_i32 var)
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{
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    tcg_gen_mov_i32(cpu_NF, var);
    tcg_gen_mov_i32(cpu_ZF, var);
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}

/* T0 += T1 + CF.  */
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static void gen_adc(TCGv_i32 t0, TCGv_i32 t1)
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{
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    tcg_gen_add_i32(t0, t0, t1);
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    tcg_gen_add_i32(t0, t0, cpu_CF);
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}

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/* dest = T0 + T1 + CF. */
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static void gen_add_carry(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
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{
    tcg_gen_add_i32(dest, t0, t1);
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    tcg_gen_add_i32(dest, dest, cpu_CF);
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}

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/* dest = T0 - T1 + CF - 1.  */
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static void gen_sub_carry(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
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{
    tcg_gen_sub_i32(dest, t0, t1);
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    tcg_gen_add_i32(dest, dest, cpu_CF);
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    tcg_gen_subi_i32(dest, dest, 1);
}

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/* dest = T0 + T1. Compute C, N, V and Z flags */
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static void gen_add_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
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{
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    TCGv_i32 tmp = tcg_temp_new_i32();
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    tcg_gen_movi_i32(tmp, 0);
    tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, t1, tmp);
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    tcg_gen_mov_i32(cpu_ZF, cpu_NF);
    tcg_gen_xor_i32(cpu_VF, cpu_NF, t0);
    tcg_gen_xor_i32(tmp, t0, t1);
    tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
    tcg_temp_free_i32(tmp);
    tcg_gen_mov_i32(dest, cpu_NF);
}

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/* dest = T0 + T1 + CF.  Compute C, N, V and Z flags */
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static void gen_adc_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
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{
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    TCGv_i32 tmp = tcg_temp_new_i32();
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    if (TCG_TARGET_HAS_add2_i32) {
        tcg_gen_movi_i32(tmp, 0);
        tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, cpu_CF, tmp);
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        tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1, tmp);
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    } else {
        TCGv_i64 q0 = tcg_temp_new_i64();
        TCGv_i64 q1 = tcg_temp_new_i64();
        tcg_gen_extu_i32_i64(q0, t0);
        tcg_gen_extu_i32_i64(q1, t1);
        tcg_gen_add_i64(q0, q0, q1);
        tcg_gen_extu_i32_i64(q1, cpu_CF);
        tcg_gen_add_i64(q0, q0, q1);
        tcg_gen_extr_i64_i32(cpu_NF, cpu_CF, q0);
        tcg_temp_free_i64(q0);
        tcg_temp_free_i64(q1);
    }
    tcg_gen_mov_i32(cpu_ZF, cpu_NF);
    tcg_gen_xor_i32(cpu_VF, cpu_NF, t0);
    tcg_gen_xor_i32(tmp, t0, t1);
    tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
    tcg_temp_free_i32(tmp);
    tcg_gen_mov_i32(dest, cpu_NF);
}

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/* dest = T0 - T1. Compute C, N, V and Z flags */
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static void gen_sub_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
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{
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    tcg_gen_sub_i32(cpu_NF, t0, t1);
    tcg_gen_mov_i32(cpu_ZF, cpu_NF);
    tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0, t1);
    tcg_gen_xor_i32(cpu_VF, cpu_NF, t0);
    tmp = tcg_temp_new_i32();
    tcg_gen_xor_i32(tmp, t0, t1);
    tcg_gen_and_i32(cpu_VF, cpu_VF, tmp);
    tcg_temp_free_i32(tmp);
    tcg_gen_mov_i32(dest, cpu_NF);
}

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/* dest = T0 + ~T1 + CF.  Compute C, N, V and Z flags */
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static void gen_sbc_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
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{
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    TCGv_i32 tmp = tcg_temp_new_i32();
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    tcg_gen_not_i32(tmp, t1);
    gen_adc_CC(dest, t0, tmp);
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    tcg_temp_free_i32(tmp);
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}

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#define GEN_SHIFT(name)                                               \
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static void gen_##name(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)       \
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{                                                                     \
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    TCGv_i32 tmp1, tmp2, tmp3;                                        \
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    tmp1 = tcg_temp_new_i32();                                        \
    tcg_gen_andi_i32(tmp1, t1, 0xff);                                 \
    tmp2 = tcg_const_i32(0);                                          \
    tmp3 = tcg_const_i32(0x1f);                                       \
    tcg_gen_movcond_i32(TCG_COND_GTU, tmp2, tmp1, tmp3, tmp2, t0);    \
    tcg_temp_free_i32(tmp3);                                          \
    tcg_gen_andi_i32(tmp1, tmp1, 0x1f);                               \
    tcg_gen_##name##_i32(dest, tmp2, tmp1);                           \
    tcg_temp_free_i32(tmp2);                                          \
    tcg_temp_free_i32(tmp1);                                          \
}
GEN_SHIFT(shl)
GEN_SHIFT(shr)
#undef GEN_SHIFT

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static void gen_sar(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
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{
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    tmp1 = tcg_temp_new_i32();
    tcg_gen_andi_i32(tmp1, t1, 0xff);
    tmp2 = tcg_const_i32(0x1f);
    tcg_gen_movcond_i32(TCG_COND_GTU, tmp1, tmp1, tmp2, tmp2, tmp1);
    tcg_temp_free_i32(tmp2);
    tcg_gen_sar_i32(dest, t0, tmp1);
    tcg_temp_free_i32(tmp1);
}

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static void tcg_gen_abs_i32(TCGv_i32 dest, TCGv_i32 src)
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{
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    TCGv_i32 c0 = tcg_const_i32(0);
    TCGv_i32 tmp = tcg_temp_new_i32();
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    tcg_gen_neg_i32(tmp, src);
    tcg_gen_movcond_i32(TCG_COND_GT, dest, src, c0, src, tmp);
    tcg_temp_free_i32(c0);
    tcg_temp_free_i32(tmp);
}
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static void shifter_out_im(TCGv_i32 var, int shift)
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{
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    if (shift == 0) {
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        tcg_gen_andi_i32(cpu_CF, var, 1);
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    } else {
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        tcg_gen_shri_i32(cpu_CF, var, shift);
        if (shift != 31) {
            tcg_gen_andi_i32(cpu_CF, cpu_CF, 1);
        }
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    }
}
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/* Shift by immediate.  Includes special handling for shift == 0.  */
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static inline void gen_arm_shift_im(TCGv_i32 var, int shiftop,
                                    int shift, int flags)
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{
    switch (shiftop) {
    case 0: /* LSL */
        if (shift != 0) {
            if (flags)
                shifter_out_im(var, 32 - shift);
            tcg_gen_shli_i32(var, var, shift);
        }
        break;
    case 1: /* LSR */
        if (shift == 0) {
            if (flags) {
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                tcg_gen_shri_i32(cpu_CF, var, 31);
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            }
            tcg_gen_movi_i32(var, 0);
        } else {
            if (flags)
                shifter_out_im(var, shift - 1);
            tcg_gen_shri_i32(var, var, shift);
        }
        break;
    case 2: /* ASR */
        if (shift == 0)
            shift = 32;
        if (flags)
            shifter_out_im(var, shift - 1);
        if (shift == 32)
          shift = 31;
        tcg_gen_sari_i32(var, var, shift);
        break;
    case 3: /* ROR/RRX */
        if (shift != 0) {
            if (flags)
                shifter_out_im(var, shift - 1);
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            tcg_gen_rotri_i32(var, var, shift); break;
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        } else {
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            TCGv_i32 tmp = tcg_temp_new_i32();
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            tcg_gen_shli_i32(tmp, cpu_CF, 31);
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            if (flags)
                shifter_out_im(var, 0);
            tcg_gen_shri_i32(var, var, 1);
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            tcg_gen_or_i32(var, var, tmp);
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            tcg_temp_free_i32(tmp);
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        }
    }
};

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static inline void gen_arm_shift_reg(TCGv_i32 var, int shiftop,
                                     TCGv_i32 shift, int flags)
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{
    if (flags) {
        switch (shiftop) {
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        case 0: gen_helper_shl_cc(var, cpu_env, var, shift); break;
        case 1: gen_helper_shr_cc(var, cpu_env, var, shift); break;
        case 2: gen_helper_sar_cc(var, cpu_env, var, shift); break;
        case 3: gen_helper_ror_cc(var, cpu_env, var, shift); break;
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        }
    } else {
        switch (shiftop) {
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        case 0:
            gen_shl(var, var, shift);
            break;
        case 1:
            gen_shr(var, var, shift);
            break;
        case 2:
            gen_sar(var, var, shift);
            break;
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        case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
                tcg_gen_rotr_i32(var, var, shift); break;
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        }
    }
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    tcg_temp_free_i32(shift);
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}

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#define PAS_OP(pfx) \
    switch (op2) {  \
    case 0: gen_pas_helper(glue(pfx,add16)); break; \
    case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
    case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
    case 3: gen_pas_helper(glue(pfx,sub16)); break; \
    case 4: gen_pas_helper(glue(pfx,add8)); break; \
    case 7: gen_pas_helper(glue(pfx,sub8)); break; \
    }
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static void gen_arm_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b)
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{
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    TCGv_ptr tmp;
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    switch (op1) {
#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
    case 1:
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        tmp = tcg_temp_new_ptr();
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        tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
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        PAS_OP(s)
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        tcg_temp_free_ptr(tmp);
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        break;
    case 5:
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        tmp = tcg_temp_new_ptr();
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        tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
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        PAS_OP(u)
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        tcg_temp_free_ptr(tmp);
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        break;
#undef gen_pas_helper
#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
    case 2:
        PAS_OP(q);
        break;
    case 3:
        PAS_OP(sh);
        break;
    case 6:
        PAS_OP(uq);
        break;
    case 7:
        PAS_OP(uh);
        break;
#undef gen_pas_helper
    }
}
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#undef PAS_OP

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/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings.  */
#define PAS_OP(pfx) \
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    switch (op1) {  \
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    case 0: gen_pas_helper(glue(pfx,add8)); break; \
    case 1: gen_pas_helper(glue(pfx,add16)); break; \
    case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
    case 4: gen_pas_helper(glue(pfx,sub8)); break; \
    case 5: gen_pas_helper(glue(pfx,sub16)); break; \
    case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
    }
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static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b)
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{
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    TCGv_ptr tmp;
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    switch (op2) {
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#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
    case 0:
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        tmp = tcg_temp_new_ptr();
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        tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
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        PAS_OP(s)
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        tcg_temp_free_ptr(tmp);
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        break;
    case 4:
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        tmp = tcg_temp_new_ptr();
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        tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
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        PAS_OP(u)
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        tcg_temp_free_ptr(tmp);
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        break;
#undef gen_pas_helper
#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
    case 1:
        PAS_OP(q);
        break;
    case 2:
        PAS_OP(sh);
        break;
    case 5:
        PAS_OP(uq);
        break;
    case 6:
        PAS_OP(uh);
        break;
#undef gen_pas_helper
    }
}
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#undef PAS_OP

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static void gen_test_cc(int cc, int label)
{
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    TCGv_i32 tmp;
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    int inv;

    switch (cc) {
    case 0: /* eq: Z */
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        tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ZF, 0, label);
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        break;
    case 1: /* ne: !Z */
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        tcg_gen_brcondi_i32(TCG_COND_NE, cpu_ZF, 0, label);
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        break;
    case 2: /* cs: C */
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        tcg_gen_brcondi_i32(TCG_COND_NE, cpu_CF, 0, label);
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        break;
    case 3: /* cc: !C */
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        tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_CF, 0, label);
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        break;
    case 4: /* mi: N */
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        tcg_gen_brcondi_i32(TCG_COND_LT, cpu_NF, 0, label);
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        break;
    case 5: /* pl: !N */
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        tcg_gen_brcondi_i32(TCG_COND_GE, cpu_NF, 0, label);
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        break;
    case 6: /* vs: V */
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        tcg_gen_brcondi_i32(TCG_COND_LT, cpu_VF, 0, label);
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        break;
    case 7: /* vc: !V */
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        tcg_gen_brcondi_i32(TCG_COND_GE, cpu_VF, 0, label);
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        break;
    case 8: /* hi: C && !Z */
        inv = gen_new_label();
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        tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_CF, 0, inv);
        tcg_gen_brcondi_i32(TCG_COND_NE, cpu_ZF, 0, label);
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        gen_set_label(inv);
        break;
    case 9: /* ls: !C || Z */
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        tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_CF, 0, label);
        tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ZF, 0, label);
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        break;
    case 10: /* ge: N == V -> N ^ V == 0 */
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        tmp = tcg_temp_new_i32();
        tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
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        tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
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        tcg_temp_free_i32(tmp);
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        break;
    case 11: /* lt: N != V -> N ^ V != 0 */
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        tmp = tcg_temp_new_i32();
        tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
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        tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
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        tcg_temp_free_i32(tmp);
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        break;
    case 12: /* gt: !Z && N == V */
        inv = gen_new_label();
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        tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ZF, 0, inv);
        tmp = tcg_temp_new_i32();
        tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
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        tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
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        tcg_temp_free_i32(tmp);
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        gen_set_label(inv);
        break;
    case 13: /* le: Z || N != V */
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        tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ZF, 0, label);
        tmp = tcg_temp_new_i32();
        tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
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        tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
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        tcg_temp_free_i32(tmp);
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        break;
    default:
        fprintf(stderr, "Bad condition code 0x%x\n", cc);
        abort();
    }
}
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static const uint8_t table_logic_cc[16] = {
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    1, /* and */
    1, /* xor */
    0, /* sub */
    0, /* rsb */
    0, /* add */
    0, /* adc */
    0, /* sbc */
    0, /* rsc */
    1, /* andl */
    1, /* xorl */
    0, /* cmp */
    0, /* cmn */
    1, /* orr */
    1, /* mov */
    1, /* bic */
    1, /* mvn */
};
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/* Set PC and Thumb state from an immediate address.  */
static inline void gen_bx_im(DisasContext *s, uint32_t addr)
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{
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    TCGv_i32 tmp;
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    s->is_jmp = DISAS_UPDATE;
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    if (s->thumb != (addr & 1)) {
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        tmp = tcg_temp_new_i32();
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        tcg_gen_movi_i32(tmp, addr & 1);
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        tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, thumb));
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        tcg_temp_free_i32(tmp);
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    }
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    tcg_gen_movi_i32(cpu_R[15], addr & ~1);
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}

/* Set PC and Thumb state from var.  var is marked as dead.  */
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static inline void gen_bx(DisasContext *s, TCGv_i32 var)
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{
    s->is_jmp = DISAS_UPDATE;
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    tcg_gen_andi_i32(cpu_R[15], var, ~1);
    tcg_gen_andi_i32(var, var, 1);
    store_cpu_field(var, thumb);
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}

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/* Variant of store_reg which uses branch&exchange logic when storing
   to r15 in ARM architecture v7 and above. The source must be a temporary
   and will be marked as dead. */
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static inline void store_reg_bx(CPUARMState *env, DisasContext *s,
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                                int reg, TCGv_i32 var)
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{
    if (reg == 15 && ENABLE_ARCH_7) {
        gen_bx(s, var);
    } else {
        store_reg(s, reg, var);
    }
}

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/* Variant of store_reg which uses branch&exchange logic when storing
 * to r15 in ARM architecture v5T and above. This is used for storing
 * the results of a LDR/LDM/POP into r15, and corresponds to the cases
 * in the ARM ARM which use the LoadWritePC() pseudocode function. */
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static inline void store_reg_from_load(CPUARMState *env, DisasContext *s,
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                                       int reg, TCGv_i32 var)
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{
    if (reg == 15 && ENABLE_ARCH_5) {
        gen_bx(s, var);
    } else {
        store_reg(s, reg, var);
    }
}

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/* Abstractions of "generate code to do a guest load/store for
 * AArch32", where a vaddr is always 32 bits (and is zero
 * extended if we're a 64 bit core) and  data is also
 * 32 bits unless specifically doing a 64 bit access.
 * These functions work like tcg_gen_qemu_{ld,st}* except
 * that their arguments are TCGv_i32 rather than TCGv.
 */
#if TARGET_LONG_BITS == 32

#define DO_GEN_LD(OP)                                                    \
static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \
{                                                                        \
    tcg_gen_qemu_##OP(val, addr, index);                                 \
}

#define DO_GEN_ST(OP)                                                    \
static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \
{                                                                        \
    tcg_gen_qemu_##OP(val, addr, index);                                 \
}

static inline void gen_aa32_ld64(TCGv_i64 val, TCGv_i32 addr, int index)
{
    tcg_gen_qemu_ld64(val, addr, index);
}

static inline void gen_aa32_st64(TCGv_i64 val, TCGv_i32 addr, int index)
{
    tcg_gen_qemu_st64(val, addr, index);
}

#else

#define DO_GEN_LD(OP)                                                    \
static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \
{                                                                        \
    TCGv addr64 = tcg_temp_new();                                        \
    TCGv val64 = tcg_temp_new();                                         \
    tcg_gen_extu_i32_i64(addr64, addr);                                  \
    tcg_gen_qemu_##OP(val64, addr64, index);                             \
    tcg_temp_free(addr64);                                               \
    tcg_gen_trunc_i64_i32(val, val64);                                   \
    tcg_temp_free(val64);                                                \
}

#define DO_GEN_ST(OP)                                                    \
static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \
{                                                                        \
    TCGv addr64 = tcg_temp_new();                                        \
    TCGv val64 = tcg_temp_new();                                         \
    tcg_gen_extu_i32_i64(addr64, addr);                                  \
    tcg_gen_extu_i32_i64(val64, val);                                    \
    tcg_gen_qemu_##OP(val64, addr64, index);                             \
    tcg_temp_free(addr64);                                               \
    tcg_temp_free(val64);                                                \
}

static inline void gen_aa32_ld64(TCGv_i64 val, TCGv_i32 addr, int index)
{
    TCGv addr64 = tcg_temp_new();
    tcg_gen_extu_i32_i64(addr64, addr);
    tcg_gen_qemu_ld64(val, addr64, index);
    tcg_temp_free(addr64);
}

static inline void gen_aa32_st64(TCGv_i64 val, TCGv_i32 addr, int index)
{
    TCGv addr64 = tcg_temp_new();
    tcg_gen_extu_i32_i64(addr64, addr);
    tcg_gen_qemu_st64(val, addr64, index);
    tcg_temp_free(addr64);
}

#endif

DO_GEN_LD(ld8s)
DO_GEN_LD(ld8u)
DO_GEN_LD(ld16s)
DO_GEN_LD(ld16u)
DO_GEN_LD(ld32u)
DO_GEN_ST(st8)
DO_GEN_ST(st16)
DO_GEN_ST(st32)

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static inline void gen_set_pc_im(target_ulong val)
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{
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    tcg_gen_movi_i32(cpu_R[15], val);
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}

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/* Force a TB lookup after an instruction that changes the CPU state.  */
static inline void gen_lookup_tb(DisasContext *s)
{
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    tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
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    s->is_jmp = DISAS_UPDATE;
}

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static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
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                                       TCGv_i32 var)
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{
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    int val, rm, shift, shiftop;
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    TCGv_i32 offset;
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    if (!(insn & (1 << 25))) {
        /* immediate */
        val = insn & 0xfff;
        if (!(insn & (1 << 23)))
            val = -val;
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        if (val != 0)
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            tcg_gen_addi_i32(var, var, val);
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    } else {
        /* shift/register */
        rm = (insn) & 0xf;
        shift = (insn >> 7) & 0x1f;
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        shiftop = (insn >> 5) & 3;
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        offset = load_reg(s, rm);
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        gen_arm_shift_im(offset, shiftop, shift, 0);
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        if (!(insn & (1 << 23)))
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            tcg_gen_sub_i32(var, var, offset);
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        else
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            tcg_gen_add_i32(var, var, offset);
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        tcg_temp_free_i32(offset);
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    }
}

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static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
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                                        int extra, TCGv_i32 var)
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{
    int val, rm;
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    TCGv_i32 offset;
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    if (insn & (1 << 22)) {
        /* immediate */
        val = (insn & 0xf) | ((insn >> 4) & 0xf0);
        if (!(insn & (1 << 23)))
            val = -val;
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        val += extra;
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        if (val != 0)
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            tcg_gen_addi_i32(var, var, val);
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    } else {
        /* register */
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        if (extra)
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            tcg_gen_addi_i32(var, var, extra);
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        rm = (insn) & 0xf;
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        offset = load_reg(s, rm);
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        if (!(insn & (1 << 23)))
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            tcg_gen_sub_i32(var, var, offset);
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        else
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            tcg_gen_add_i32(var, var, offset);
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        tcg_temp_free_i32(offset);
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    }
}

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static TCGv_ptr get_fpstatus_ptr(int neon)
{
    TCGv_ptr statusptr = tcg_temp_new_ptr();
    int offset;
    if (neon) {
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        offset = offsetof(CPUARMState, vfp.standard_fp_status);
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    } else {
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        offset = offsetof(CPUARMState, vfp.fp_status);
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    }
    tcg_gen_addi_ptr(statusptr, cpu_env, offset);
    return statusptr;
}

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#define VFP_OP2(name)                                                 \
static inline void gen_vfp_##name(int dp)                             \
{                                                                     \
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    TCGv_ptr fpst = get_fpstatus_ptr(0);                              \
    if (dp) {                                                         \
        gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, fpst);    \
    } else {                                                          \
        gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, fpst);    \
    }                                                                 \
    tcg_temp_free_ptr(fpst);                                          \
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}

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VFP_OP2(add)
VFP_OP2(sub)
VFP_OP2(mul)
VFP_OP2(div)

#undef VFP_OP2

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static inline void gen_vfp_F1_mul(int dp)
{
    /* Like gen_vfp_mul() but put result in F1 */
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    TCGv_ptr fpst = get_fpstatus_ptr(0);
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    if (dp) {
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        gen_helper_vfp_muld(cpu_F1d, cpu_F0d, cpu_F1d, fpst);
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    } else {
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        gen_helper_vfp_muls(cpu_F1s, cpu_F0s, cpu_F1s, fpst);
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    }
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    tcg_temp_free_ptr(fpst);
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}

static inline void gen_vfp_F1_neg(int dp)
{
    /* Like gen_vfp_neg() but put result in F1 */
    if (dp) {
        gen_helper_vfp_negd(cpu_F1d, cpu_F0d);
    } else {
        gen_helper_vfp_negs(cpu_F1s, cpu_F0s);
    }
}

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static inline void gen_vfp_abs(int dp)
{
    if (dp)
        gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
    else
        gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
}

static inline void gen_vfp_neg(int dp)
{
    if (dp)
        gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
    else
        gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
}

static inline void gen_vfp_sqrt(int dp)
{
    if (dp)
        gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
    else
        gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
}

static inline void gen_vfp_cmp(int dp)
{
    if (dp)
        gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
    else
        gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
}

static inline void gen_vfp_cmpe(int dp)
{
    if (dp)
        gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
    else
        gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
}

static inline void gen_vfp_F1_ld0(int dp)
{
    if (dp)
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        tcg_gen_movi_i64(cpu_F1d, 0);
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    else
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        tcg_gen_movi_i32(cpu_F1s, 0);
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}

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#define VFP_GEN_ITOF(name) \
static inline void gen_vfp_##name(int dp, int neon) \
{ \
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    TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
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    if (dp) { \
        gen_helper_vfp_##name##d(cpu_F0d, cpu_F0s, statusptr); \
    } else { \
        gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, statusptr); \
    } \
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    tcg_temp_free_ptr(statusptr); \
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}

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VFP_GEN_ITOF(uito)
VFP_GEN_ITOF(sito)
#undef VFP_GEN_ITOF
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#define VFP_GEN_FTOI(name) \
static inline void gen_vfp_##name(int dp, int neon) \
{ \
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    TCGv_ptr statusptr = get_fpstatus_ptr(neon); \