1. 24 Aug, 2015 2 commits
  2. 07 Aug, 2015 1 commit
  3. 27 Jul, 2015 2 commits
    • Boris Brezillon's avatar
      clk: fix some determine_rate implementations · 57d866e6
      Boris Brezillon authored
      Some determine_rate implementations are not returning an error
      when they failed to adapt the rate according to the rate request.
      Fix them so that they return an error instead of silently
      returning 0.
      Signed-off-by: 's avatarBoris Brezillon <boris.brezillon@free-electrons.com>
      CC: Jonathan Corbet <corbet@lwn.net>
      CC: Tony Lindgren <tony@atomide.com>
      CC: Ralf Baechle <ralf@linux-mips.org>
      CC: "Emilio López" <emilio@elopez.com.ar>
      CC: Maxime Ripard <maxime.ripard@free-electrons.com>
      Cc: Tero Kristo <t-kristo@ti.com>
      CC: Peter De Schrijver <pdeschrijver@nvidia.com>
      CC: Prashant Gaikwad <pgaikwad@nvidia.com>
      CC: Stephen Warren <swarren@wwwdotorg.org>
      CC: Thierry Reding <thierry.reding@gmail.com>
      CC: Alexandre Courbot <gnurou@gmail.com>
      CC: linux-doc@vger.kernel.org
      CC: linux-kernel@vger.kernel.org
      CC: linux-arm-kernel@lists.infradead.org
      CC: linux-omap@vger.kernel.org
      CC: linux-mips@linux-mips.org
      CC: linux-tegra@vger.kernel.org
      Signed-off-by: 's avatarStephen Boyd <sboyd@codeaurora.org>
      57d866e6
    • Boris Brezillon's avatar
      clk: change clk_ops' ->determine_rate() prototype · 0817b62c
      Boris Brezillon authored
      Clock rates are stored in an unsigned long field, but ->determine_rate()
      (which returns a rounded rate from a requested one) returns a long
      value (errors are reported using negative error codes), which can lead
      to long overflow if the clock rate exceed 2Ghz.
      
      Change ->determine_rate() prototype to return 0 or an error code, and pass
      a pointer to a clk_rate_request structure containing the expected target
      rate and the rate constraints imposed by clk users.
      
      The clk_rate_request structure might be extended in the future to contain
      other kind of constraints like the rounding policy, the maximum clock
      inaccuracy or other things that are not yet supported by the CCF
      (power consumption constraints ?).
      Signed-off-by: 's avatarBoris Brezillon <boris.brezillon@free-electrons.com>
      CC: Jonathan Corbet <corbet@lwn.net>
      CC: Tony Lindgren <tony@atomide.com>
      CC: Ralf Baechle <ralf@linux-mips.org>
      CC: "Emilio López" <emilio@elopez.com.ar>
      CC: Maxime Ripard <maxime.ripard@free-electrons.com>
      Acked-by: 's avatarTero Kristo <t-kristo@ti.com>
      CC: Peter De Schrijver <pdeschrijver@nvidia.com>
      CC: Prashant Gaikwad <pgaikwad@nvidia.com>
      CC: Stephen Warren <swarren@wwwdotorg.org>
      CC: Thierry Reding <thierry.reding@gmail.com>
      CC: Alexandre Courbot <gnurou@gmail.com>
      CC: linux-doc@vger.kernel.org
      CC: linux-kernel@vger.kernel.org
      CC: linux-arm-kernel@lists.infradead.org
      CC: linux-omap@vger.kernel.org
      CC: linux-mips@linux-mips.org
      CC: linux-tegra@vger.kernel.org
      [sboyd@codeaurora.org: Fix parent dereference problem in
      __clk_determine_rate()]
      Signed-off-by: 's avatarStephen Boyd <sboyd@codeaurora.org>
      Tested-by: 's avatarRomain Perier <romain.perier@gmail.com>
      Signed-off-by: 's avatarHeiko Stuebner <heiko@sntech.de>
      [sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate
      clocks without parents or a rate determining op]
      Signed-off-by: 's avatarStephen Boyd <sboyd@codeaurora.org>
      0817b62c
  4. 02 Feb, 2015 1 commit
  5. 03 Dec, 2014 1 commit
  6. 12 Nov, 2014 1 commit
    • Chao Xie's avatar
      clk: mmp: add clock type mix · ee81f4ee
      Chao Xie authored
      The clock type mix is a kind of clock combines "div" and "mux".
      This kind of clock can not allow to change div first then
      mux or change mux first or div.
      The reason is
      1. Some clock has frequency change bit. Each time want to change
         the frequency, there are some operations based on this bit, and
         these operations are time-cost.
         Seperating div and mux change will make the process longer, and
         waste more time.
      2. Seperting the div and mux may generate middle clock that the
         peripharals do not support. It may make the peripharals hang.
      
      There are three kinds of this type of clock in all SOCes.
      1. The clock has bit to trigger the frequency change.
      2. Same as #1, but the operations for the bit is different
      3. Do not have frequency change bit.
      
      So this type of clock has implemented the callbacks
      ->determine_rate
      ->set_rate_and_parent
      These callbacks can help to change the div and mux together.
      Signed-off-by: 's avatarChao Xie <chao.xie@marvell.com>
      Acked-by: 's avatarHaojian Zhuang <haojian.zhuang@gmail.com>
      Signed-off-by: 's avatarMichael Turquette <mturquette@linaro.org>
      ee81f4ee