1. 22 Oct, 2016 2 commits
  2. 29 Aug, 2016 1 commit
  3. 24 Aug, 2016 2 commits
  4. 12 Aug, 2016 2 commits
    • Xing Zheng's avatar
      clk: rockchip: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src on rk3399 · 4608d96f
      Xing Zheng authored
      Sorry to refer incorrect clock diagram, we double check it that the bits
      configuration of the Xpll_aclk_perihp_src need to be fixed:
      bit 1 - shows aclk_perihp_cpll_src_en
      bit 0 - shows aclk_perihp_gpll_src_en
      
      Through the testing that plug/unplug the USB ethernet cable on the RK3399 kevin board.
      
      1. the hclk_host0 and hclk_host1 are endpoint clocks:
      cpll --> G5[1] --> aclk_perihp_cpll_src --\              |--> hclk_host0
                                                | --> ... ---> |
      gpll --> G5[0] --> aclk_perihp_gpll_src --/              |--> hclk_host1
      
      2. there is no clock below the cpll_aclk_perihp_src,
         and the hclk_hostX are below the gpll_aclk_perihp_src:
          pll_cpll                              1            1   800000000          0 0
             cpll                               7           19   800000000          0 0
                cpll_aclk_perihp_src            0            0   800000000          0 0
      ...
          pll_gpll                              1            1   594000000          0 0
             gpll                              10           10   594000000          0 0
                gpll_aclk_perihp_src            2            2   594000000          0 0
                      hclk_perihp               5            5    74250000          0 0
                         hclk_host1_arb         2            2    74250000          0 0
                         hclk_host1             2            2    74250000          0 0
                         hclk_host0_arb         2            2    74250000          0 0
                         hclk_host0             2            2    74250000          0 0
      
      3. by default, G5[0] and G5[1] are enabled:
      localhost ~ # mem r 0xff760314
      0x000003e0
      
      4. close the G5[1] (aclk_perihp_cpll_src), and plug/unplug USB ethernet cable,
         the DUT still works well:
      localhost ~ # mem w 0xff760314 0xffff03e2
      localhost ~ # mem r 0xff760314
      0x000003e2
      plug/unplug, the work statue is ok
      
      5. close the G5[0] (aclk_perihp_gpll_src), , and plug/unplug USB ethernet cable,
         the DUT will be crashed:
      localhost ~ # mem w 0xff760314 0xffff03e1
      localhost ~ # mem r 0xff760314
      0x000003e1
      plug/unplug, the DUT is crashed
      
      Summary:
      bit 1 - shows aclk_perihp_cpll_src_en
      bit 0 - shows aclk_perihp_gpll_src_en
      
      Fixes: 3bd14ae9 ("clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src")
      Signed-off-by: 's avatarXing Zheng <zhengxing@rock-chips.com>
      
      [here the clock-documentation in the manual was actually stating the wrong
      bits and thus only Xing's testing above revealed the issue]
      Signed-off-by: 's avatarHeiko Stuebner <heiko@sntech.de>
      4608d96f
    • Xing Zheng's avatar
      clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399 · 20c389e6
      Xing Zheng authored
      Dues to incorrect diagram, we need to fix incorrect bits for
      (c/g)pll_aclk_emmc_src:
      cpll_aclk_emmc_src --> G6[13]
      gpll_aclk_emmc_src --> G6[12]
      
      Fixes: 11551005 ("clk: rockchip: add clock controller for the RK3399")
      Signed-off-by: 's avatarXing Zheng <zhengxing@rock-chips.com>
      Reviewed-by: 's avatarShawn Lin <shawn.lin@rock-chips.com>
      Signed-off-by: 's avatarHeiko Stuebner <heiko@sntech.de>
      20c389e6
  5. 11 Aug, 2016 2 commits
  6. 10 Aug, 2016 1 commit
  7. 08 Aug, 2016 4 commits
  8. 02 Aug, 2016 1 commit
  9. 19 Jul, 2016 1 commit
  10. 18 Jul, 2016 1 commit
  11. 15 Jul, 2016 1 commit
  12. 13 Jul, 2016 3 commits
  13. 12 Jul, 2016 3 commits
    • Jean Delvare's avatar
      clk: oxnas: Add hardware dependencies · 821f9946
      Jean Delvare authored
      The clk-oxnas driver is specific to its architecture, so do not
      propose it on other architectures, unless build-testing.
      Signed-off-by: 's avatarJean Delvare <jdelvare@suse.de>
      Cc: Stephen Boyd <sboyd@codeaurora.org>
      Acked-by: 's avatarNeil Armstrong <narmstrong@baylibre.com>
      Signed-off-by: 's avatarMichael Turquette <mturquette@baylibre.com>
      Link: lkml.kernel.org/r/20160707091844.196a7930@endymion
      821f9946
    • Stefan Agner's avatar
      clk: imx7d: do not set parent of ethernet time/ref clocks · 5e33ebff
      Stefan Agner authored
      All device trees currently in mainline specify the time clock parent
      using the assigned-clocks/assigned-clock-parents method, there is no
      need to statically assign the parent in the core clock driver.
      Also all current boards provide an Ethernet reference clock for the
      PHY externally, hence configuring the internal PHY reference clock.
      
      Furthermore, and the actual driver of this patch, specify ethernet
      related parents at that early point in boot leads to a warning:
      bad: scheduling from the idle thread!
      
      The reason for the warning is that setting the parent enables the ENET
      PLL since we are using CLK_OPS_PARENT_ENABLE. Enabling the ENET PLL can
      cause clk_pllv3_wait_lock to sleep. See also:
      commit fc8726a2 ("clk: core: support clocks which requires parents
      enable (part 2)").
      
      Note that setting the ENET AXI root clock parent also requires ENET
      PLL to be enabled. However, U-Boot typically leaves the ENET PLL on,
      hence when the framework sets the parent of the first clock, it does
      not need to wait for the PLL to come up. But because there is currently
      no user of that clock, the PLL gets disabled after setting the parent.
      Therefore, subsequent reparenting calls of any clock which somehow rely
      on the ENET PLL, need to reenable the ENET PLL which leads to a sleep.
      Removing those subsequent reparenting calls works around this issue.
      
      Also remove comments. The code is really verbose enough.
      Signed-off-by: 's avatarStefan Agner <stefan@agner.ch>
      Tested-by: 's avatarFabio Estevam <festevam@gmail.com>
      Signed-off-by: 's avatarMichael Turquette <mturquette@baylibre.com>
      Link: lkml.kernel.org/r/20160703174813.13970-1-stefan@agner.ch
      5e33ebff
    • Arnd Bergmann's avatar
      ARM: ux500: use CLK_OF_DECLARE() · 269f1aac
      Arnd Bergmann authored
      The ux500 DT support predates the CLK_OF_DECLARE macro and calls
      directly into the clk driver from platform code.
      
      Converting this to CLK_OF_DECLARE makes the code much nicer and
      similar to how modern platforms do it today. It also removes the
      last user of cpu_is_u8500_family() etc.
      Signed-off-by: 's avatarArnd Bergmann <arnd@arndb.de>
      Signed-off-by: 's avatarLinus Walleij <linus.walleij@linaro.org>
      269f1aac
  14. 11 Jul, 2016 2 commits
  15. 08 Jul, 2016 14 commits