1. 06 Jul, 2015 1 commit
  2. 23 Mar, 2015 1 commit
    • Georgi Djakov's avatar
      clk: qcom: Introduce parent_map tables · 293d2e97
      Georgi Djakov authored
      In the current parent mapping code, we can get duplicate or inconsistent
      indexes, which leads to discrepancy between the number of elements in the
      array and the number of parents. Until now, this was solved with some
      reordering but this is not always possible.
      
      This patch introduces index tables that are used to define the relations
      between the PLL source and the hardware mux configuration value.
      To accomplish this, here we do the following:
       - Define a parent_map struct to map the relations between PLL source index
       and register configuration value.
       - Add a qcom_find_src_index() function for finding the index of a clock
       matching the specific PLL configuration.
       - Update the {set,get}_parent RCG functions use the newly introduced
       parent_map struct.
       - Convert all existing drivers to the new parent_map tables.
      Signed-off-by: default avatarGeorgi Djakov <georgi.djakov@linaro.org>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      293d2e97
  3. 25 Sep, 2014 1 commit
  4. 15 Jul, 2014 1 commit
    • Stephen Boyd's avatar
      clk: qcom: Fix PLL rate configurations · 5b6b7490
      Stephen Boyd authored
      Sometimes we need to program PLLs with a fixed rate
      configuration during driver probe. Doing this after we register
      the PLLs with the clock framework causes the common clock
      framework to assume the rate of the PLLs are 0. This causes all
      sorts of problems for rate recalculations because the common
      clock framework caches the rate once at registration time unless
      a flag is set to always recalculate the rates.
      
      Split the qcom_cc_probe() function into two pieces, map and
      everything else, so that drivers which need to configure some
      PLL rates or otherwise twiddle bits in the clock controller can
      do so before registering clocks. This allows us to properly
      detect the rates of PLLs that are programmed at boot.
      
      Fixes: 49fc825f "clk: qcom: Consolidate common probe code"
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      5b6b7490
  5. 29 May, 2014 2 commits
  6. 30 Apr, 2014 1 commit
  7. 16 Jan, 2014 1 commit