1. 12 Mar, 2010 3 commits
  2. 28 Feb, 2010 1 commit
  3. 20 Feb, 2010 2 commits
    • Russell King's avatar
      MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself · 4b3073e1
      Russell King authored
      On VIVT ARM, when we have multiple shared mappings of the same file
      in the same MM, we need to ensure that we have coherency across all
      copies.  We do this via make_coherent() by making the pages
      uncacheable.
      
      This used to work fine, until we allowed highmem with highpte - we
      now have a page table which is mapped as required, and is not available
      for modification via update_mmu_cache().
      
      Ralf Beache suggested getting rid of the PTE value passed to
      update_mmu_cache():
      
        On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables
        to construct a pointer to the pte again.  Passing a pte_t * is much
        more elegant.  Maybe we might even replace the pte argument with the
        pte_t?
      
      Ben Herrenschmidt would also like the pte pointer for PowerPC:
      
        Passing the ptep in there is exactly what I want.  I want that
        -instead- of the PTE value, because I have issue on some ppc cases,
        for I$/D$ coherency, where set_pte_at() may decide to mask out the
        _PAGE_EXEC.
      
      So, pass in the mapped page table pointer into update_mmu_cache(), and
      remove the PTE value, updating all implementations and call sites to
      suit.
      
      Includes a fix from Stephen Rothwell:
      
        sparc: fix fallout from update_mmu_cache API change
      Signed-off-by: default avatarStephen Rothwell <sfr@canb.auug.org.au>
      Acked-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      4b3073e1
    • Abdoulaye Walsimou Gaye's avatar
      ARM: 5950/1: ARM: Fix build error for arm1026ej-s processor · 1c8e170a
      Abdoulaye Walsimou Gaye authored
      This patch fix the below build error for arm1026ej-s processor (IntegratorCP/arm1026ej-s board).
        CC      init/main.o
      In file included from include/linux/highmem.h:8,
                       from include/linux/pagemap.h:10,
                       from include/linux/mempolicy.h:62,
                       from init/main.c:52:
      arch/arm/include/asm/cacheflush.h:134:2: error: #error Unknown cache maintainence model
      make[1]: *** [init/main.o] Erreur 1
      make: *** [init] Erreur 2
      Signed-off-by: default avatarAbdoulaye Walsimou Gaye <walsimou@walsimou.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      1c8e170a
  4. 15 Feb, 2010 14 commits
  5. 12 Feb, 2010 3 commits
  6. 05 Feb, 2010 1 commit
  7. 19 Jan, 2010 1 commit
  8. 10 Jan, 2010 1 commit
  9. 09 Jan, 2010 1 commit
  10. 08 Jan, 2010 1 commit
  11. 07 Jan, 2010 1 commit
  12. 18 Dec, 2009 2 commits
  13. 16 Dec, 2009 1 commit
  14. 14 Dec, 2009 8 commits