1. 22 May, 2012 1 commit
    • Paul Mundt's avatar
      sh: intc: Kill off special reservation interface. · 5f19f14f
      Paul Mundt authored
      At present reserving the IRLs in the IRQ bitmap in addition to the
      dropping of the legacy IRQ pre-allocation prevent IRL IRQs from being
      allocated for the x3proto board.
      
      The only reason to permit reservations was to lock down possible hardware
      vectors prior to dynamic IRQ scanning, but this doesn't matter much given
      that the hardware controller configuration is sorted before we get around
      to doing any dynamic IRQ allocation anyways. Beyond that, all of the
      tables are __init annotated, so quite a bit more work would need to be
      done to support reconfiguring things like IRL controllers on the fly,
      much more than would ever make it worth the hassle.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      5f19f14f
  2. 25 Jan, 2012 2 commits
  3. 25 Dec, 2011 1 commit
    • Rafael J. Wysocki's avatar
      PM / shmobile: Don't include SH7372's INTCS in syscore suspend/resume · 0f966d74
      Rafael J. Wysocki authored
      Since the SH7372's INTCS in included into syscore suspend/resume,
      which causes the chip to be accessed when PM domains have been
      turned off during system suspend, the A4R domain containing the
      INTCS has to stay on during system sleep, which is suboptimal
      from the power consumption point of view.
      
      For this reason, add a new INTC flag, skip_syscore_suspend, to mark
      the INTCS for intc_suspend() and intc_resume(), so that they don't
      touch it.  This allows the A4R domain to be turned off during
      system suspend and the INTCS state is resrored during system
      resume by the A4R's "power on" code.
      Suggested-by: default avatarMagnus Damm <damm@opensource.se>
      Signed-off-by: default avatarRafael J. Wysocki <rjw@sisk.pl>
      Acked-by: default avatarMagnus Damm <damm@opensource.se>
      0f966d74
  4. 09 Nov, 2010 1 commit
  5. 26 Oct, 2010 1 commit
  6. 05 Oct, 2010 2 commits
    • Paul Mundt's avatar
      sh: intc: Split up the INTC code. · 2be6bb0c
      Paul Mundt authored
      This splits up the sh intc core in to something more vaguely resembling
      a subsystem. Most of the functionality was alread fairly well
      compartmentalized, and there were only a handful of interdependencies
      that needed to be resolved in the process.
      
      This also serves as future-proofing for the genirq and sparseirq rework,
      which will make some of the split out functionality wholly generic,
      allowing things to be killed off in place with minimal migration pain.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      2be6bb0c
    • Paul Mundt's avatar
      sh: intc: Handle early lookups of subgroup IRQs. · d74310d3
      Paul Mundt authored
      If lookups happen while the radix node still points to a subgroup
      mapping, an IRQ hasn't yet been made available for the specified id, so
      error out accordingly. Once the slot is replaced with an IRQ mapping and
      the tag is discarded, lookup can commence as normal.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      d74310d3
  7. 04 Oct, 2010 2 commits
    • Paul Mundt's avatar
      sh: intc: Support virtual mappings for IRQ subgroups. · c1e30ad9
      Paul Mundt authored
      Many interrupts that share a single mask source but are on different
      hardware vectors will have an associated register tied to an INTEVT that
      denotes the precise cause for the interrupt exception being triggered.
      
      This introduces the concept of IRQ subgroups in the intc core, where
      a virtual IRQ map is constructed for each of the pre-defined cause bits,
      and a higher level chained handler takes control of the parent INTEVT.
      This enables CPUs with heavily muxed IRQ vectors (especially across
      disjoint blocks) to break things out in to a series of managed chained
      handlers while being able to dynamically lookup and adopt the IRQs
      created for them.
      
      This is largely an opt-in interface, requiring CPUs to manually submit
      IRQs for subgroup splitting, in addition to providing identifiers in
      their enum maps that can be used for lazy lookup via the radix tree.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      c1e30ad9
    • Paul Mundt's avatar
      sh: intc: Implement reverse mapping for IRQs to per-controller IDs. · 44629f57
      Paul Mundt authored
      This implements a scheme roughly analogous to the PowerPC virtual to
      hardware IRQ mapping, which we use for IRQ to per-controller ID mapping.
      This makes it possible for drivers to use the IDs directly for lookup
      instead of hardcoding the vector.
      
      The main motivation for this work is as a building block for dynamically
      allocating virtual IRQs for demuxing INTC events sharing a single INTEVT
      in addition to a common masking source.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      44629f57
  8. 02 Oct, 2010 1 commit
  9. 14 Apr, 2010 1 commit
    • Paul Mundt's avatar
      sh: intc: IRQ auto-distribution support. · dc825b17
      Paul Mundt authored
      This implements support for hardware-managed IRQ balancing as implemented
      by SH-X3 cores (presently only hooked up for SH7786, but can probably be
      carried over to other SH-X3 cores, too).
      
      CPUs need to specify their distribution register along with the mask
      definitions, as these follow the same format. Peripheral IRQs that don't
      opt out of balancing will be automatically distributed at the whim of the
      hardware block, while each CPU needs to verify whether it is handling the
      IRQ or not, especially before clearing the mask.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      dc825b17
  10. 12 Apr, 2010 1 commit
    • Paul Mundt's avatar
      sh: intc: userimask support. · 43b8774d
      Paul Mundt authored
      This adds support for hardware-assisted userspace irq masking for
      special priority levels. Due to the SR.IMASK interactivity, only some
      platforms implement this in hardware (including but not limited to
      SH-4A interrupt controllers, and ARM-based SH-Mobile CPUs). Each CPU
      needs to wire this up on its own, for now only SH7786 is wired up as an
      example.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      43b8774d
  11. 19 Mar, 2010 2 commits
  12. 15 Feb, 2010 1 commit
  13. 09 Feb, 2010 2 commits
  14. 01 Nov, 2009 1 commit
    • Paul Mundt's avatar
      sh: intc: Handle legacy IRQ reservation in vector map. · 45b9deaf
      Paul Mundt authored
      Different CPUs will have different starting vectors, with varying
      amounts of reserved or unusable vector space prior to the first slot.
      This introduces a legacy vector reservation system that inserts itself in
      between the CPU vector map registration and the platform specific IRQ
      setup. This works fine in practice as the only new vectors that boards
      need to establish on their own should be dynamically allocated rather
      than arbitrarily assigned. As a plus, this also makes all of the
      converted platforms sparseirq ready.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      45b9deaf
  15. 26 Oct, 2009 1 commit
    • Paul Mundt's avatar
      sh: intc: Make ack_regs generally available. · 9b798d50
      Paul Mundt authored
      Currently this is ifdef'ed under SH-3 and SH-4A, but there are other CPUs
      that will need this as well. Given the size of the existing data
      structures, this doesn't cause any additional cacheline utilization for
      the existing users, so has no direct impact on the data structures.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      9b798d50
  16. 24 Aug, 2009 1 commit
  17. 27 Feb, 2009 1 commit
    • Magnus Damm's avatar
      sh: multiple vectors per irq - base · bdaa6e80
      Magnus Damm authored
      Instead of keeping the single vector -> single linux irq mapping
      we extend the intc code to support merging of vectors to a single
      linux irq. This helps processors such as sh7750, sh7780 and sh7785
      which have more vectors than masking ability. With this patch in
      place we can modify the intc tables to use one irq per maskable
      irq source. Please note the following:
      
       - If multiple vectors share the same enum then only the
         first vector will be available as a linux irq.
      
       - Drivers may need to be rewritten to get pending irq
         source from the hardware block instead of irq number.
      
      This patch together with the sh7785 specific intc tables solves
      DMA controller irq issues related to buggy interrupt masking.
      Reported-by: default avatarYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
      Signed-off-by: default avatarMagnus Damm <damm@igel.co.jp>
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      bdaa6e80
  18. 01 Oct, 2008 1 commit
  19. 28 Jul, 2008 2 commits
  20. 08 May, 2008 2 commits
  21. 27 Jan, 2008 1 commit
  22. 21 Sep, 2007 1 commit
  23. 20 Sep, 2007 9 commits
  24. 20 Jul, 2007 1 commit
  25. 19 Jul, 2007 1 commit
    • Magnus Damm's avatar
      sh: intc - add support for 7780 · 39c7aa9e
      Magnus Damm authored
      This patch converts the cpu specific 7780 setup code to use the
      new intc controller. Many new vectors are added and also support for
      external interrupt sense configuration. So with this patch it is now
      possible to configure external interrupt pins as edge or level
      triggered using set_irq_type().
      
      No external interrupts are registered by default.
      Use plat_irq_setup_pins() to select between IRQ or IRL mode.
      
      This patch also fixes the Alarm IRQ for the RTC.
      Signed-off-by: default avatarMagnus Damm <damm@igel.co.jp>
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      39c7aa9e