1. 25 Feb, 2016 1 commit
  2. 21 Dec, 2015 1 commit
  3. 16 Dec, 2015 1 commit
    • Linus Walleij's avatar
      irqchip/gic: Support RealView variant setup · 8673c1d7
      Linus Walleij authored
      The ARM RealView PB11MPCore reference design has some special
      bits in a system controller register to set up the GIC in one
      of three modes: legacy, new with DCC, new without DCC. The
      register is also used to enable FIQ.
      
      Since the platform will not boot unless this register is set
      up to "new with DCC" mode, we need a special quirk to be
      compiled-in for the RealView platforms.
      
      If we find the right compatible string on the GIC TestChip,
      we enable this quirk by looking up the system controller and
      enabling the special bits.
      
      We depend on the CONFIG_REALVIEW_DT Kconfig symbol as the old
      boardfile code has the same fix hardcoded, and this is only
      needed for the attempts to modernize the RealView code using
      device tree.
      
      After fixing this, the PB11MPCore boots with device tree
      only.
      
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      8673c1d7
  4. 10 Dec, 2015 1 commit
  5. 11 Nov, 2015 1 commit
    • Alex Smith's avatar
      irqchip: irq-mips-gic: Provide function to map GIC user section · c0a9f72c
      Alex Smith authored
      The GIC provides a "user-mode visible" section containing a mirror of
      the counter registers which can be mapped into user memory. This will
      be used by the VDSO time function implementations, so provide a
      function to map it in.
      
      When the GIC is not enabled in Kconfig a dummy inline version of this
      function is provided, along with "#define gic_present 0", so that we
      don't have to litter the VDSO code with ifdefs.
      
      [markos.chandras@imgtec.com:
        - Move mapping code to arch/mips/kernel/vdso.c and use a resource
          type to get the GIC usermode information
        - Avoid renaming function arguments and use __gic_base_addr to hold
          the base GIC address prior to ioremap.]
      [ralf@linux-mips.org: Fix up gic_get_usm_range() to compile and make inline
      again.]
      Signed-off-by: default avatarAlex Smith <alex.smith@imgtec.com>
      Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
      Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Alex Smith <alex.smith@imgtec.com>
      Cc: Markos Chandras <markos.chandras@imgtec.com>
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-mips@linux-mips.org
      Patchwork: http://patchwork.linux-mips.org/patch/11281/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      c0a9f72c
  6. 13 Oct, 2015 1 commit
  7. 09 Oct, 2015 3 commits
  8. 30 Sep, 2015 1 commit
  9. 29 Sep, 2015 1 commit
  10. 27 Aug, 2015 2 commits
    • Marc Zyngier's avatar
      irqchip/GIC: Convert to EOImode == 1 · 0b996fd3
      Marc Zyngier authored
      So far, GICv2 has been used with EOImode == 0. The effect of this
      mode is to perform the priority drop and the deactivation of the
      interrupt at the same time.
      
      While this works perfectly for Linux (we only have a single priority),
      it causes issues when an interrupt is forwarded to a guest, and when
      we want the guest to perform the EOI itself.
      
      For this case, the GIC architecture provides EOImode == 1, where:
      - A write to the EOI register drops the priority of the interrupt
        and leaves it active. Other interrupts at the same priority level
        can now be taken, but the active interrupt cannot be taken again
      - A write to the DIR marks the interrupt as inactive, meaning it can
        now be taken again.
      
      We only enable this feature when booted in HYP mode and that
      the device-tree reported a suitable CPU interface. Observable behaviour
      should remain unchanged.
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Reviewed-and-tested-by: default avatarEric Auger <eric.auger@linaro.org>
      Cc: Christoffer Dall <christoffer.dall@linaro.org>
      Cc: Jiang Liu <jiang.liu@linux.intel.com>
      Cc: <linux-arm-kernel@lists.infradead.org>
      Cc: kvmarm@lists.cs.columbia.edu
      Cc: Jason Cooper <jason@lakedaemon.net>
      Link: http://lkml.kernel.org/r/1440604845-28229-4-git-send-email-marc.zyngier@arm.comSigned-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      0b996fd3
    • Marc Zyngier's avatar
      irqchip/GICv3: Convert to EOImode == 1 · 0b6a3da9
      Marc Zyngier authored
      So far, GICv3 has been used in with EOImode == 0. The effect of this
      mode is to perform the priority drop and the deactivation of the
      interrupt at the same time.
      
      While this works perfectly for Linux (we only have a single priority),
      it causes issues when an interrupt is forwarded to a guest, and when
      we want the guest to perform the EOI itself.
      
      For this case, the GIC architecture provides EOImode == 1, where:
      - A write to ICC_EOIR1_EL1 drops the priority of the interrupt and
        leaves it active. Other interrupts at the same priority level can
        now be taken, but the active interrupt cannot be taken again
      - A write to ICC_DIR_EL1 marks the interrupt as inactive, meaning
        it can now be taken again.
      
      This patch converts the driver to be able to use this new mode,
      depending on whether or not the kernel can behave as a hypervisor.
      No feature change.
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Reviewed-and-tested-by: default avatarEric Auger <eric.auger@linaro.org>
      Cc: Christoffer Dall <christoffer.dall@linaro.org>
      Cc: Jiang Liu <jiang.liu@linux.intel.com>
      Cc: <linux-arm-kernel@lists.infradead.org>
      Cc: kvmarm@lists.cs.columbia.edu
      Cc: Jason Cooper <jason@lakedaemon.net>
      Link: http://lkml.kernel.org/r/1440604845-28229-2-git-send-email-marc.zyngier@arm.comSigned-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      0b6a3da9
  11. 26 Aug, 2015 2 commits
  12. 12 Aug, 2015 1 commit
  13. 04 Aug, 2015 1 commit
    • Jon Hunter's avatar
      irqchip/gic: Ensure gic_cpu_if_up/down() programs correct GIC instance · 4c2880b3
      Jon Hunter authored
      Commit 32289506 ("irqchip: gic: Preserve gic V2 bypass bits in cpu
      ctrl register") added a new function, gic_cpu_if_up(), to program the
      GIC CPU_CTRL register. This function assumes that there is only one GIC
      instance present and hence always uses the chip data for the primary GIC
      controller. Although it is not common for there to be a secondary, some
      devices do support a secondary. Therefore, fix this by passing
      gic_cpu_if_up() a pointer to the appropriate chip data structure.
      
      Similarly, the function gic_cpu_if_down() only assumes that there is a
      single GIC instance present. Update this function so that an instance
      number is passed for the appropriate GIC and return an error code on
      failure. The vexpress TC2 (which has a single GIC) is currently the only
      user of this function and so update it accordingly. Note that because the
      TC2 only has a single GIC, the call to gic_cpu_if_down() should always
      be successful.
      Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
      Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Cc: <linux-arm-kernel@lists.infradead.org>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Link: http://lkml.kernel.org/r/1438332252-25248-2-git-send-email-jonathanh@nvidia.comSigned-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      4c2880b3
  14. 29 Jul, 2015 2 commits
  15. 27 Jul, 2015 1 commit
  16. 21 Jun, 2015 1 commit
  17. 28 May, 2015 1 commit
  18. 24 Apr, 2015 1 commit
  19. 31 Mar, 2015 3 commits
  20. 29 Mar, 2015 3 commits
  21. 26 Mar, 2015 1 commit
  22. 14 Mar, 2015 3 commits
  23. 07 Mar, 2015 2 commits
  24. 05 Feb, 2015 1 commit
    • James Hogan's avatar
      MIPS: cevt-r4k: Drop GIC special case · ae58d882
      James Hogan authored
      The cevt-r4k driver used to call into the GIC driver to find whether the
      timer was pending, but only with External Interrupt Controller (EIC)
      mode, where the Cause.IP bits can't be used as they encode the interrupt
      priority level (Cause.RIPL) instead.
      
      However commit e9de688d ("irqchip: mips-gic: Support local
      interrupts") changed the condition from cpu_has_veic to gic_present.
      This fails on cores such as P5600 which have a GIC but the local
      interrupts aren't routable by the GIC, causing c0_compare_int_usable()
      to consider the interrupt unusable so r4k_clockevent_init() fails.
      
      The previous behaviour, added in commit 98b67c37 ("MIPS: Add EIC
      support for GIC."), wasn't really correct either as far as I can tell,
      since P5600 apparently supports EIC mode too, and in any case the use of
      Cause.TI with r2 should have been sufficient anyway since commit
      010c108d ("MIPS: PowerTV: Fix support for timer interrupts with > 64
      external IRQs").
      
      Therefore drop the call into the gic driver altogether, and add a
      comment in c0_compare_int_pending() to clarify that Cause.TI does get
      checked since MIPS r2.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Fixes: e9de688d ("irqchip: mips-gic: Support local interrupts")
      Reviewed-by: default avatarAndrew Bresticker <abrestic@chromium.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Steven J. Hill <steven.hill@imgtec.com>
      Cc: Qais Yousef <qais.yousef@imgtec.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/9077/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      ae58d882
  25. 26 Jan, 2015 2 commits
  26. 20 Jan, 2015 2 commits