1. 02 Mar, 2016 22 commits
  2. 01 Mar, 2016 4 commits
  3. 29 Feb, 2016 1 commit
    • Archit Taneja's avatar
      clk: qcom: Fix pre-divider usage for pixel RCG · 811a498e
      Archit Taneja authored
      The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading
      its current value from the NS register.
      
      Using the pre-divider wasn't really intended when creating these ops.
      The pixel RCG was only intended to achieve fractional multiplication
      provided in the pixel_table array. Leaving the pre-divider to the
      existing register value results in a wrong pixel clock when the
      bootloader sets up the display. This was left unidentified because
      the IFC6410 Plus board on which this was verified didn't have a
      bootloader that configured the display.
      
      Don't set the RCG pre-divider in freq_tbl to the existing NS register
      value. Force it to 1 and only use the M/N counter to achieve the desired
      fractional multiplication.
      
      Cc: Vinay Simha <vinaysimha@inforcecomputing.com>
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Tested-by: default avatarJohn Stultz <john.stultz@linaro.org>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      811a498e
  4. 27 Feb, 2016 2 commits
  5. 26 Feb, 2016 11 commits