1. 28 Apr, 2016 1 commit
  2. 20 Apr, 2016 2 commits
  3. 15 Apr, 2016 1 commit
  4. 07 Apr, 2016 2 commits
  5. 15 Mar, 2016 1 commit
  6. 22 Feb, 2016 1 commit
  7. 17 Feb, 2016 1 commit
  8. 09 Dec, 2015 1 commit
  9. 01 Dec, 2015 1 commit
    • Arnd Bergmann's avatar
      clk: mmp: stop using platform headers · 990f2f22
      Arnd Bergmann authored
      The mmp clock drivers currently hardcode the physical addresses for
      the clock registers. This is generally a bad idea, and it also gets in
      the way of multiplatform builds, which make the platform header files
      inaccessible to device drivers.
      
      To work around the header file problem, this patch changes the calling
      convention so the three mmp clock drivers get initialized with the base
      addresses as arguments from the platform code.
      
      It would still be useful to have a larger rework of the clock drivers,
      with DT integration to let the clocks actually be probed automatically,
      and the base addresses passed as DT properties. I am unsure if anyone
      is still interested in the mmp platform, so it is possible that this
      won't happen.
      Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      Cc: Mike Turquette <mturquette@linaro.org>
      Cc: Chao Xie <chao.xie@marvell.com>
      Cc: Eric Miao <eric.y.miao@gmail.com>
      Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
      990f2f22
  10. 30 Nov, 2015 1 commit
    • Tero Kristo's avatar
      clk: ti: omap5+: dpll: implement errata i810 · 07ff73a9
      Tero Kristo authored
      Errata i810 states that DPLL controller can get stuck while transitioning
      to a power saving state, while its M/N ratio is being re-programmed.
      
      As a workaround, before re-programming the M/N ratio, SW has to ensure
      the DPLL cannot start an idle state transition. SW can disable DPLL
      idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request
      active by setting a dependent clock domain in SW_WKUP.
      
      This errata impacts OMAP5 and DRA7 chips, so enable the errata for these.
      Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      07ff73a9
  11. 01 Oct, 2015 3 commits
  12. 25 Aug, 2015 1 commit
  13. 11 Aug, 2015 1 commit
  14. 27 Jul, 2015 1 commit
    • Boris Brezillon's avatar
      clk: change clk_ops' ->determine_rate() prototype · 0817b62c
      Boris Brezillon authored
      Clock rates are stored in an unsigned long field, but ->determine_rate()
      (which returns a rounded rate from a requested one) returns a long
      value (errors are reported using negative error codes), which can lead
      to long overflow if the clock rate exceed 2Ghz.
      
      Change ->determine_rate() prototype to return 0 or an error code, and pass
      a pointer to a clk_rate_request structure containing the expected target
      rate and the rate constraints imposed by clk users.
      
      The clk_rate_request structure might be extended in the future to contain
      other kind of constraints like the rounding policy, the maximum clock
      inaccuracy or other things that are not yet supported by the CCF
      (power consumption constraints ?).
      Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
      CC: Jonathan Corbet <corbet@lwn.net>
      CC: Tony Lindgren <tony@atomide.com>
      CC: Ralf Baechle <ralf@linux-mips.org>
      CC: "Emilio López" <emilio@elopez.com.ar>
      CC: Maxime Ripard <maxime.ripard@free-electrons.com>
      Acked-by: default avatarTero Kristo <t-kristo@ti.com>
      CC: Peter De Schrijver <pdeschrijver@nvidia.com>
      CC: Prashant Gaikwad <pgaikwad@nvidia.com>
      CC: Stephen Warren <swarren@wwwdotorg.org>
      CC: Thierry Reding <thierry.reding@gmail.com>
      CC: Alexandre Courbot <gnurou@gmail.com>
      CC: linux-doc@vger.kernel.org
      CC: linux-kernel@vger.kernel.org
      CC: linux-arm-kernel@lists.infradead.org
      CC: linux-omap@vger.kernel.org
      CC: linux-mips@linux-mips.org
      CC: linux-tegra@vger.kernel.org
      [sboyd@codeaurora.org: Fix parent dereference problem in
      __clk_determine_rate()]
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      Tested-by: default avatarRomain Perier <romain.perier@gmail.com>
      Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      [sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate
      clocks without parents or a rate determining op]
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      0817b62c
  15. 20 Jul, 2015 1 commit
    • Stephen Boyd's avatar
      clk: tegra: Properly include clk.h · 584ac4e9
      Stephen Boyd authored
      Clock provider drivers generally shouldn't include clk.h because
      it's the consumer API. Only include clk.h in files that are using
      it. Also add in a clkdev.h include that was missing in a file
      using clkdev APIs.
      
      Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
      Cc: Thierry Reding <treding@nvidia.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      584ac4e9
  16. 16 Jul, 2015 1 commit
  17. 02 Jun, 2015 18 commits
  18. 11 Apr, 2015 1 commit
    • Ben Dooks's avatar
      clk: at91: change to using endian agnositc IO · f6194213
      Ben Dooks authored
      Change to using endian agnostic _relaxed IO accessors instead of __raw
      Signed-off-by: default avatarBen Dooks <ben.dooks@codethink.co.uk>
      --
      CC: Andrew Victor <linux@maxim.org.za>
      CC: Nicolas Ferre <nicolas.ferre@atmel.com>
      CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
      CC: Mike Turquette <mturquette@linaro.org> (maintainer:COMMON CLK FRAMEWORK)
      CC: Stephen Boyd <sboyd@codeaurora.org> (maintainer:COMMON CLK FRAMEWORK)
      CC: linux-kernel@vger.kernel.org (open list:COMMON CLK FRAMEWORK)
      Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
      f6194213
  19. 27 Mar, 2015 1 commit