1. 20 Jul, 2015 1 commit
    • Stephen Boyd's avatar
      clk: tegra: Properly include clk.h · 584ac4e9
      Stephen Boyd authored
      Clock provider drivers generally shouldn't include clk.h because
      it's the consumer API. Only include clk.h in files that are using
      it. Also add in a clkdev.h include that was missing in a file
      using clkdev APIs.
      Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
      Cc: Thierry Reding <treding@nvidia.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
  2. 11 Apr, 2015 1 commit
    • Ben Dooks's avatar
      clk: at91: change to using endian agnositc IO · f6194213
      Ben Dooks authored
      Change to using endian agnostic _relaxed IO accessors instead of __raw
      Signed-off-by: default avatarBen Dooks <ben.dooks@codethink.co.uk>
      CC: Andrew Victor <linux@maxim.org.za>
      CC: Nicolas Ferre <nicolas.ferre@atmel.com>
      CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
      CC: Mike Turquette <mturquette@linaro.org> (maintainer:COMMON CLK FRAMEWORK)
      CC: Stephen Boyd <sboyd@codeaurora.org> (maintainer:COMMON CLK FRAMEWORK)
      CC: linux-kernel@vger.kernel.org (open list:COMMON CLK FRAMEWORK)
      Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
  3. 27 Mar, 2015 1 commit
  4. 25 Mar, 2015 1 commit
  5. 26 Feb, 2015 1 commit
  6. 03 Feb, 2015 1 commit
    • Arnd Bergmann's avatar
      clk: omap: compile legacy omap3 clocks conditionally · 6793a30a
      Arnd Bergmann authored
      The 'ARM: OMAP3: legacy clock data move under clk driver' patch series
      causes build errors when CONFIG_OMAP3 is not set:
      drivers/clk/ti/dpll.c: In function 'ti_clk_register_dpll':
      drivers/clk/ti/dpll.c:199:31: error: 'omap3_dpll_ck_ops' undeclared (first use in this function)
        const struct clk_ops *ops = &omap3_dpll_ck_ops;
      drivers/clk/ti/dpll.c:199:31: note: each undeclared identifier is reported only once for each function it appears in
      drivers/clk/ti/dpll.c:259:10: error: 'omap3_dpll_per_ck_ops' undeclared (first use in this function)
         ops = &omap3_dpll_per_ck_ops;
      drivers/built-in.o: In function `ti_clk_register_gate':
      drivers/clk/ti/gate.c:179: undefined reference to `clkhwops_omap3430es2_dss_usbhost_wait'
      drivers/clk/ti/gate.c:179: undefined reference to `clkhwops_am35xx_ipss_module_wait'
      -in.o: In function `ti_clk_register_interface':
      drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_omap3430es2_iclk_hsotgusb_wait'
      drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_omap3430es2_iclk_dss_usbhost_wait'
      drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_omap3430es2_iclk_ssi_wait'
      drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_am35xx_ipss_wait'
      drivers/built-in.o: In function `ti_clk_register_composite':
      :(.text+0x3da768): undefined reference to `ti_clk_build_component_gate'
      In order to fix that problem, this patch makes the omap3 legacy code
      compiled only when both CONFIG_OMAP3 and CONFIG_ATAGS are set.
      Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      Acked-by: default avatarTony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
  7. 02 Feb, 2015 2 commits
    • Tomeu Vizoso's avatar
      clk: Add rate constraints to clocks · 1c8e6004
      Tomeu Vizoso authored
      Adds a way for clock consumers to set maximum and minimum rates. This
      can be used for thermal drivers to set minimum rates, or by misc.
      drivers to set maximum rates to assure a minimum performance level.
      Changes the signature of the determine_rate callback by adding the
      parameters min_rate and max_rate.
      Signed-off-by: default avatarTomeu Vizoso <tomeu.vizoso@collabora.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      [sboyd@codeaurora.org: set req_rate in __clk_init]
      Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
      [mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate
                              migrated clk-private.h changes to clk.c]
    • Peter De Schrijver's avatar
      clk: tegra: make tegra_clocks_apply_init_table() arch_initcall · d0a57bd5
      Peter De Schrijver authored
      tegra_clocks_apply_init_table() needs to be called after the udelay
      loop has been calibrated (see commit
      441f199a ("clk: tegra: defer
      application of init table") for why that is).  On existing Tegra SoCs
      this was done by calling tegra_clocks_apply_init_table() from
      tegra_dt_init(). To make this also work on ARM64, we need to change
      this into an initcall. tegra_dt_init() is called from
      customize_machine which is an arch_initcall. Therefore this should
      also work on existing 32bit Tegra SoCs.
      Tested on Tegra20 (ventana), Tegra30 (beaverboard), Tegra124 (jetson TK1) and
      Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
      [paul@pwsan.com: tweaked the commit message]
      Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
      Signed-off-by: default avatarPaul Walmsley <pwalmsley@nvidia.com>
      Cc: Thierry Reding <treding@nvidia.com>
      Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
      Cc: Mike Turquette <mturquette@linaro.org>
      Cc: Stephen Boyd <sboyd@codeaurora.org>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      Cc: Thierry Reding <thierry.reding@gmail.com>
      Cc: Alexandre Courbot <gnurou@gmail.com>
  8. 30 Jan, 2015 1 commit
    • Tero Kristo's avatar
      clk: ti: add omap3 legacy clock data · 74807dff
      Tero Kristo authored
      Introduces omap3 legacy clock data under clock driver. The clock data
      is also in new format, which makes it possible to get rid of the
      clk-private.h header. This patch also introduces SoC specific init
      functions that shall be called from the low level init.
      The data format used in this file has two possible evolution paths;
      it can either be removed completely once no longer needed, or it will
      be possible to retain the format and modify the TI clock driver to be
      a loadable module at some point. The actual path to be followed
      will be decided later.
      Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
      Acked-by: default avatarTony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
  9. 27 Jan, 2015 1 commit
  10. 14 Jan, 2015 1 commit
  11. 15 Dec, 2014 1 commit
  12. 13 Nov, 2014 3 commits
  13. 29 Sep, 2014 1 commit
    • Tero Kristo's avatar
      clk: ti: change clock init to use generic of_clk_init · c08ee14c
      Tero Kristo authored
      Previously, the TI clock driver initialized all the clocks hierarchically
      under each separate clock provider node. Now, each clock that requires
      IO access will instead check their parent node to find out which IO range
      to use.
      This patch allows the TI clock driver to use a few new features provided
      by the generic of_clk_init, and also allows registration of clock nodes
      outside the clock hierarchy (for example, any external clocks.)
      Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
      Cc: Mike Turquette <mturquette@linaro.org>
      Cc: Paul Walmsley <paul@pwsan.com>
      Cc: Tony Lindgren <tony@atomide.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
      Cc: Jyri Sarha <jsarha@ti.com>
      Cc: Stefan Assmann <sassmann@kpanic.de>
      Acked-by: default avatarTony Lindgren <tony@atomide.com>
  14. 22 Sep, 2014 1 commit
  15. 25 Jul, 2014 1 commit
  16. 06 Jun, 2014 1 commit
    • Andrii Tseglytskyi's avatar
      ARM: OMAP5+: dpll: support Duty Cycle Correction(DCC) · ce369a54
      Andrii Tseglytskyi authored
      Duty Cycle Correction(DCC) needs to be enabled if the MPU is to run at
      frequencies beyond 1.4GHz for OMAP5, DRA75x, DRA72x.
      MPU DPLL has a limitation on the maximum frequency it can be locked
      at. Duty Cycle Correction circuit is used to recover a correct duty
      cycle for achieving higher frequencies (hardware internally switches
      output to M3 output(CLKOUTHIF) from M2 output (CLKOUT)).
      For further information, See the note on OMAP5432 Technical Reference
      Manual(SWPU282U) chapter "DPLLs Output Clocks Parameters",
      and also the "OMAP543x ES2.0 DM Operating Conditions Addendum v0.5"
      chapter 2.1 "Micro Processor Unit (MPU)". Equivalent information is
      present in relevant DRA75x, 72x documentation(SPRUHP2E, SPRUHI2P).
      Signed-off-by: default avatarAndrii Tseglytskyi <andrii.tseglytskyi@ti.com>
      Signed-off-by: default avatarTaras Kondratiuk <taras@ti.com>
      Signed-off-by: default avatarJ Keerthy <j-keerthy@ti.com>
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      [t-kristo@ti.com: added TRM / DM references for DCC clock rate]
      Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
  17. 28 May, 2014 5 commits
  18. 14 May, 2014 1 commit
  19. 13 May, 2014 1 commit
  20. 07 May, 2014 1 commit
  21. 05 May, 2014 1 commit
  22. 19 Feb, 2014 1 commit
  23. 10 Feb, 2014 1 commit
  24. 17 Jan, 2014 10 commits