1. 22 Jun, 2016 1 commit
  2. 10 Jun, 2016 1 commit
  3. 19 Apr, 2016 1 commit
  4. 15 Apr, 2016 4 commits
  5. 11 Apr, 2016 1 commit
  6. 02 Mar, 2016 1 commit
  7. 01 Mar, 2016 3 commits
  8. 26 Feb, 2016 1 commit
  9. 22 Feb, 2016 2 commits
  10. 29 Jan, 2016 1 commit
  11. 03 Dec, 2015 1 commit
  12. 30 Nov, 2015 1 commit
    • Tero Kristo's avatar
      clk: ti: omap5+: dpll: implement errata i810 · 07ff73a9
      Tero Kristo authored
      Errata i810 states that DPLL controller can get stuck while transitioning
      to a power saving state, while its M/N ratio is being re-programmed.
      
      As a workaround, before re-programming the M/N ratio, SW has to ensure
      the DPLL cannot start an idle state transition. SW can disable DPLL
      idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request
      active by setting a dependent clock domain in SW_WKUP.
      
      This errata impacts OMAP5 and DRA7 chips, so enable the errata for these.
      Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      07ff73a9
  13. 24 Nov, 2015 4 commits
  14. 20 Nov, 2015 1 commit
  15. 16 Nov, 2015 2 commits
  16. 02 Oct, 2015 3 commits
    • Suman Anna's avatar
      clk: ti: dflt: fix enable_reg validity check · 7aba4f52
      Suman Anna authored
      The default clock enabling functions for TI clocks -
      omap2_dflt_clk_enable() and omap2_dflt_clk_disable() perform a
      NULL check for the enable_reg field of the clk_hw_omap structure.
      This enable_reg field however is merely a combination of the index
      of the master IP module, and the offset from the master IP module's
      base address. A value of 0 is perfectly valid, and the current error
      checking will fail in these cases. The issue was found when trying
      to enable the iva2_ck clock on OMAP3 platforms.
      
      So, switch the check to use IS_ERR. This correction is similar to the
      logic used in commit c807dbed ("clk: ti: fix ti_clk_get_reg_addr
      error handling").
      
      Fixes: 9f37e90e ("clk: ti: dflt: move support for default gate clock..")
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
      7aba4f52
    • Ben Dooks's avatar
      clk: ti: fix dual-registration of uart4_ick · 19e79687
      Ben Dooks authored
      On the OMAP AM3517 platform the uart4_ick gets registered
      twice, causing any power management to /dev/ttyO3 to fail
      when trying to wake the device up.
      
      This solves the following oops:
      
      [] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfa09e008
      [] PC is at serial_omap_pm+0x48/0x15c
      [] LR is at _raw_spin_unlock_irqrestore+0x30/0x5c
      
      Fixes: aafd900c ("CLK: TI: add omap3 clock init file")
      Cc: stable@vger.kernel.org
      Cc: mturquette@baylibre.com
      Cc: sboyd@codeaurora.org
      Cc: linux-clk@vger.kernel.org
      Cc: linux-omap@vger.kernel.org
      Cc: linux-kernel@lists.codethink.co.uk
      Signed-off-by: default avatarBen Dooks <ben.dooks@codethink.co.uk>
      Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
      19e79687
    • Peter Ujfalusi's avatar
      clk: ti: clk-7xx: Remove hardwired ABE clock configuration · 4b3061b3
      Peter Ujfalusi authored
      The ABE related clocks should be configured via DT and not have it wired
      inside of the kernel.
      
      Fixes: a74c52de ("clk: ti: clk-7xx: Correct ABE DPLL configuration")
      Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
      Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
      4b3061b3
  17. 24 Aug, 2015 5 commits
  18. 13 Aug, 2015 1 commit
  19. 31 Jul, 2015 1 commit
  20. 28 Jul, 2015 5 commits