1. 04 Mar, 2016 2 commits
    • Joachim Eastwood's avatar
      clk: add lpc18xx creg clk driver · 378523d1
      Joachim Eastwood authored
      The CREG block on lpc18xx contains configuration register
      for two low power clocks. Support enabling of these two
      clocks with a clk driver that access CREG trough the
      syscon regmap interface.
      These clocks are needed to support peripherals like the
      internal RTC on lpc18xx.
      Signed-off-by: default avatarJoachim Eastwood <manabian@gmail.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
    • Stephen Boyd's avatar
      Merge tag 'v4.6-rockchip-clk2' of... · 37655fae
      Stephen Boyd authored
      Merge tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
      Pull second batch of rockchip clk updates from Heiko Stuebner:
      Inclusion of the rk3368 fractional dividers into our handling scheme,
      fixes for missing error-handling in mmc-phase, inverters and cpu-clocks
      and some more clock-ids.
      * tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
        clk: rockchip: include downstream muxes into fractional dividers on rk3368
        clk: rockchip: set the clock ids for RK3228 HDMI
        clk: rockchip: set the clock ids for RK3228 VOP
        clk: rockchip: add the tsadc clocks found on rk3228 SoCs
        clk: rockchip: add the new clock ids for RK3228 HDMI
        clk: rockchip: add the new clock ids for RK3228 VOP
        clk: rockchip: add id of the tsadc clock found on rk3228 SoCs
        clk: rockchip: fix coding style for clk-cpu.c
        clk: rockchip: don't return NULL when registering mmc branch fails
        clk: rockchip: don't return NULL when registering inverter fails
        clk: rockchip: check grf when waiting pll lock
        clk: rockchip: disable alt_parent clk in err cases when registering cpuclk
  2. 03 Mar, 2016 8 commits
  3. 02 Mar, 2016 22 commits
  4. 01 Mar, 2016 4 commits
  5. 29 Feb, 2016 1 commit
    • Archit Taneja's avatar
      clk: qcom: Fix pre-divider usage for pixel RCG · 811a498e
      Archit Taneja authored
      The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading
      its current value from the NS register.
      Using the pre-divider wasn't really intended when creating these ops.
      The pixel RCG was only intended to achieve fractional multiplication
      provided in the pixel_table array. Leaving the pre-divider to the
      existing register value results in a wrong pixel clock when the
      bootloader sets up the display. This was left unidentified because
      the IFC6410 Plus board on which this was verified didn't have a
      bootloader that configured the display.
      Don't set the RCG pre-divider in freq_tbl to the existing NS register
      value. Force it to 1 and only use the M/N counter to achieve the desired
      fractional multiplication.
      Cc: Vinay Simha <vinaysimha@inforcecomputing.com>
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Tested-by: default avatarJohn Stultz <john.stultz@linaro.org>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
  6. 27 Feb, 2016 2 commits
  7. 26 Feb, 2016 1 commit