1. 12 May, 2014 1 commit
    • Dinh Nguyen's avatar
      clk: socfpga: add divider registers to the main pll outputs · 0691bb1b
      Dinh Nguyen authored
      The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main
      PLL go through a pre-divider before coming into the system. These registers
      were hidden for the CycloneV platform, but are now used for the ArriaV
      platform.
      
      This patch updates the clock driver to read the div-reg property for the
      socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use.
      Signed-off-by: default avatarDinh Nguyen <dinguyen@altera.com>
      0691bb1b
  2. 18 Feb, 2014 1 commit