1. 12 May, 2014 1 commit
    • Dinh Nguyen's avatar
      clk: socfpga: add divider registers to the main pll outputs · 0691bb1b
      Dinh Nguyen authored
      The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main
      PLL go through a pre-divider before coming into the system. These registers
      were hidden for the CycloneV platform, but are now used for the ArriaV
      platform.
      
      This patch updates the clock driver to read the div-reg property for the
      socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use.
      Signed-off-by: default avatarDinh Nguyen <dinguyen@altera.com>
      0691bb1b
  2. 30 Apr, 2014 1 commit
    • Dinh Nguyen's avatar
      clk: socfpga: fix clock driver for 3.15 · a30d27ed
      Dinh Nguyen authored
      commit [1771b10d clk: respect the clock dependencies in of_clk_init]
      exposed a flaw in the socfpga clock driver and prevents the platform
      from booting on 3.15-rc1.
      
      Because the "altr,clk-mgr" is not really a clock, it should not be using
      CLK_OF_DECLARE, instead we should be mapping the clk-mgr's base address
      one of the functional clock init function. Use the socfpga_pll_init function
      to map the clk_mgr_base_addr as this clock should always be initialized first.
      Signed-off-by: default avatarDinh Nguyen <dinguyen@altera.com>
      Tested-by: default avatarPavel Machek <pavel@denx.de>
      a30d27ed
  3. 19 Mar, 2014 1 commit
    • Dinh Nguyen's avatar
      clk: socfpga: Fix section mismatch warning · 95bb9f51
      Dinh Nguyen authored
      WARNING: drivers/clk/socfpga/built-in.o(.data+0xc0): Section mismatch in
      reference from the variable socfpga_child_clocks to the function
      .init.text:socfpga_pll_init()
      The variable socfpga_child_clocks references
      the function __init socfpga_pll_init()
      If the reference is valid then annotate the
      variable with __init* or __refdata (see linux/init.h) or name the variable:
      *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
      
      WARNING: drivers/clk/socfpga/built-in.o(.data+0x184): Section mismatch in
      reference from the variable socfpga_child_clocks to the function
      .init.text:socfpga_periph_init()
      The variable socfpga_child_clocks references
      the function __init socfpga_periph_init()
      If the reference is valid then annotate the
      variable with __init* or __refdata (see linux/init.h) or name the variable:
      *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
      
      WARNING: drivers/clk/socfpga/built-in.o(.data+0x248): Section mismatch in
      reference from the variable socfpga_child_clocks to the function
      .init.text:socfpga_gate_init()
      The variable socfpga_child_clocks references
      the function __init socfpga_gate_init()
      If the reference is valid then annotate the
      variable with __init* or __refdata (see linux/init.h) or name the variable:
      *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
      Reported-by: default avatarMike Turquette <mturquette@linaro.org>
      Signed-off-by: default avatarDinh Nguyen <dinguyen@altera.com>
      Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      95bb9f51
  4. 26 Feb, 2014 2 commits
  5. 18 Feb, 2014 7 commits
  6. 19 Dec, 2013 1 commit
  7. 27 Nov, 2013 1 commit
  8. 07 Oct, 2013 1 commit
  9. 11 Jun, 2013 1 commit
  10. 14 Apr, 2013 1 commit
  11. 19 Jul, 2012 1 commit