1. 20 Sep, 2016 1 commit
    • Paul Burton's avatar
      irqchip/mips-gic: Fix local interrupts · e875bd66
      Paul Burton authored
      Since the device hierarchy domain was added by commit c98c1822
      ("irqchip/mips-gic: Add device hierarchy domain"), GIC local interrupts
      have been broken.
      Users attempting to setup a per-cpu local IRQ, for example the GIC timer
      clock events code in drivers/clocksource/mips-gic-timer.c, the
      setup_percpu_irq function would refuse with -EINVAL because the GIC
      irqchip driver never called irq_set_percpu_devid so the
      IRQ_PER_CPU_DEVID flag was never set for the IRQ. This happens because
      irq_set_percpu_devid was being called from the gic_irq_domain_map
      function which is no longer called.
      Doing only that runs into further problems because gic_dev_domain_alloc
      set the struct irq_chip for all interrupts, local or shared, to
      gic_level_irq_controller despite that only being suitable for shared
      interrupts. The typical outcome of this is that gic_level_irq_controller
      callback functions are called for local interrupts, and then hwirq
      number calculations overflow & the driver ends up attempting to access
      some invalid register with an address calculated from an invalid hwirq
      number. Best case scenario is that this then leads to a bus error. This
      is fixed by abstracting the setup of the hwirq & chip to a new function
      gic_setup_dev_chip which is used by both the root GIC IRQ domain & the
      device domain.
      Finally, decoding local interrupts failed because gic_dev_domain_alloc
      only called irq_domain_alloc_irqs_parent for shared interrupts. Local
      ones were therefore never associated with hwirqs in the root GIC IRQ
      domain and the virq in gic_handle_local_int would always be 0. This is
      fixed by calling irq_domain_alloc_irqs_parent unconditionally & having
      gic_irq_domain_alloc handle both local & shared interrupts, which is
      easy due to the aforementioned abstraction of chip setup into
      This fixes use of the MIPS GIC timer for clock events, which has been
      broken since c98c1822 ("irqchip/mips-gic: Add device hierarchy
      domain") but hadn't been noticed due to a silent fallback to the MIPS
      coprocessor 0 count/compare clock events device.
      Fixes: c98c1822 ("irqchip/mips-gic: Add device hierarchy domain")
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Qais Yousef <qsyousef@gmail.com>
      Cc: stable@vger.kernel.org
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Link: http://lkml.kernel.org/r/20160913165335.31389-1-paul.burton@imgtec.comSigned-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
  2. 19 Sep, 2016 1 commit
    • James Morse's avatar
      irqchip/gicv3: Silence noisy DEBUG_PER_CPU_MAPS warning · 727653d6
      James Morse authored
      gic_raise_softirq() walks the list of cpus using for_each_cpu(), it calls
      gic_compute_target_list() which advances the iterator by the number of
      CPUs in the cluster.
      If gic_compute_target_list() reaches the last CPU it leaves the iterator
      pointing at the last CPU. This means the next time round the for_each_cpu()
      loop cpumask_next() will be called with an invalid CPU.
      This triggers a warning when built with CONFIG_DEBUG_PER_CPU_MAPS:
      [    3.077738] GICv3: CPU1: found redistributor 1 region 0:0x000000002f120000
      [    3.077943] CPU1: Booted secondary processor [410fd0f0]
      [    3.078542] ------------[ cut here ]------------
      [    3.078746] WARNING: CPU: 1 PID: 0 at ../include/linux/cpumask.h:121 gic_raise_softirq+0x12c/0x170
      [    3.078812] Modules linked in:
      [    3.078869]
      [    3.078930] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 4.8.0-rc5+ #5188
      [    3.078994] Hardware name: Foundation-v8A (DT)
      [    3.079059] task: ffff80087a1a0080 task.stack: ffff80087a19c000
      [    3.079145] PC is at gic_raise_softirq+0x12c/0x170
      [    3.079226] LR is at gic_raise_softirq+0xa4/0x170
      [    3.079296] pc : [<ffff0000083ead24>] lr : [<ffff0000083eac9c>] pstate: 200001c9
      [    3.081139] Call trace:
      [    3.081202] Exception stack(0xffff80087a19fbe0 to 0xffff80087a19fd10)
      [    3.082269] [<ffff0000083ead24>] gic_raise_softirq+0x12c/0x170
      [    3.082354] [<ffff00000808e614>] smp_send_reschedule+0x34/0x40
      [    3.082433] [<ffff0000080e80a0>] resched_curr+0x50/0x88
      [    3.082512] [<ffff0000080e89d0>] check_preempt_curr+0x60/0xd0
      [    3.082593] [<ffff0000080e8a60>] ttwu_do_wakeup+0x20/0xe8
      [    3.082672] [<ffff0000080e8bb8>] ttwu_do_activate+0x90/0xc0
      [    3.082753] [<ffff0000080ea9a4>] try_to_wake_up+0x224/0x370
      [    3.082836] [<ffff0000080eabc8>] default_wake_function+0x10/0x18
      [    3.082920] [<ffff000008103134>] __wake_up_common+0x5c/0xa0
      [    3.083003] [<ffff0000081031f4>] __wake_up_locked+0x14/0x20
      [    3.083086] [<ffff000008103f80>] complete+0x40/0x60
      [    3.083168] [<ffff00000808df7c>] secondary_start_kernel+0x15c/0x1d0
      [    3.083240] [<00000000808911a4>] 0x808911a4
      [    3.113401] Detected PIPT I-cache on CPU2
      Avoid updating the iterator if the next call to cpumask_next() would
      cause the for_each_cpu() loop to exit.
      There is no change to gic_raise_softirq()'s behaviour, (cpumask_next()s
      eventual call to _find_next_bit() will return early as start >= nbits),
      this patch just silences the warning.
      Fixes: 021f6537 ("irqchip: gic-v3: Initial support for GICv3")
      Signed-off-by: default avatarJames Morse <james.morse@arm.com>
      Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: Jason Cooper <jason@lakedaemon.net>
      Link: http://lkml.kernel.org/r/1474306155-3303-1-git-send-email-james.morse@arm.comSigned-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
  3. 13 Sep, 2016 1 commit
  4. 22 Aug, 2016 2 commits
    • Paul Burton's avatar
      irqchip/mips-gic: Implement activate op for device domain · 2564970a
      Paul Burton authored
      If an IRQ is setup using __setup_irq(), which is used by the
      request_irq() family of functions, and we are using an SMP kernel then
      the affinity of the IRQ will be set via setup_affinity() immediately
      after the IRQ is enabled. This call to gic_set_affinity() will lead to
      the interrupt being mapped to a VPE. However there are other ways to use
      IRQs which don't cause affinity to be set, for example if it is used to
      chain to another IRQ controller with irq_set_chained_handler_and_data().
      The irq_set_chained_handler_and_data() code path will enable the IRQ,
      but will not trigger a call to gic_set_affinity() and in this case
      nothing will map the interrupt to a VPE, meaning that the interrupt is
      never received.
      Fix this by implementing the activate operation for the GIC device IRQ
      domain, using gic_shared_irq_domain_map() to map the interrupt to the
      correct pin of cpu 0.
      Fixes: c98c1822 ("irqchip/mips-gic: Add device hierarchy domain")
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: stable@vger.kernel.org
      Link: http://lkml.kernel.org/r/20160819170715.27820-2-paul.burton@imgtec.comSigned-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
    • Paul Burton's avatar
      irqchip/mips-gic: Cleanup chip and handler setup · 6a33fa2b
      Paul Burton authored
      gic_shared_irq_domain_map() is called from gic_irq_domain_alloc() where
      the wrong chip has been set, and is then overwritten. Tidy this up by
      setting the correct chip the first time, and setting the
      handle_level_irq handler from gic_irq_domain_alloc() too.
      gic_shared_irq_domain_map() is also called from gic_irq_domain_map(),
      which now calls irq_set_chip_and_handler() to retain its previous
      This patch prepares for a follow-on which will call
      gic_shared_irq_domain_map() from a callback where the lock on the struct
      irq_desc is held, which without this change would cause the call to
      irq_set_chip_and_handler() to lead to a deadlock.
      Fixes: c98c1822 ("irqchip/mips-gic: Add device hierarchy domain")
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: stable@vger.kernel.org
      Link: http://lkml.kernel.org/r/20160819170715.27820-1-paul.burton@imgtec.comSigned-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
  5. 19 Aug, 2016 1 commit
    • David Daney's avatar
      irqchip/gicv3-its: Disable the ITS before initializing it · 7611da86
      David Daney authored
      When starting a kexec/kdump kernel, the GIC ITS will already have been
      enabled.  According to the ARM Generic Interrupt Controller
      Architecture Specification (GIC architecture Version 3.0 and version
      4.0), writing to GITS_BASER<n> or GITS_CBASER is "UNPREDICTABLE" when
      the ITS is enabled.  On Cavium Thunder systems, this prevents the ITS
      from being initializing in the kexec/kdump kernel, resulting in
      failure to register/enable interrupts for all devices.
      The fix is to disable the ITS if it is not already in the disabled
      state.  This allows the ITS to be properly initialized and then
      re-enabled in the kexec/kdump kernel.
      Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
  6. 17 Aug, 2016 2 commits
    • Sudeep Holla's avatar
      irqchip/gicv3: Remove disabling redistributor and group1 non-secure interrupts · ccd9432a
      Sudeep Holla authored
      As per the GICv3 specification, to power down a processor using GICv3
      and allow automatic power-on if an interrupt must be sent to a processor,
      software must set Enable to zero for all interrupt groups(by writing
      to GICC_CTLR or ICC_IGRPEN{0,1}_EL1/3 as appropriate.
      When commit 3708d52f ("irqchip: gic-v3: Implement CPU PM notifier")
      was introduced there were no firmware implementations(in particular PSCI)
      handling this.
      Linux kernel may not be aware of the CPU power state details and might
      fail to identify the power states that require quiescing the CPU
      interface. Even if it can be aware of those details, it can't determine
      which CPU power state have been triggered at the platform level and how
      the power control is implemented.
      This patch make disabling redistributor and group1 non-secure interrupts
      in the power down path and re-enabling of redistributor in the power-up
      path conditional. It will be handled in the kernel if and only if the
      non-secure accesses are permitted to access and modify control registers.
      It is left to the platform implementation otherwise.
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Tested-by: default avatarChristopher Covington <cov@codeaurora.org>
      Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
    • Marc Zyngier's avatar
      irqchip/gic: Allow self-SGIs for SMP on UP configurations · 059e2320
      Marc Zyngier authored
      On systems where a single CPU is present, the GIC may not support
      having SGIs delivered to a target list. In that case, we use the
      self-SGI mechanism to allow the interrupt to be delivered locally.
      Tested-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
  7. 04 Aug, 2016 1 commit
    • Masahiro Yamada's avatar
      tree-wide: replace config_enabled() with IS_ENABLED() · 97f2645f
      Masahiro Yamada authored
      The use of config_enabled() against config options is ambiguous.  In
      practical terms, config_enabled() is equivalent to IS_BUILTIN(), but the
      author might have used it for the meaning of IS_ENABLED().  Using
      IS_ENABLED(), IS_BUILTIN(), IS_MODULE() etc.  makes the intention
      This commit replaces config_enabled() with IS_ENABLED() where possible.
      This commit is only touching bool config options.
      I noticed two cases where config_enabled() is used against a tristate
       - config_enabled(CONFIG_HWMON)
        [ drivers/net/wireless/ath/ath10k/thermal.c ]
       - config_enabled(CONFIG_BACKLIGHT_CLASS_DEVICE)
        [ drivers/gpu/drm/gma500/opregion.c ]
      I did not touch them because they should be converted to IS_BUILTIN()
      in order to keep the logic, but I was not sure it was the authors'
      Link: http://lkml.kernel.org/r/1465215656-20569-1-git-send-email-yamada.masahiro@socionext.comSigned-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      Acked-by: default avatarKees Cook <keescook@chromium.org>
      Cc: Stas Sergeev <stsp@list.ru>
      Cc: Matt Redfearn <matt.redfearn@imgtec.com>
      Cc: Joshua Kinard <kumba@gentoo.org>
      Cc: Jiri Slaby <jslaby@suse.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Borislav Petkov <bp@suse.de>
      Cc: Markos Chandras <markos.chandras@imgtec.com>
      Cc: "Dmitry V. Levin" <ldv@altlinux.org>
      Cc: yu-cheng yu <yu-cheng.yu@intel.com>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: Brian Gerst <brgerst@gmail.com>
      Cc: Johannes Berg <johannes@sipsolutions.net>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Al Viro <viro@zeniv.linux.org.uk>
      Cc: Will Drewry <wad@chromium.org>
      Cc: Nikolay Martynov <mar.kolya@gmail.com>
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Daniel Borkmann <daniel@iogearbox.net>
      Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
      Cc: Rafal Milecki <zajec5@gmail.com>
      Cc: James Cowgill <James.Cowgill@imgtec.com>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Alex Smith <alex.smith@imgtec.com>
      Cc: Adam Buchbinder <adam.buchbinder@gmail.com>
      Cc: Qais Yousef <qais.yousef@imgtec.com>
      Cc: Jiang Liu <jiang.liu@linux.intel.com>
      Cc: Mikko Rapeli <mikko.rapeli@iki.fi>
      Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
      Cc: Denys Vlasenko <dvlasenk@redhat.com>
      Cc: Brian Norris <computersforpeace@gmail.com>
      Cc: Hidehiro Kawai <hidehiro.kawai.ez@hitachi.com>
      Cc: "Luis R. Rodriguez" <mcgrof@do-not-panic.com>
      Cc: Andy Lutomirski <luto@amacapital.net>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Dave Hansen <dave.hansen@linux.intel.com>
      Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
      Cc: Roland McGrath <roland@hack.frob.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Kalle Valo <kvalo@qca.qualcomm.com>
      Cc: Viresh Kumar <viresh.kumar@linaro.org>
      Cc: Tony Wu <tung7970@gmail.com>
      Cc: Huaitong Han <huaitong.han@intel.com>
      Cc: Sumit Semwal <sumit.semwal@linaro.org>
      Cc: Alexei Starovoitov <ast@kernel.org>
      Cc: Juergen Gross <jgross@suse.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: Oleg Nesterov <oleg@redhat.com>
      Cc: Andrea Gelmini <andrea.gelmini@gelma.net>
      Cc: David Woodhouse <dwmw2@infradead.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Rabin Vincent <rabin@rab.in>
      Cc: "Maciej W. Rozycki" <macro@imgtec.com>
      Cc: David Daney <david.daney@cavium.com>
      Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
  8. 19 Jul, 2016 1 commit
    • Arnd Bergmann's avatar
      irqchip/armada: Avoid unused function warnings · c76c15e6
      Arnd Bergmann authored
      When building with CONFIG_SMP disabled, we get some new harmless warnings:
       drivers/irqchip/irq-armada-370-xp.c:356:12: error: 'mpic_cascaded_starting_cpu' defined but not used [-Werror=unused-function]
        static int mpic_cascaded_starting_cpu(unsigned int cpu)
       drivers/irqchip/irq-armada-370-xp.c:349:12: error: 'armada_xp_mpic_starting_cpu' defined but not used [-Werror=unused-function]
        static int armada_xp_mpic_starting_cpu(unsigned int cpu)
      This moves the unused functions into the #ifdef, as they previously were.
      Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      Acked-by: default avatarJason Cooper <jason@lakedaemon.net>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Richard Cochran <rcochran@linutronix.de>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
      Fixes: cb5ff2d2 ("irqchip/armada-370-xp: Convert to hotplug state machine")
      Link: http://lkml.kernel.org/r/20160718160335.3134412-1-arnd@arndb.deSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
  9. 14 Jul, 2016 5 commits
  10. 06 Jul, 2016 1 commit
  11. 05 Jul, 2016 2 commits
    • Paul Burton's avatar
      irqchip/mips-gic: Match IPI IRQ domain by bus token only · 547aefc4
      Paul Burton authored
      Commit fbde2d7d ("MIPS: Add generic SMP IPI support") introduced
      code which calls irq_find_matching_host with a NULL node parameter in
      order to discover IPI IRQ domains which are not associated with the DT
      root node's interrupt parent. This suggests that implementations of IPI
      IRQ domains should effectively ignore the node parameter if it is NULL
      and search purely based upon the bus token. Commit 2af70a96
      ("irqchip/mips-gic: Add a IPI hierarchy domain") did not do this when
      implementing the GIC IPI IRQ domain, and on MIPS Boston boards this
      leads to no IPI domain being discovered and a NULL pointer dereference
      when attempting to send an IPI:
        CPU 0 Unable to handle kernel paging request at virtual address 0000000000000040, epc == ffffffff8016e70c, ra == ffffffff8010ff5c
        CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.7.0-rc6-00223-gad0d1b6 #945
        task: a8000000ff066fc0 ti: a8000000ff068000 task.ti: a8000000ff068000
        $ 0   : 0000000000000000 0000000000000001 ffffffff80730000 0000000000000003
        $ 4   : 0000000000000000 ffffffff8057e5b0 a800000001e3ee00 0000000000000000
        $ 8   : 0000000000000000 0000000000000023 0000000000000001 0000000000000001
        $12   : 0000000000000000 ffffffff803323d0 0000000000000000 0000000000000000
        $16   : 0000000000000000 0000000000000000 0000000000000001 ffffffff801108fc
        $20   : 0000000000000000 ffffffff8057e5b0 0000000000000001 0000000000000000
        $24   : 0000000000000000 ffffffff8012de28
        $28   : a8000000ff068000 a8000000ff06fbc0 0000000000000000 ffffffff8010ff5c
        Hi    : ffffffff8014c174
        Lo    : a800000001e1e140
        epc   : ffffffff8016e70c __ipi_send_mask+0x24/0x11c
        ra    : ffffffff8010ff5c mips_smp_send_ipi_mask+0x68/0x178
        Status: 140084e2        KX SX UX KERNEL EXL
        Cause : 00800008 (ExcCode 02)
        BadVA : 0000000000000040
        PrId  : 0001a920 (MIPS I6400)
        Process swapper/0 (pid: 1, threadinfo=a8000000ff068000, task=a8000000ff066fc0, tls=0000000000000000)
        Stack : 0000000000000000 0000000000000000 0000000000000001 ffffffff801108fc
                  0000000000000000 ffffffff8057e5b0 0000000000000001 ffffffff8010ff5c
                  0000000000000001 0000000000000020 0000000000000000 0000000000000000
                  0000000000000000 ffffffff801108fc 0000000000000000 0000000000000001
                  0000000000000001 0000000000000000 0000000000000000 ffffffff801865e8
                  a8000000ff0c7500 a8000000ff06fc90 0000000000000001 0000000000000002
                  ffffffff801108fc ffffffff801868b8 0000000000000000 ffffffff801108fc
                  0000000000000000 0000000000000003 ffffffff8068c700 0000000000000001
                  ffffffff80730000 0000000000000001 a8000000ff00a290 ffffffff80110c50
                  0000000000000003 a800000001e48308 0000000000000003 0000000000000008
        Call Trace:
        [<ffffffff8016e70c>] __ipi_send_mask+0x24/0x11c
        [<ffffffff8010ff5c>] mips_smp_send_ipi_mask+0x68/0x178
        [<ffffffff801865e8>] generic_exec_single+0x150/0x170
        [<ffffffff801868b8>] smp_call_function_single+0x108/0x160
        [<ffffffff80110c50>] cps_boot_secondary+0x328/0x394
        [<ffffffff80110534>] __cpu_up+0x38/0x90
        [<ffffffff8012de4c>] bringup_cpu+0x24/0xac
        [<ffffffff8012df40>] cpuhp_up_callbacks+0x58/0xdc
        [<ffffffff8012e648>] cpu_up+0x118/0x18c
        [<ffffffff806dc158>] smp_init+0xbc/0xe8
        [<ffffffff806d4c18>] kernel_init_freeable+0xa0/0x228
        [<ffffffff8056c908>] kernel_init+0x10/0xf0
        [<ffffffff80105098>] ret_from_kernel_thread+0x14/0x1c
      Fix this by allowing the GIC IPI IRQ domain to match purely based upon
      the bus token if the node provided is NULL.
      Fixes: 2af70a96 ("irqchip/mips-gic: Add a IPI hierarchy domain")
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Qais Yousef <qsyousef@gmail.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: stable@vger.kernel.org
      Link: http://lkml.kernel.org/r/20160705132600.27730-2-paul.burton@imgtec.comSigned-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
    • Paul Burton's avatar
      irqchip/mips-gic: Map to VPs using HW VPNum · 99ec8a36
      Paul Burton authored
      When mapping an interrupt to a VP(E) we must use the identifier for the
      VP that the hardware expects, and this does not always match up with the
      Linux CPU number. Commit d46812bb ("irqchip: mips-gic: Use HW IDs
      for VPE_OTHER_ADDR") corrected this for the cases that existed at the
      time it was written, but commit 2af70a96 ("irqchip/mips-gic: Add a
      IPI hierarchy domain") added another case before the former patch was
      merged. This leads to incorrectly using Linux CPU numbers when mapping
      interrupts to VPs, which breaks on certain systems such as those with
      multi-core I6400 CPUs. Fix by adding the appropriate call to
      mips_cm_vp_id() to retrieve the expected VP identifier.
      Fixes: d46812bb ("irqchip: mips-gic: Use HW IDs for VPE_OTHER_ADDR")
      Fixes: 2af70a96 ("irqchip/mips-gic: Add a IPI hierarchy domain")
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Qais Yousef <qsyousef@gmail.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: stable@vger.kernel.org
      Link: http://lkml.kernel.org/r/20160705132600.27730-1-paul.burton@imgtec.comSigned-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
  12. 23 Jun, 2016 2 commits
  13. 22 Jun, 2016 1 commit
  14. 15 Jun, 2016 1 commit
    • Arnd Bergmann's avatar
      PCI/MSI: irqchip: Fix PCI_MSI dependencies · 3ee80364
      Arnd Bergmann authored
      The PCI_MSI symbol is used inconsistently throughout the tree, with some
      drivers using 'select' and others using 'depends on', or using conditional
      selects.  This keeps causing problems; the latest one is a result of
      ARCH_ALPINE using a 'select' statement to enable its platform-specific MSI
      driver without enabling MSI:
        warning: (ARCH_ALPINE) selects ALPINE_MSI which has unmet direct dependencies (PCI && PCI_MSI)
        drivers/irqchip/irq-alpine-msi.c:104:15: error: variable 'alpine_msix_domain_info' has initializer but incomplete type
         static struct msi_domain_info alpine_msix_domain_info = {
        drivers/irqchip/irq-alpine-msi.c:105:2: error: unknown field 'flags' specified in initializer
        drivers/irqchip/irq-alpine-msi.c:105:11: error: 'MSI_FLAG_USE_DEF_DOM_OPS' undeclared here (not in a function)
      There is little reason to enable PCI support for a platform that uses MSI
      but then leave MSI disabled at compile time.
      Select PCI_MSI from irqchips that implement MSI, and make PCI host bridges
      that use MSI on ARM depend on PCI_MSI_IRQ_DOMAIN.
      For all three architectures that support PCI_MSI_IRQ_DOMAIN (ARM, ARM64,
      X86), enable it by default whenever MSI is enabled.
      [bhelgaas: changelog, omit crypto config change]
      Suggested-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
  15. 14 Jun, 2016 2 commits
  16. 13 Jun, 2016 9 commits
    • Shanker Donthineni's avatar
      irqchip/gicv3-its: Implement two-level(indirect) device table support · 3faf24ea
      Shanker Donthineni authored
      Since device IDs are extremely sparse, the single, a.k.a flat table is
      not sufficient for the following two reasons.
      1) According to ARM-GIC spec, ITS hw can access maximum of 256(pages)*
         64K(pageszie) bytes. In the best case, it supports upto DEVid=21
         sparse with minimum device table entry size 8bytes.
      2) The maximum memory size that is possible without memblock depends on
         MAX_ORDER. 4MB on 4K page size kernel with default MAX_ORDER, so it
         supports DEVid range 19bits.
      The two-level device table feature brings us two advantages, the first
      is a very high possibility of supporting upto 32bit sparse, and the
      second one is the best utilization of memory allocation.
      The feature is enabled automatically during driver probe if the memory
      requirement is more than 2*ITS-pages and the hardware is capable of
      two-level table walk.
      Signed-off-by: default avatarShanker Donthineni <shankerd@codeaurora.org>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
    • Shanker Donthineni's avatar
      irqchip/gicv3-its: Remove an unused argument 'node_name' · 0e0b0f69
      Shanker Donthineni authored
      No references to argument 'node_name' after modifying pr_xxx()
      messages to include ITS base address instead of 'node_name'.
      Signed-off-by: default avatarShanker Donthineni <shankerd@codeaurora.org>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
    • Shanker Donthineni's avatar
      irqchip/gicv3-its: Split its_alloc_tables() into two functions · 9347359a
      Shanker Donthineni authored
      The function is getting out of control, it has too many goto
      statements and would be too complicated for adding a feature
      two-level device table. So, it is time for us to cleanup and
      move some of the logic to a separate function without affecting
      the existing functionality.
      Signed-off-by: default avatarShanker Donthineni <shankerd@codeaurora.org>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
    • Shanker Donthineni's avatar
      irqchip/gicv3-its: Add a new function for parsing device table BASERn · 4b75c459
      Shanker Donthineni authored
      Only the device table BASERn needs to be handled differently as
      compared to all other tables. So, adding a separate function for
      easy code maintenance and improved code readability.
      Signed-off-by: default avatarShanker Donthineni <shankerd@codeaurora.org>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
    • Shanker Donthineni's avatar
      irqchip/gicv3-its: Introduce two helper functions for accessing BASERn · 2d81d425
      Shanker Donthineni authored
      This patch adds the two handy helper functions for reading and writing
      ITS BASERn register.
      Signed-off-by: default avatarShanker Donthineni <shankerd@codeaurora.org>
      [Marc: Folded its_write_baser_cache into its_write_baser]
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
    • Jon Hunter's avatar
      irqchip/gic: Add platform driver for non-root GICs that require RPM · 9c8edddf
      Jon Hunter authored
      Add a platform driver to support non-root GICs that require runtime
      power-management. Currently, only non-root GICs are supported because
      the functions, smp_cross_call() and set_handle_irq(), that need to
      be called for a root controller are located in the __init section and
      so cannot be called by the platform driver.
      The GIC platform driver re-uses many functions from the existing GIC
      driver including some functions to save and restore the GIC context
      during power transitions. The functions for saving and restoring the
      GIC context are currently only defined if CONFIG_CPU_PM is enabled and
      to ensure that these functions are always defined when the platform
      driver is enabled, a dependency on CONFIG_ARM_GIC_PM (which selects the
      platform driver) has been added.
      In order to re-use the private GIC initialisation code, a new public
      function, gic_of_init_child(), has been added which calls various
      private functions to initialise the GIC. This is different from the
      existing gic_of_init() because it only supports non-root GICs (ie. does
      not call smp_cross_call() is set_handle_irq()) and is not located in
      the __init section (so can be used by platform drivers). Furthermore,
      gic_of_init_child() dynamically allocates memory for the GIC chip data
      which is also different from gic_of_init().
      There is no specific suspend handling for GICs registered as platform
      devices. Non-wakeup interrupts will be disabled by the kernel during
      late suspend, however, this alone will not power down the GIC if
      interrupts have been requested and not freed. Therefore, requestors of
      non-wakeup interrupts will need to free them on entering suspend in
      order to power-down the GIC.
      Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
    • Jon Hunter's avatar
      irqchip/gic: Prepare for adding platform driver · cdbb813d
      Jon Hunter authored
      To support GICs that require runtime power management, it is necessary
      to add a platform driver, so that the probing of the chip can be
      deferred if resources, such as a power-domain, is not yet available.
      To prepare for adding a platform driver:
       1. Drop the __init section from the gic_dist_config() so this can be
          re-used by the platform driver.
       2. Add prototypes for functions required by the platform driver to the
          GIC header file so they can be re-used.
      Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
    • Jon Hunter's avatar
      irqchip/gic: Add helper function for chip initialisation · faea6455
      Jon Hunter authored
      For GICs that require runtime power-management it is necessary to
      populate the 'parent_device' member of the irqchip structure. In
      preparation for supporting such GICs, move the code that initialises
      the irqchip structure for a GIC into its own function called
      gic_init_chip() where the parent device pointer is also set.
      Instead of calling gic_init_chip() from within gic_init_bases(), move
      the calls to outside of this function, so that in the future we can
      avoid having to pass additional parameters to gic_init_bases() in order
      set the parent device pointer or set the name to a specific string.
      Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
    • Jon Hunter's avatar
      irqchip/gic: Isolate early GIC initialisation code · d6ce564c
      Jon Hunter authored
      To re-use the code that initialises the GIC (found in
      __gic_init_bases()), from within a platform driver, it is necessary to
      move the code from the __init section so that it is always present and
      not removed. Unfortunately, it is not possible to simply drop the __init
      from the function declaration for __gic_init_bases() because it contains
      calls to set_smp_cross_call() and set_handle_irq() which are both
      located in the __init section. Fortunately, these calls are only
      required for the root controller and because the initial platform driver
      will only support non-root controllers that can be initialised later in
      the boot process, we can move these calls to another function.
      Move the bulk of the code from __gic_init_bases() to a new function
      called gic_init_bases() which is not located in the __init section and
      can be used by the platform driver. Update __gic_init_bases() to call
      gic_init_bases() and if necessary, set_smp_cross_call() and
      Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
  17. 12 Jun, 2016 7 commits