Commit dbe91a2e authored by Ken Cox's avatar Ken Cox Committed by Mark Salter

C6X: add basic support for TMS320C6678 SoC

This patch adds support for the TMS320C6678 SoC on an EVMC6678LE
evaluation board. The 6678 is a C66x family CPU which is very similar
to the already supported C64x CPUs with the addition of floating point
instructions.
Signed-off-by: default avatarKen Cox <jkc@redhat.com>
Signed-off-by: default avatarMark Salter <msalter@redhat.com>
CC: Aurelien Jacquiot <a-jacquiot@ti.com>
CC: linux-c6x-dev@linux-c6x.org
parent f84f1f46
/*
* arch/c6x/boot/dts/evmc6678.dts
*
* EVMC6678 Evaluation Platform For TMS320C6678
*
* Copyright (C) 2012 Texas Instruments Incorporated
*
* Author: Ken Cox <jkc@redhat.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
*/
/dts-v1/;
/include/ "tms320c6678.dtsi"
/ {
model = "Advantech EVMC6678";
compatible = "advantech,evmc6678";
chosen {
bootargs = "root=/dev/nfs ip=dhcp rw";
};
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
soc {
megamod_pic: interrupt-controller@1800000 {
interrupts = < 12 13 14 15 >;
};
timer8: timer@2280000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 66 >;
};
timer9: timer@2290000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 68 >;
};
timer10: timer@22A0000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 70 >;
};
timer11: timer@22B0000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 72 >;
};
timer12: timer@22C0000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 74 >;
};
timer13: timer@22D0000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 76 >;
};
timer14: timer@22E0000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 78 >;
};
timer15: timer@22F0000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 80 >;
};
clock-controller@2310000 {
clock-frequency = <100000000>;
};
};
};
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
reg = <0>;
model = "ti,c66x";
};
cpu@1 {
device_type = "cpu";
reg = <1>;
model = "ti,c66x";
};
cpu@2 {
device_type = "cpu";
reg = <2>;
model = "ti,c66x";
};
cpu@3 {
device_type = "cpu";
reg = <3>;
model = "ti,c66x";
};
cpu@4 {
device_type = "cpu";
reg = <4>;
model = "ti,c66x";
};
cpu@5 {
device_type = "cpu";
reg = <5>;
model = "ti,c66x";
};
cpu@6 {
device_type = "cpu";
reg = <6>;
model = "ti,c66x";
};
cpu@7 {
device_type = "cpu";
reg = <7>;
model = "ti,c66x";
};
};
soc {
compatible = "simple-bus";
model = "tms320c6678";
#address-cells = <1>;
#size-cells = <1>;
ranges;
core_pic: interrupt-controller {
compatible = "ti,c64x+core-pic";
interrupt-controller;
#interrupt-cells = <1>;
};
megamod_pic: interrupt-controller@1800000 {
compatible = "ti,c64x+megamod-pic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x1800000 0x1000>;
interrupt-parent = <&core_pic>;
};
cache-controller@1840000 {
compatible = "ti,c64x+cache";
reg = <0x01840000 0x8400>;
};
timer8: timer@2280000 {
compatible = "ti,c64x+timer64";
ti,core-mask = < 0x01 >;
reg = <0x2280000 0x40>;
};
timer9: timer@2290000 {
compatible = "ti,c64x+timer64";
ti,core-mask = < 0x02 >;
reg = <0x2290000 0x40>;
};
timer10: timer@22A0000 {
compatible = "ti,c64x+timer64";
ti,core-mask = < 0x04 >;
reg = <0x22A0000 0x40>;
};
timer11: timer@22B0000 {
compatible = "ti,c64x+timer64";
ti,core-mask = < 0x08 >;
reg = <0x22B0000 0x40>;
};
timer12: timer@22C0000 {
compatible = "ti,c64x+timer64";
ti,core-mask = < 0x10 >;
reg = <0x22C0000 0x40>;
};
timer13: timer@22D0000 {
compatible = "ti,c64x+timer64";
ti,core-mask = < 0x20 >;
reg = <0x22D0000 0x40>;
};
timer14: timer@22E0000 {
compatible = "ti,c64x+timer64";
ti,core-mask = < 0x40 >;
reg = <0x22E0000 0x40>;
};
timer15: timer@22F0000 {
compatible = "ti,c64x+timer64";
ti,core-mask = < 0x80 >;
reg = <0x22F0000 0x40>;
};
clock-controller@2310000 {
compatible = "ti,c6678-pll", "ti,c64x+pll";
reg = <0x02310000 0x200>;
ti,c64x+pll-bypass-delay = <200>;
ti,c64x+pll-reset-delay = <12000>;
ti,c64x+pll-lock-delay = <80000>;
};
device-state-controller@2620000 {
compatible = "ti,c64x+dscr";
reg = <0x02620000 0x1000>;
ti,dscr-devstat = <0x20>;
ti,dscr-silicon-rev = <0x18 28 0xf>;
ti,dscr-mac-fuse-regs = <0x110 1 2 3 4
0x114 5 6 0 0>;
};
};
};
CONFIG_SOC_TMS320C6678=y
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_SPARSE_IRQ=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_EXPERT=y
# CONFIG_FUTEX is not set
# CONFIG_SLUB_DEBUG is not set
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_FORCE is not set
CONFIG_BOARD_EVM6678=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=2
CONFIG_BLK_DEV_RAM_SIZE=17000
CONFIG_MISC_DEVICES=y
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_IOMMU_SUPPORT is not set
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_CRC16=y
# CONFIG_ENABLE_MUST_CHECK is not set
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
......@@ -143,6 +143,10 @@ static void __init get_cpuinfo(void)
p->cpu_name = "C64x+";
p->cpu_voltage = "1.2";
break;
case 21:
p->cpu_name = "C66X";
p->cpu_voltage = "1.2";
break;
default:
p->cpu_name = "unknown";
break;
......
......@@ -14,3 +14,7 @@ config SOC_TMS320C6472
config SOC_TMS320C6474
bool "TMS320C6474"
default n
config SOC_TMS320C6678
bool "TMS320C6678"
default n
......@@ -335,6 +335,68 @@ static void __init c6474_setup_clocks(struct device_node *node)
}
#endif /* CONFIG_SOC_TMS320C6474 */
#ifdef CONFIG_SOC_TMS320C6678
static struct clk_lookup c6678_clks[] = {
CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
CLK(NULL, "pll1_refclk", &c6x_soc_pll1.sysclks[1]),
CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
CLK(NULL, "pll1_sysclk6", &c6x_soc_pll1.sysclks[6]),
CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
CLK(NULL, "pll1_sysclk8", &c6x_soc_pll1.sysclks[8]),
CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
CLK(NULL, "pll1_sysclk11", &c6x_soc_pll1.sysclks[11]),
CLK(NULL, "core", &c6x_core_clk),
CLK("", NULL, NULL)
};
static void __init c6678_setup_clocks(struct device_node *node)
{
struct pll_data *pll = &c6x_soc_pll1;
struct clk *sysclks = pll->sysclks;
pll->flags = PLL_HAS_MUL;
sysclks[1].flags |= FIXED_DIV_PLL;
sysclks[1].div = 1;
sysclks[2].div = PLLDIV2;
sysclks[3].flags |= FIXED_DIV_PLL;
sysclks[3].div = 2;
sysclks[4].flags |= FIXED_DIV_PLL;
sysclks[4].div = 3;
sysclks[5].div = PLLDIV5;
sysclks[6].flags |= FIXED_DIV_PLL;
sysclks[6].div = 64;
sysclks[7].flags |= FIXED_DIV_PLL;
sysclks[7].div = 6;
sysclks[8].div = PLLDIV8;
sysclks[9].flags |= FIXED_DIV_PLL;
sysclks[9].div = 12;
sysclks[10].flags |= FIXED_DIV_PLL;
sysclks[10].div = 3;
sysclks[11].flags |= FIXED_DIV_PLL;
sysclks[11].div = 6;
c6x_core_clk.parent = &sysclks[0];
c6x_i2c_clk.parent = &sysclks[7];
c6x_clks_init(c6678_clks);
}
#endif /* CONFIG_SOC_TMS320C6678 */
static struct of_device_id c6x_clkc_match[] __initdata = {
#ifdef CONFIG_SOC_TMS320C6455
{ .compatible = "ti,c6455-pll", .data = c6455_setup_clocks },
......@@ -347,6 +409,9 @@ static struct of_device_id c6x_clkc_match[] __initdata = {
#endif
#ifdef CONFIG_SOC_TMS320C6474
{ .compatible = "ti,c6474-pll", .data = c6474_setup_clocks },
#endif
#ifdef CONFIG_SOC_TMS320C6678
{ .compatible = "ti,c6678-pll", .data = c6678_setup_clocks },
#endif
{ .compatible = "ti,c64x+pll" },
{}
......
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