ide: prefix messages from IDE PCI host drivers by driver name

Prefix messages from IDE PCI host drivers by driver name instead of marketed
chipset name (it is still possible to exactly identify the particular chipset
basing on driver messages).

As a bonus this provides nice code savings for some drivers:

   text    data     bss     dec     hex filename
   3826     112       8    3946     f6a drivers/ide/pci/amd74xx.o.before
   2786     112       8    2906     b5a drivers/ide/pci/amd74xx.o.after
    764     108       0     872     368 drivers/ide/pci/cs5520.o.before
    680     108       0     788     314 drivers/ide/pci/cs5520.o.after
   1680     112       4    1796     704 drivers/ide/pci/generic.o.before
   1155     112       4    1271     4f7 drivers/ide/pci/generic.o.after
   7128     792       0    7920    1ef0 drivers/ide/pci/hpt366.o.before
   6984     792       0    7776    1e60 drivers/ide/pci/hpt366.o.after
   2800     148       0    2948     b84 drivers/ide/pci/pdc202xx_new.o.before
   2523     148       0    2671     a6f drivers/ide/pci/pdc202xx_new.o.after
   2831     148       0    2979     ba3 drivers/ide/pci/pdc202xx_old.o.before
   2683     148       0    2831     b0f drivers/ide/pci/pdc202xx_old.o.after
   3776     112       4    3892     f34 drivers/ide/pci/piix.o.before
   2804     112       4    2920     b68 drivers/ide/pci/piix.o.after
   4693     116       0    4809    12c9 drivers/ide/pci/siimage.o.before
   4600     116       0    4716    126c drivers/ide/pci/siimage.o.after
Signed-off-by: 's avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
parent 04ba6e73
......@@ -13,6 +13,8 @@
#include <asm/io.h>
#define DRV_NAME "aec62xx"
struct chipset_bus_clock_list_entry {
u8 xfer_speed;
u8 chipset_settings;
......@@ -180,8 +182,8 @@ static const struct ide_port_ops atp86x_port_ops = {
};
static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
{ /* 0 */
.name = "AEC6210",
{ /* 0: AEC6210 */
.name = DRV_NAME,
.init_chipset = init_chipset_aec62xx,
.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
.port_ops = &atp850_port_ops,
......@@ -192,8 +194,9 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA2,
},{ /* 1 */
.name = "AEC6260",
},
{ /* 1: AEC6260 */
.name = DRV_NAME,
.init_chipset = init_chipset_aec62xx,
.port_ops = &atp86x_port_ops,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA |
......@@ -201,8 +204,9 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA4,
},{ /* 2 */
.name = "AEC6260R",
},
{ /* 2: AEC6260R */
.name = DRV_NAME,
.init_chipset = init_chipset_aec62xx,
.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
.port_ops = &atp86x_port_ops,
......@@ -211,8 +215,9 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA4,
},{ /* 3 */
.name = "AEC6280",
},
{ /* 3: AEC6280 */
.name = DRV_NAME,
.init_chipset = init_chipset_aec62xx,
.port_ops = &atp86x_port_ops,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA |
......@@ -220,8 +225,9 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA5,
},{ /* 4 */
.name = "AEC6280R",
},
{ /* 4: AEC6280R */
.name = DRV_NAME,
.init_chipset = init_chipset_aec62xx,
.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
.port_ops = &atp86x_port_ops,
......@@ -268,7 +274,8 @@ static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_devi
unsigned long dma_base = pci_resource_start(dev, 4);
if (inb(dma_base + 2) & 0x10) {
d.name = (idx == 4) ? "AEC6880R" : "AEC6880";
printk(KERN_INFO DRV_NAME " %s: AEC6880%s card detected"
"\n", pci_name(dev), (idx == 4) ? "R" : "");
d.udma_mask = ATA_UDMA6;
}
}
......
......@@ -38,6 +38,8 @@
#include <asm/io.h>
#define DRV_NAME "alim15x3"
/*
* Allow UDMA on M1543C-E chipset for WDC disks that ignore CRC checking
* (this is DANGEROUS and could result in data corruption).
......@@ -515,7 +517,7 @@ static const struct ide_dma_ops ali_dma_ops = {
};
static const struct ide_port_info ali15x3_chipset __devinitdata = {
.name = "ALI15X3",
.name = DRV_NAME,
.init_chipset = init_chipset_ali15x3,
.init_hwif = init_hwif_ali15x3,
.init_dma = init_dma_ali15x3,
......
......@@ -21,6 +21,8 @@
#include <linux/init.h>
#include <linux/ide.h>
#define DRV_NAME "amd74xx"
enum {
AMD_IDE_CONFIG = 0x41,
AMD_CABLE_DETECT = 0x42,
......@@ -204,9 +206,9 @@ static const struct ide_port_ops amd_port_ops = {
IDE_HFLAG_IO_32BIT | \
IDE_HFLAG_UNMASK_IRQS)
#define DECLARE_AMD_DEV(name_str, swdma, udma) \
#define DECLARE_AMD_DEV(swdma, udma) \
{ \
.name = name_str, \
.name = DRV_NAME, \
.init_chipset = init_chipset_amd74xx, \
.init_hwif = init_hwif_amd74xx, \
.enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \
......@@ -218,9 +220,9 @@ static const struct ide_port_ops amd_port_ops = {
.udma_mask = udma, \
}
#define DECLARE_NV_DEV(name_str, udma) \
#define DECLARE_NV_DEV(udma) \
{ \
.name = name_str, \
.name = DRV_NAME, \
.init_chipset = init_chipset_amd74xx, \
.init_hwif = init_hwif_amd74xx, \
.enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \
......@@ -233,31 +235,15 @@ static const struct ide_port_ops amd_port_ops = {
}
static const struct ide_port_info amd74xx_chipsets[] __devinitdata = {
/* 0 */ DECLARE_AMD_DEV("AMD7401", 0x00, ATA_UDMA2),
/* 1 */ DECLARE_AMD_DEV("AMD7409", ATA_SWDMA2, ATA_UDMA4),
/* 2 */ DECLARE_AMD_DEV("AMD7411", ATA_SWDMA2, ATA_UDMA5),
/* 3 */ DECLARE_AMD_DEV("AMD7441", ATA_SWDMA2, ATA_UDMA5),
/* 4 */ DECLARE_AMD_DEV("AMD8111", ATA_SWDMA2, ATA_UDMA6),
/* 5 */ DECLARE_NV_DEV("NFORCE", ATA_UDMA5),
/* 6 */ DECLARE_NV_DEV("NFORCE2", ATA_UDMA6),
/* 7 */ DECLARE_NV_DEV("NFORCE2-U400R", ATA_UDMA6),
/* 8 */ DECLARE_NV_DEV("NFORCE2-U400R-SATA", ATA_UDMA6),
/* 9 */ DECLARE_NV_DEV("NFORCE3-150", ATA_UDMA6),
/* 10 */ DECLARE_NV_DEV("NFORCE3-250", ATA_UDMA6),
/* 11 */ DECLARE_NV_DEV("NFORCE3-250-SATA", ATA_UDMA6),
/* 12 */ DECLARE_NV_DEV("NFORCE3-250-SATA2", ATA_UDMA6),
/* 13 */ DECLARE_NV_DEV("NFORCE-CK804", ATA_UDMA6),
/* 14 */ DECLARE_NV_DEV("NFORCE-MCP04", ATA_UDMA6),
/* 15 */ DECLARE_NV_DEV("NFORCE-MCP51", ATA_UDMA6),
/* 16 */ DECLARE_NV_DEV("NFORCE-MCP55", ATA_UDMA6),
/* 17 */ DECLARE_NV_DEV("NFORCE-MCP61", ATA_UDMA6),
/* 18 */ DECLARE_NV_DEV("NFORCE-MCP65", ATA_UDMA6),
/* 19 */ DECLARE_NV_DEV("NFORCE-MCP67", ATA_UDMA6),
/* 20 */ DECLARE_NV_DEV("NFORCE-MCP73", ATA_UDMA6),
/* 21 */ DECLARE_NV_DEV("NFORCE-MCP77", ATA_UDMA6),
/* 22 */ DECLARE_AMD_DEV("AMD5536", ATA_SWDMA2, ATA_UDMA5),
/* 0: AMD7401 */ DECLARE_AMD_DEV(0x00, ATA_UDMA2),
/* 1: AMD7409 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA4),
/* 2: AMD7411/7441 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5),
/* 3: AMD8111 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA6),
/* 4: NFORCE */ DECLARE_NV_DEV(ATA_UDMA5),
/* 5: >= NFORCE2 */ DECLARE_NV_DEV(ATA_UDMA6),
/* 6: AMD5536 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5),
};
static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
......@@ -274,7 +260,7 @@ static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_
if (dev->revision <= 7)
d.swdma_mask = 0;
d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
} else if (idx == 4) {
} else if (idx == 3) {
if (dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
d.udma_mask = ATA_UDMA5;
......@@ -308,30 +294,30 @@ static const struct pci_device_id amd74xx_pci_tbl[] = {
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 2 },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 3 },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 4 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 5 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 6 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 7 },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 2 },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 3 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 4 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 5 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 5 },
#ifdef CONFIG_BLK_DEV_IDE_SATA
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), 8 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), 5 },
#endif
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 9 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 10 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 5 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 5 },
#ifdef CONFIG_BLK_DEV_IDE_SATA
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), 11 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), 12 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), 5 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), 5 },
#endif
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 13 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 14 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 15 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 16 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 17 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 18 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 19 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 20 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 21 },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 22 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 5 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 5 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 5 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 5 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 5 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 5 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 5 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 5 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 5 },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 6 },
{ 0, },
};
MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
......
......@@ -11,6 +11,8 @@
#include <linux/ide.h>
#include <linux/init.h>
#define DRV_NAME "atiixp"
#define ATIIXP_IDE_PIO_TIMING 0x40
#define ATIIXP_IDE_MDMA_TIMING 0x44
#define ATIIXP_IDE_PIO_CONTROL 0x48
......@@ -137,16 +139,17 @@ static const struct ide_port_ops atiixp_port_ops = {
};
static const struct ide_port_info atiixp_pci_info[] __devinitdata = {
{ /* 0 */
.name = "ATIIXP",
{ /* 0: IXP200/300/400/700 */
.name = DRV_NAME,
.enablebits = {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
.port_ops = &atiixp_port_ops,
.host_flags = IDE_HFLAG_LEGACY_IRQS,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA5,
},{ /* 1 */
.name = "SB600_PATA",
},
{ /* 1: IXP600 */
.name = DRV_NAME,
.enablebits = {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
.port_ops = &atiixp_port_ops,
.host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_LEGACY_IRQS,
......
......@@ -19,6 +19,8 @@
#include <asm/io.h>
#define DRV_NAME "cmd64x"
#define CMD_DEBUG 0
#if CMD_DEBUG
......@@ -407,8 +409,8 @@ static const struct ide_dma_ops cmd648_dma_ops = {
};
static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
{ /* 0 */
.name = "CMD643",
{ /* 0: CMD643 */
.name = DRV_NAME,
.init_chipset = init_chipset_cmd64x,
.enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
.port_ops = &cmd64x_port_ops,
......@@ -418,8 +420,9 @@ static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
.pio_mask = ATA_PIO5,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = 0x00, /* no udma */
},{ /* 1 */
.name = "CMD646",
},
{ /* 1: CMD646 */
.name = DRV_NAME,
.init_chipset = init_chipset_cmd64x,
.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
.chipset = ide_cmd646,
......@@ -429,8 +432,9 @@ static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
.pio_mask = ATA_PIO5,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA2,
},{ /* 2 */
.name = "CMD648",
},
{ /* 2: CMD648 */
.name = DRV_NAME,
.init_chipset = init_chipset_cmd64x,
.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
.port_ops = &cmd64x_port_ops,
......@@ -439,8 +443,9 @@ static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
.pio_mask = ATA_PIO5,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA4,
},{ /* 3 */
.name = "CMD649",
},
{ /* 3: CMD649 */
.name = DRV_NAME,
.init_chipset = init_chipset_cmd64x,
.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
.port_ops = &cmd64x_port_ops,
......
......@@ -41,6 +41,8 @@
#include <linux/ide.h>
#include <linux/dma-mapping.h>
#define DRV_NAME "cs5520"
struct pio_clocks
{
int address;
......@@ -92,18 +94,11 @@ static const struct ide_port_ops cs5520_port_ops = {
.set_dma_mode = cs5520_set_dma_mode,
};
#define DECLARE_CS_DEV(name_str) \
{ \
.name = name_str, \
.port_ops = &cs5520_port_ops, \
.host_flags = IDE_HFLAG_ISA_PORTS | \
IDE_HFLAG_CS5520, \
.pio_mask = ATA_PIO4, \
}
static const struct ide_port_info cyrix_chipsets[] __devinitdata = {
/* 0 */ DECLARE_CS_DEV("Cyrix 5510"),
/* 1 */ DECLARE_CS_DEV("Cyrix 5520")
static const struct ide_port_info cyrix_chipset __devinitdata = {
.name = DRV_NAME,
.port_ops = &cs5520_port_ops,
.host_flags = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_CS5520,
.pio_mask = ATA_PIO4,
};
/*
......@@ -114,7 +109,7 @@ static const struct ide_port_info cyrix_chipsets[] __devinitdata = {
static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
const struct ide_port_info *d = &cyrix_chipsets[id->driver_data];
const struct ide_port_info *d = &cyrix_chipset;
hw_regs_t hw[4], *hws[] = { NULL, NULL, NULL, NULL };
ide_setup_pci_noise(dev, d);
......@@ -128,7 +123,8 @@ static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_devic
}
pci_set_master(dev);
if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
printk(KERN_WARNING "cs5520: No suitable DMA available.\n");
printk(KERN_WARNING "%s: No suitable DMA available.\n",
d->name);
return -ENODEV;
}
......
......@@ -22,6 +22,8 @@
#include <asm/io.h>
#define DRV_NAME "cs5530"
/*
* Here are the standard PIO mode 0-4 timings for each "format".
* Format-0 uses fast data reg timings, with slower command reg timings.
......@@ -243,7 +245,7 @@ static const struct ide_port_ops cs5530_port_ops = {
};
static const struct ide_port_info cs5530_chipset __devinitdata = {
.name = "CS5530",
.name = DRV_NAME,
.init_chipset = init_chipset_cs5530,
.init_hwif = init_hwif_cs5530,
.port_ops = &cs5530_port_ops,
......
......@@ -26,6 +26,8 @@
#include <linux/pci.h>
#include <linux/ide.h>
#define DRV_NAME "cs5535"
#define MSR_ATAC_BASE 0x51300000
#define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0)
#define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01)
......@@ -169,7 +171,7 @@ static const struct ide_port_ops cs5535_port_ops = {
};
static const struct ide_port_info cs5535_chipset __devinitdata = {
.name = "CS5535",
.name = DRV_NAME,
.port_ops = &cs5535_port_ops,
.host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE,
.pio_mask = ATA_PIO4,
......
......@@ -48,6 +48,8 @@
#include <asm/io.h>
#define DRV_NAME "cy82c693"
/* the current version */
#define CY82_VERSION "CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"
......@@ -398,7 +400,7 @@ static const struct ide_port_ops cy82c693_port_ops = {
};
static const struct ide_port_info cy82c693_chipset __devinitdata = {
.name = "CY82C693",
.name = DRV_NAME,
.init_chipset = init_chipset_cy82c693,
.init_iops = init_iops_cy82c693,
.port_ops = &cy82c693_port_ops,
......
......@@ -27,6 +27,8 @@
#include <linux/ide.h>
#include <linux/init.h>
#define DRV_NAME "ide_pci_generic"
static int ide_generic_all; /* Set to claim all devices */
module_param_named(all_generic_ide, ide_generic_all, bool, 0444);
......@@ -34,9 +36,9 @@ MODULE_PARM_DESC(all_generic_ide, "IDE generic will claim all unknown PCI IDE st
#define IDE_HFLAGS_UMC (IDE_HFLAG_NO_DMA | IDE_HFLAG_FORCE_LEGACY_IRQS)
#define DECLARE_GENERIC_PCI_DEV(name_str, extra_flags) \
#define DECLARE_GENERIC_PCI_DEV(extra_flags) \
{ \
.name = name_str, \
.name = DRV_NAME, \
.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA | \
extra_flags, \
.swdma_mask = ATA_SWDMA2, \
......@@ -45,10 +47,11 @@ MODULE_PARM_DESC(all_generic_ide, "IDE generic will claim all unknown PCI IDE st
}
static const struct ide_port_info generic_chipsets[] __devinitdata = {
/* 0 */ DECLARE_GENERIC_PCI_DEV("Unknown", 0),
/* 0: Unknown */
DECLARE_GENERIC_PCI_DEV(0),
{ /* 1 */
.name = "NS87410",
{ /* 1: NS87410 */
.name = DRV_NAME,
.enablebits = { {0x43, 0x08, 0x08}, {0x47, 0x08, 0x08} },
.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA,
.swdma_mask = ATA_SWDMA2,
......@@ -56,17 +59,15 @@ static const struct ide_port_info generic_chipsets[] __devinitdata = {
.udma_mask = ATA_UDMA6,
},
/* 2 */ DECLARE_GENERIC_PCI_DEV("SAMURAI", 0),
/* 3 */ DECLARE_GENERIC_PCI_DEV("HT6565", 0),
/* 4 */ DECLARE_GENERIC_PCI_DEV("UM8673F", IDE_HFLAGS_UMC),
/* 5 */ DECLARE_GENERIC_PCI_DEV("UM8886A", IDE_HFLAGS_UMC),
/* 6 */ DECLARE_GENERIC_PCI_DEV("UM8886BF", IDE_HFLAGS_UMC),
/* 7 */ DECLARE_GENERIC_PCI_DEV("HINT_IDE", 0),
/* 8 */ DECLARE_GENERIC_PCI_DEV("VIA_IDE", IDE_HFLAG_NO_AUTODMA),
/* 9 */ DECLARE_GENERIC_PCI_DEV("OPTI621V", IDE_HFLAG_NO_AUTODMA),
{ /* 10 */
.name = "VIA8237SATA",
/* 2: SAMURAI / HT6565 / HINT_IDE */
DECLARE_GENERIC_PCI_DEV(0),
/* 3: UM8673F / UM8886A / UM8886BF */
DECLARE_GENERIC_PCI_DEV(IDE_HFLAGS_UMC),
/* 4: VIA_IDE / OPTI621V / Piccolo010{2,3,5} */
DECLARE_GENERIC_PCI_DEV(IDE_HFLAG_NO_AUTODMA),
{ /* 5: VIA8237SATA */
.name = DRV_NAME,
.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
IDE_HFLAG_OFF_BOARD,
.swdma_mask = ATA_SWDMA2,
......@@ -74,12 +75,8 @@ static const struct ide_port_info generic_chipsets[] __devinitdata = {
.udma_mask = ATA_UDMA6,
},
/* 11 */ DECLARE_GENERIC_PCI_DEV("Piccolo0102", IDE_HFLAG_NO_AUTODMA),
/* 12 */ DECLARE_GENERIC_PCI_DEV("Piccolo0103", IDE_HFLAG_NO_AUTODMA),
/* 13 */ DECLARE_GENERIC_PCI_DEV("Piccolo0105", IDE_HFLAG_NO_AUTODMA),
{ /* 14 */
.name = "Revolution",
{ /* 6: Revolution */
.name = DRV_NAME,
.host_flags = IDE_HFLAG_CLEAR_SIMPLEX |
IDE_HFLAG_TRUST_BIOS_FOR_DMA |
IDE_HFLAG_OFF_BOARD,
......@@ -147,20 +144,20 @@ out:
static const struct pci_device_id generic_pci_tbl[] = {
{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87410), 1 },
{ PCI_VDEVICE(PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE), 2 },
{ PCI_VDEVICE(HOLTEK, PCI_DEVICE_ID_HOLTEK_6565), 3 },
{ PCI_VDEVICE(UMC, PCI_DEVICE_ID_UMC_UM8673F), 4 },
{ PCI_VDEVICE(UMC, PCI_DEVICE_ID_UMC_UM8886A), 5 },
{ PCI_VDEVICE(UMC, PCI_DEVICE_ID_UMC_UM8886BF), 6 },
{ PCI_VDEVICE(HINT, PCI_DEVICE_ID_HINT_VXPROII_IDE), 7 },
{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C561), 8 },
{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C558), 9 },
{ PCI_VDEVICE(HOLTEK, PCI_DEVICE_ID_HOLTEK_6565), 2 },
{ PCI_VDEVICE(UMC, PCI_DEVICE_ID_UMC_UM8673F), 3 },
{ PCI_VDEVICE(UMC, PCI_DEVICE_ID_UMC_UM8886A), 3 },
{ PCI_VDEVICE(UMC, PCI_DEVICE_ID_UMC_UM8886BF), 3 },
{ PCI_VDEVICE(HINT, PCI_DEVICE_ID_HINT_VXPROII_IDE), 2 },
{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C561), 4 },
{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C558), 4 },
#ifdef CONFIG_BLK_DEV_IDE_SATA
{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_8237_SATA), 10 },
{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_8237_SATA), 5 },
#endif
{ PCI_VDEVICE(TOSHIBA, PCI_DEVICE_ID_TOSHIBA_PICCOLO), 11 },
{ PCI_VDEVICE(TOSHIBA, PCI_DEVICE_ID_TOSHIBA_PICCOLO_1), 12 },
{ PCI_VDEVICE(TOSHIBA, PCI_DEVICE_ID_TOSHIBA_PICCOLO_2), 13 },
{ PCI_VDEVICE(NETCELL, PCI_DEVICE_ID_REVOLUTION), 14 },
{ PCI_VDEVICE(TOSHIBA, PCI_DEVICE_ID_TOSHIBA_PICCOLO), 4 },
{ PCI_VDEVICE(TOSHIBA, PCI_DEVICE_ID_TOSHIBA_PICCOLO_1), 4 },
{ PCI_VDEVICE(TOSHIBA, PCI_DEVICE_ID_TOSHIBA_PICCOLO_2), 4 },
{ PCI_VDEVICE(NETCELL, PCI_DEVICE_ID_REVOLUTION), 6 },
/*
* Must come last. If you add entries adjust
* this table and generic_chipsets[] appropriately.
......
......@@ -33,6 +33,8 @@
#include <linux/init.h>
#include <linux/ide.h>
#define DRV_NAME "hpt34x"
#define HPT343_DEBUG_DRIVE_INFO 0
static void hpt34x_set_mode(ide_drive_t *drive, const u8 speed)
......@@ -126,15 +128,15 @@ static const struct ide_port_ops hpt34x_port_ops = {
IDE_HFLAG_NO_AUTODMA)
static const struct ide_port_info hpt34x_chipsets[] __devinitdata = {
{ /* 0 */
.name = "HPT343",
{ /* 0: HPT343 */
.name = DRV_NAME,
.init_chipset = init_chipset_hpt34x,
.port_ops = &hpt34x_port_ops,
.host_flags = IDE_HFLAGS_HPT34X | IDE_HFLAG_NON_BOOTABLE,
.pio_mask = ATA_PIO5,
},
{ /* 1 */
.name = "HPT345",
{ /* 1: HPT345 */
.name = DRV_NAME,
.init_chipset = init_chipset_hpt34x,
.port_ops = &hpt34x_port_ops,
.host_flags = IDE_HFLAGS_HPT34X | IDE_HFLAG_OFF_BOARD,
......
......@@ -131,6 +131,8 @@
#include <asm/uaccess.h>
#include <asm/io.h>
#define DRV_NAME "hpt366"
/* various tuning parameters */
#define HPT_RESET_STATE_ENGINE
#undef HPT_DELAY_INTERRUPT
......@@ -1362,7 +1364,7 @@ static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
if (dev2->irq != dev->irq) {
/* FIXME: we need a core pci_set_interrupt() */
dev2->irq = dev->irq;
printk(KERN_INFO "HPT374 %s: PCI config space interrupt "
printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt "
"fixed\n", pci_name(dev2));
}
}
......@@ -1398,7 +1400,7 @@ static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
if (pin1 != pin2 && dev->irq == dev2->irq) {
printk(KERN_INFO "HPT36x %s: onboard version of chipset, "
printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, "
"pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2);
return 1;
}
......@@ -1454,8 +1456,8 @@ static const struct ide_dma_ops hpt36x_dma_ops = {
};
static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
{ /* 0 */
.name = "HPT36x",
{ /* 0: HPT36x */
.name = DRV_NAME,
.init_chipset = init_chipset_hpt366,
.init_hwif = init_hwif_hpt366,
.init_dma = init_dma_hpt366,
......@@ -1471,53 +1473,9 @@ static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
.host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
},{ /* 1 */
.name = "HPT372A",
.init_chipset = init_chipset_hpt366,
.init_hwif = init_hwif_hpt366,
.init_dma = init_dma_hpt366,
.enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
.port_ops = &hpt3xx_port_ops,
.dma_ops = &hpt37x_dma_ops,
.host_flags = IDE_HFLAGS_HPT3XX,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
},{ /* 2 */
.name = "HPT302",
.init_chipset = init_chipset_hpt366,
.init_hwif = init_hwif_hpt366,
.init_dma = init_dma_hpt366,
.enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
.port_ops = &hpt3xx_port_ops,
.dma_ops = &hpt37x_dma_ops,
.host_flags = IDE_HFLAGS_HPT3XX,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
},{ /* 3 */
.name = "HPT371",
.init_chipset = init_chipset_hpt366,
.init_hwif = init_hwif_hpt366,
.init_dma = init_dma_hpt366,
.enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
.port_ops = &hpt3xx_port_ops,
.dma_ops = &hpt37x_dma_ops,
.host_flags = IDE_HFLAGS_HPT3XX,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
},{ /* 4 */
.name = "HPT374",
.init_chipset = init_chipset_hpt366,
.init_hwif = init_hwif_hpt366,
.init_dma = init_dma_hpt366,
.enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
.udma_mask = ATA_UDMA5,
.port_ops = &hpt3xx_port_ops,
.dma_ops = &hpt37x_dma_ops,
.host_flags = IDE_HFLAGS_HPT3XX,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
},{ /* 5 */
.name = "HPT372N",
},
{ /* 1: HPT3xx */
.name = DRV_NAME,
.init_chipset = init_chipset_hpt366,
.init_hwif = init_hwif_hpt366,
.init_dma = init_dma_hpt366,
......@@ -1583,9 +1541,10 @@ static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_devic
break;
}
d = hpt366_chipsets[idx];
printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name);
d = hpt366_chipsets[min_t(u8, idx, 1)];
d.name = info->chip_name;
d.udma_mask = info->udma_mask;
/* fixup ->dma_ops for HPT370/HPT370A */
......
......@@ -14,6 +14,8 @@
#include <linux/ide.h>
#include <linux/init.h>
#define DRV_NAME "it8213"
/**
* it8213_set_pio_mode - set host controller for PIO mode
* @drive: drive
......@@ -156,7 +158,7 @@ static const struct ide_port_ops it8213_port_ops = {
};
static const struct ide_port_info it8213_chipset __devinitdata = {
.name = "IT8213",
.name = DRV_NAME,
.enablebits = { {0x41, 0x80, 0x80} },
.port_ops = &it8213_port_ops,
.host_flags = IDE_HFLAG_SINGLE,
......
......@@ -67,6 +67,8 @@
#include <linux/ide.h>
#include <linux/init.h>
#define DRV_NAME "it821x"
struct it821x_dev
{
unsigned int smart:1, /* Are we in smart raid mode */
......@@ -569,7 +571,7 @@ static void __devinit init_hwif_it821x(ide_hwif_t *hwif)
idev->timing10 = 1;
hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
if (idev->smart == 0)
printk(KERN_WARNING "it821x %s: revision 0x10, "
printk(KERN_WARNING DRV_NAME " %s: revision 0x10, "
"workarounds activated\n", pci_name(dev));
}
......@@ -610,12 +612,12 @@ static unsigned int __devinit init_chipset_it821x(struct pci_dev *dev, const cha
/* Force the card into bypass mode if so requested */
if (it8212_noraid) {
printk(KERN_INFO "it821x %s: forcing bypass mode\n",
printk(KERN_INFO DRV_NAME " %s: forcing bypass mode\n",
pci_name(dev));
it8212_disable_raid(dev);
}
pci_read_config_byte(dev, 0x50, &conf);
printk(KERN_INFO "it821x %s: controller in %s mode\n",
printk(KERN_INFO DRV_NAME " %s: controller in %s mode\n",
pci_name(dev), mode[conf & 1]);
return 0;
}
......@@ -629,7 +631,7 @@ static const struct ide_port_ops it821x_port_ops = {
};
static const struct ide_port_info it821x_chipset __devinitdata = {
.name = "IT821X",
.name = DRV_NAME,
.init_chipset = init_chipset_it821x,
.init_hwif = init_hwif_it821x,
.port_ops = &it821x_port_ops,
......@@ -652,7 +654,7 @@ static int __devinit it821x_init_one(struct pci_dev *dev, const struct pci_devic
itdevs = kzalloc(2 * sizeof(*itdevs), GFP_KERNEL);
if (itdevs == NULL) {
printk(KERN_ERR "it821x %s: out of memory\n", pci_name(dev));
printk(KERN_ERR DRV_NAME " %s: out of memory\n", pci_name(dev));
return -ENOMEM;
}