Commit b343d002 authored by Yuval Mintz's avatar Yuval Mintz Committed by David S. Miller

bnx2x: mask CPL_OF interrupt

Unmasked interrupt caused "FATAL HW block attention set2 0x20" messages
to erroneously appear, as the associated interrupt is fully recoverable.
Signed-off-by: default avatarYuval Mintz <yuvalmin@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 9b341bb1
...@@ -6059,6 +6059,8 @@ static int bnx2x_int_mem_test(struct bnx2x *bp) ...@@ -6059,6 +6059,8 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
static void bnx2x_enable_blocks_attention(struct bnx2x *bp) static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
{ {
u32 val;
REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
if (!CHIP_IS_E1x(bp)) if (!CHIP_IS_E1x(bp))
REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
...@@ -6092,17 +6094,14 @@ static void bnx2x_enable_blocks_attention(struct bnx2x *bp) ...@@ -6092,17 +6094,14 @@ static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
if (CHIP_REV_IS_FPGA(bp)) val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
else if (!CHIP_IS_E1x(bp)) PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, if (!CHIP_IS_E1x(bp))
(PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
| PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
| PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
| PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
| PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
else
REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
......
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